PCI to SH-3 AN Hitachi SH3 to PCI bus

PCI to SH-3 AN Hitachi SH3 to PCI bus Version 1.0 Application Note FEATURES GENERAL DESCRIPTION Complete Application Note for designing a PCI adapter or embedded system based on the Hitachi SH-3 including: Detailed Design Description OrCad Schematics Verilog HDL Source Code Superior PCI performance based on PCI 9080 bus master interface chip which supports: PCI burst master, DMA and slave cycles PCI configuration cycles Asynchronous PCI/ SH-3 operation I 2 O Messaging Unit Combined with PLX s I2OSDK, provides a powerful tool for developing an SH-3-based I 2 O IOP This application note describes how to interface the Hitachi SH-3 CPU to the PCI bus using the PLX PCI 9080 "PCI to Local Bus Bridge" IC in a PCI target/initiator board configuration with a Squall daughtercard connector for prototype debugging. The PCI 9080 has Direct Master, DMA and Direct Slave data transfer capabilities. The Direct Master mode allows a device (SH-3) on the Local Bus to perform memory, I/O, and configuration cycles to the PCI bus. The Direct Slave gives a master device on the PCI bus the ability to access memory on the Local Bus. The PCI 9080 allows the Local Bus to run asynchronously to the PCI bus through the use of bidirectional FIFOs. +3.3V Power Supply RS232 Port 9 way D 2 x 4MBit SDRAM (32 bits wide) SH3 CPU SH3 Bus +5V/+3.3V System Split Level converters Level converters 32K x 8 fast EPROM CPLD 128K x 32 fast SRAM Squall Connector 9080 Bus BIOS Flash ROM PLX PCI9080 EEPROM PCI Bus The Hitachi SH-3 CPU to the PCI bus using the PLX PCI 9080 PCI to Local Bus Bridge IC PLX Technology, Inc., 1997 PLX Technology, Inc, 390 Potrero Avenue, Sunnyvale, CA 94086, Phone 408-774-9060, Fax 408-774-2169 Products and Company names are trademarks/registered trademarks of their respective holders

Table of Contents: 1. INTRODUCTION... 3 2. OVERVIEW... 3 3. SYSTEM SPECIFICATION... 3 3.1 SH3 CPU... 3 3.2 CLOCK GENERATION... 4 3.3 SH3 CPU LOCAL SUB-SYSTEM... 5 3.4 BUS CONTROLLER... 5 3.5 9080 LOCAL BUS DEVICES... 6 3.6 SQUALL II CONNECTOR... 6 3.7 PCI BUS INTERFACE... 7 4. CIRCUIT DESCRIPTION... 8 4.1 SCHEMATIC SHEET 1... 8 4.2 SCHEMATIC SHEET 2... 8 4.3 SCHEMATIC SHEET 3... 8 4.4 SCHEMATIC SHEET 4... 8 4.5 SCHEMATIC SHEET 5... 8 4.6 SCHEMATIC SHEET 6... 8 4.7 SCHEMATIC SHEET 7... 8 4.8 SCHEMATIC SHEET 8... 8 5. DOCUMENT HISTORY... 9 6. LOGIC SOURCE CODE AND SCHEMATICS... 9 2

1. INTRODUCTION This document defines the specification for a PCI target/initiator board based on the PLX Technology PCI9080 device. The card contains its own on-board CPU, a Hitachi SH3. A Squall daughtercard connector is provided for prototyping. Refer to the following documents for further information: PCI Local Bus Specification v2.1 PLX PCI 9080 Data Sheet Hitachi SH3 Data Sheet and appropriate reference manuals. Cyclone Microsystems Squall II Module Interface Specification. 2. OVERVIEW The SH3 CPU can access the 128K of fast SRAM, the BIOS ROM and perform direct master transfers over the PCI bus. It also obviously has access to its local EPROM, SDRAM and serial port resources. The PCI9080 allows the PCI host to make direct slave transfers to the 128K of fast SRAM and the BIOS ROM. The 9080 can also perform DMA transfers into and out of the fast SRAM and EPROM. However, the 9080 cannot access any of the SH3 s local resources: EPROM; SDRAM and serial port. 3. SYSTEM SPECIFICATION The PCI card is Universal, in that it will operate in both +5V and +3.3V PCI slots. It is a full length PCI card. A +3.3V power supply is provided on the card to allow operation in typical, +5V only PCI bus slots. The SH3 CPU has a self-contained core system consisting of 1 MByte of 32 bit wide Synchronous DRAM, 32 Kbytes of 8 bit wide boot EPROM and an RS232 debug port. A +5V, socketed DIP EPROM is used for the SH3 boot code. The PCI interface, 128K x 32 fast SRAM, BIOS ROM and Squall Connector are isolated from the SH3 core system both logically and physically. The logical split allows the PCI9080 to access the SRAM or BIOS ROM without interfering with the SH3 s operation, assuming that the SH3 does not want to access either of these functions. The physical split forms a natural +5V to +3.3V barrier and provides buffering for the SH3 bus drivers. 3.1 SH3 CPU The SH3 is operated in Clock Mode 7 (CKIO as an input) with a full speed (x1) clock. It is configured to operate in little-endian mode only and is hard-configured to have an 8 bit boot device (the 32K by 8 EPROM). The 9080/SH3 Reference Platform both the 9080 and SH3 are clocked from the same clock source at up to 40MHz. Allocation of the SH3 s chip selects is as follows: 3

Chip Select Device SH3 [A25..A24] Bus Width Wait States CS0 SH3 Boot EPROM All 8 3 CS1 PCI Bus Master Transfers All 32 1 + WAIT CS2 PCI9080 Register access All 32 1 + WAIT CS3 Synchronous DRAM All 32 see below CS4 PCI BIOS ROM [0,x] 16 1 + WAIT 2096 CPLD registers [1,1] CS5 Local Bus fast SRAM All 32 1 + WAIT CS6 Squall Module All 8/16/32 1 + WAIT Notes: 1. As can be seen, chip select 5 is further divided by decoding the upper 2 address lines of the SH3 s bus. 2. The SH3 PCI card is designed to use -15 SDRAM s. Recommended SH3 register settings are: WCR1=0; WCR2=65EB hex; MCR=973C hex. As the SH3 only has an external 26 bit address bus a mapping register is provided to allow it to manipulate 9080 local address bus bits 26 through 28. 9080 local address bus bits 29 through 31 are automatically driven to the correct value for SH3 accesses, defined by the currently active SH3 chip select (see Section 3.5). Details of the SH3 address map register are as follows: SH3 Address Mapping Register Bits Function RESET state Register Type 0:2 Local Bus Address Bits 26:28 [0,0,0] read/write The SH3 Address Mapping Register is mapped to SH3 chip select 4 (CS4) with [A25..A23] == [1,1,0]. 3.2 Clock Generation A wide range of CPU clock frequencies can be selected from a PLL controlled AV9154 clock generator: JP2 JP3 pins 5-6 JP3 pins 3-4 JP3 pins 1-2 Clock Output (MHz) 1-2 16 1-2 40 1-2 33.3 1-2 25 1-2 60 1 1-2 20 1-2 66.6 1 1-2 50 1 2-3 8 1 2-3 20 2-3 16.6 2-3 12.5 1 2-3 30 2-3 10 1 2-3 33.3 2-3 25 Note 1: These frequencies should not be used (see below). 4

The high speed clocks are distributed around the board using low skew, PLL based clock buffers. The buffers require their compensation networks setting, depending on the input clock frequency, via a set of jumpers: JP1 Setting CPU Clock Frequency (MHz) range 1-2 shorted ONLY 40-83 2-3 shorted ONLY 25-50 3-4 shorted ONLY 15-30 The clock buffers therefore restrict the Reference Platform operating frequency to 15MHz minimum, while the 9080 itself places an upper limit of 40MHz. 3.3 SH3 CPU Local Sub-System The local CPU sub-system comprises a 32K by 8 boot EPROM, 1 MByte of 32 bit wide SDRAM and the necessary RS232 level converters for the SH3 s own serial port. The sub-system is buffered from the rest of the card by 74LVT16245 buffers, which also provide the necessary +3.3V to +5V level conversion. As the SH3 does not have a natural burst mode bus, it will not be provided with burst access capability to the 9080 or any other devices on the 9080 s Local Bus. 3.4 Bus Controller The Bus Controller will be implemented with an in-system-programmable CPLD. This device performs a number of different functions: Bus arbiter for the PCI9080 bus Controller for the fast SRAM PCI9080 local bus state machine for SH3 master accesses PCI9080 bus timeout Interrupt controller for the SH3 Miscellaneous control and decode functions The interrupt controller mappings provided by the Bus Controller are as follows: Interrupt Source SH3 [IRL3..IRL0] code Squall IRQ0 [0,0,0,1] Squall IRQ1 [0,0,1,0] PCI9080 local interrupt output [0,1,0,0] Please refer to the source code for the device for a more detailed description of its operation. Single-in-line header JP7 is pin-compatible with the standard Lattice download cable and allows the 2096 to be programmed in-system. Two jumpers associated with the 2096 control the card s responses to Reset inputs: JP8 setting JP9 setting RESET effect None Asserts Manual Reset permanently RESET effect PCI Bus Reset asserts SH3 reset PCI Bus Reset only affects PCI9080 5

3.5 9080 Local Bus Devices The 9080 Local Bus has 128K by 32 of fast, asynchronous SRAM which can be burst accessed at a 2-2-2-2 rate. Also on the Local Bus is the BIOS Flash ROM can also be burst accessed, but at a 4-4-4-4 rate (60ns Flash EPROM assumed). The BIOS Flash EPROM is an Intel 4 MBit Boot-Block type device, and can be programmed in-circuit. The Flash EPROM s programming voltage is +5V. All 9080 Local Bus devices are allocated 256 MByte address blocks (as per i960) and these are defined as follows: Device Width Local Address Bus Bits [A31..A29] Base Address SH3 Chip Select Mapping PCI9080 Registers 32 bit [1,1,1] E0000000 CS2 UNALLOCATED [1,1,0] C0000000 Squall Module [1,0,1] A0000000 CS6 PCI Bus Master accesses 32 bit [1,0,0] 80000000 CS1 UNALLOCATED [0,1,1] 60000000 Fast SRAM array 32 bit [0,1,0] 40000000 CS5 BIOS Flash EPROM 16 bit [0,0,1] 20000000 CS4 UNALLOCATED [0,0,0] 00000000 3.6 Squall II Connector The Squall II Module interface provides I/O expansion and flexibility by allowing customers to add a wide range of I/O interfaces. The Squall II Module interface is an open domain specification available from Cyclone Microsystems. The interface uses 32 bit data transfers to communicate with the processor or the shared memory. DMA controllers in the Squall II Modules can access the shared packet memory. The specification is published by Cyclone and is available from their web site (www.cyclone.com): Squall II Module Interface Specification Squall II modules are supported on the 9080/SH3 Reference Platform via a Squall Connector. The Squall II modules can be either bus targets or bus masters. All Squall modules have an on-board EEPROM containing configuration information. This EEPROM is physically accessed via a 2-wire interface which is implemented through an SH3 bit I/O port. Software implementing the EEPROM interface protocol must be run on the SH3 in order to read or write the EEPROM. Details of the EEPROM bit I/O port are as follows: 2 wire Serial Control Register Write Bit Function RESET state 0 2 wire Serial Controller SCL 1 0 - Turn on open collector driver 1 - Turn off open collector driver 1 2 wire Serial Controller SDA 0 - Turn on open collector driver 1 - Turn off open collector driver 1 6

2 wire Serial Control Register Read Bit Function 0 2 wire Serial Controller SCL signal wire value 1 2 wire Serial Controller SDA signal wire value Both read and write registers are mapped to SH3 chip select 4 (CS4) with [A25..A23] == [1,1,1]. There are a few points to note concerning the Squall bus interface: Squall modules may be limited to a 33MHz bus speed. The user must set the 9080/SH3 Reference Design clock selection jumpers (Section 3.2) accordingly. The SH3 has a very basic interrupt controller and only level triggered interrupts are supported. The SH3 provides no mechanism to read a specific byte within a multi-byte word (it has no Byte Enables). It can of course write to any byte within a multi-byte word (it has Write Enable outputs). It is therefore not possible to fully emulate the i960 bus interface from the SH3 CPU. The SH3 has no LOCK support. 3.7 PCI Bus Interface This is based around the PLX Technology PCI9080 device, configured in Cx mode. The local bus of the 9080 is synchronously clocked at the same rate as the SH3 CPU. This allows fully synchronous control, removing any resynchronisation delays. The 9080 has a local, socketed DIP EEPROM. The following user selectable jumpers are also be provided: JP4 setting JP5 setting 9080 No Boot effect Local Init Done status bit must be set to true by a local bus master (e.g. SH3) 9080 will automatically set Local Init Done status bit to true PCI9080 EEPROM DO Pin effect No effect EEPROM DO pin is shorted to zero volts. Allows a 9080/SH3 Reference Design Board to boot on a PCI PC with a blank EEPROM fitted (otherwise the PCI BIOS will not enable the card). The jumper short must then be removed to allow the EEPROM to be programmed and to allow normal operation. 7

JP6 setting PCI9080 EEPROM Part Type Selection 93CS46 93CS56 4. CIRCUIT DESCRIPTION Please refer to the circuit diagrams for the 9080/SH3 Reference Design. 4.1 Schematic Sheet 1 This sheet shows the function blocks of the card and their interconnections. 4.2 Schematic Sheet 2 The SH3 CPU U3 is shown on this sheet. The QuickSwitch device U4 provides +5V to +3.3V level conversion for a number of signals, while introducing virtually no propagation delay. The resistor packs limit signal underand over-shoot on the SH3 outputs. 4.3 Schematic Sheet 3 This sheet contains the SDRAM array, the boot EPROM, the RS232 level converter and the main address and data buffers. The buffers are LVT-style devices, providing the main +3.3V to +5V (bi-directional) level conversion. Buffer U9 also provides level conversion between the +5V EPROM and the +3.3V main SH3 data bus. 4.4 Schematic Sheet 4 The control CPLD U24 is shown on this sheet with its associated programming connector JP7. A number of configuration jumpers which are used by the CPLD are also shown, along with the local system reset generator U22 and the two diagnostic LED s. The ripple counter U23 is used by the CPLD for its bus time-out function, saving considerable internal register resources. For a more detailed description of the CPLD s operation, please refer to its design source file. 4.5 Schematic Sheet 5 The Squall II Module connector and the fast SRAM array are shown here. 4.6 Schematic Sheet 6 This sheet shows the PCI9080 and the PCI bus edge connectors 4.7 Schematic Sheet 7 This sheet shows the AV9154 clock generator and the QS5V991 clock buffers. All clock outputs are +3.3V level, and the maximum skew between clock outputs is kept below 500ps. All clocks have series and AC termination networks to allow fine tuning of the clock waveforms. 4.8 Schematic Sheet 8 The majority of the card s decoupling capacitors are shown on this sheet, along with the +5V to +3.3V power converter. The power converter s output is limited to 1.25 Amps @ +3.3V. 8

Standard disk drive power input connector PL1 allow the card to be easily powered when not plugged into a PCI host (for test purposes only). 5. DOCUMENT HISTORY Rev Date Comments 0.0 29 May 97 Draft version 0.1 03 Jun 97 Modified in the light of PLX comments - major alterations 0.2 20 Jun 97 Updated as per development quotation 1.0 30 Jun 97 Completed initial release - document title modified Section 3.1 - Chip select mappings defined; SDRAM controller programming defined; Mapping register defined Section 3.2 - Component references updated Section 3.3 - Local SH3 RAM changed to SDRAM Section 3.5 - Flash EPROM burst rate altered; programming voltage defined Section 3.6 - Squall EEPROM interface defined. Technical notes tidied up Section 4 added - Circuit descriptions 6. LOGIC SOURCE CODE AND SCHEMATICS The appendices of the application note contain detailed logic source code and schematics. Except for the timing diagrams, this information is also available in source code from the PLX Technology web page (http://www.plxtech.com). 9