inst.eecs.berkeley.edu/~cs6c UC Berkeley CS6C : Machine Structures The Internet is broken?! The Clean Slate team at Stanford wants to revamp the Internet, making it safer (from viruses), more reliable and transparent (no spoofing). CS6C L27 Single-Cycle CPU Control () Lecture 26 Single-cycle CPU Control 27-3-2 Lecturer SOE Dan Garcia RIP John Backus 924-27 www.cs.berkeley.edu/~ddgarcia www.technologyreview.com/infotech/8397/ Garcia, Spring 27 UCB
Review: A Single Cycle Datapath We have everything except control signals RegDst Rd RegWr busw imm6 npc_sel Rs 5 5 Rw Ra Rb RegFile 6 5 Extender busa busb instr fetch unit zero Instruction<3:> <2:25> Rs ALUctr = ALU Data In <6:2> MemWr Rd <:5> WrEn Adr Data <:5> Imm6 MemtoReg CS6C L27 Single-Cycle CPU Control (2) ExtOp ALUSrc Garcia, Spring 27 UCB
Recap: Meaning of the Control Signals npc_sel: +4 PC < PC + 4 br PC < PC + 4 + n =next {SignExt(Im6), } Later in lecture: higher-level connection between mux and branch condition 4 PC Ext Adder Adder npc_sel PC Mux Inst Address CS6C L27 Single-Cycle CPU Control (3) imm6 Garcia, Spring 27 UCB
Recap: Meaning of the Control Signals ExtOp: zero, sign ALUsrc: regb; immed ALUctr: ADD, SUB, OR RegDst RegWr busw Rd imm6 Rs 5 5 Rw Ra Rb RegFile 6 ExtOp 5 Extender MemWr: write memory MemtoReg: ALU; Mem RegDst: rt ; rd RegWr: write register busa busb ALUSrc ALUctr MemtoReg MemWr ALU Data In WrEn Adr Data CS6C L27 Single-Cycle CPU Control (4) Garcia, Spring 27 UCB
RTL: The Add Instruction 3 26 2 6 6 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add rd, rs, rt MEM[PC] Fetch the instruction from memory R[rd] = R[rs] + R[rt] The actual operation PC = PC + 4 Calculate the next instruction s address CS6C L27 Single-Cycle CPU Control (5) Garcia, Spring 27 UCB
Instruction Fetch Unit at the Beginning of Add Fetch the instruction from Instruction memory: Instruction = MEM[PC] same for all instructions Inst Instruction<3:> 4 PC Ext Adder Adder npc_sel PC Mux Inst Address imm6 CS6C L27 Single-Cycle CPU Control (6) Garcia, Spring 27 UCB
The Single Cycle Datapath during Add 3 26 2 op rs rt rd shamt funct R[rd] = R[rs] + R[rt] RegDst= Rd RegWr= busw 6 npc_sel=+4 imm6 Rs 5 5 Rw Ra Rb RegFile 6 5 ExtOp=x Extender busa busb instr fetch unit zero 6 ALUSrc= Instruction<3:> <2:25> Rs Rd Imm6 ALUctr=ADD MemtoReg= = ALU Data In <6:2> <:5> MemWr= WrEn Adr Data <:5> CS6C L27 Single-Cycle CPU Control (7) Garcia, Spring 27 UCB
Instruction Fetch Unit at the End of Add PC = PC + 4 This is the same for all instructions except: Branch and Jump Inst 4 PC Ext npc_sel=+4 Adder Adder PC Mux Inst Address imm6 CS6C L27 Single-Cycle CPU Control (8) Garcia, Spring 27 UCB
Single Cycle Datapath during Or Immediate? 3 26 2 op rs rt immediate R[rt] = R[rs] OR ZeroExt[Imm6] RegDst= Rd RegWr= busw npc_sel= imm6 Rs 5 5 Rw Ra Rb RegFile 6 5 ExtOp= Extender busa busb 6 instr fetch unit zero ALUSrc= Instruction<3:> <2:25> Rs Rd Imm6 ALUctr= MemtoReg= = ALU Data In <6:2> MemWr= <:5> WrEn Adr Data <:5> CS6C L27 Single-Cycle CPU Control (9) Garcia, Spring 27 UCB
Single Cycle Datapath during Or Immediate? 3 26 2 op rs rt immediate R[rt] = R[rs] OR ZeroExt[Imm6] RegDst= Rd RegWr= busw npc_sel=+4 imm6 Rs 5 5 Rw Ra Rb RegFile 6 5 ExtOp=zero Extender busa busb 6 instr fetch unit zero ALUSrc= Instruction<3:> <2:25> Rs Rd Imm6 ALUctr=OR MemtoReg= = ALU Data In <6:2> MemWr= <:5> WrEn Adr Data <:5> CS6C L27 Single-Cycle CPU Control () Garcia, Spring 27 UCB
The Single Cycle Datapath during Load? 3 26 2 6 op rs rt immediate R[rt] = Data {R[rs] + SignExt[imm6]} RegDst= Rd RegWr= busw npc_sel= imm6 Rs 5 5 Rw Ra Rb RegFile 6 5 ExtOp= Extender busa busb instr fetch unit zero ALUSrc= Instruction<3:> <2:25> Rs Rd Imm6 ALUctr= MemtoReg= = ALU Data In <6:2> MemWr= <:5> WrEn Adr Data <:5> CS6C L27 Single-Cycle CPU Control () Garcia, Spring 27 UCB
The Single Cycle Datapath during Load 3 26 2 6 op rs rt immediate R[rt] = Data {R[rs] + SignExt[imm6]} RegDst= Rd RegWr= busw npc_sel=+4 imm6 Rs 5 5 Rw Ra Rb RegFile 6 5 ExtOp=sign Extender busa busb instr fetch unit zero ALUSrc= Instruction<3:> <2:25> Rs Rd Imm6 ALUctr=ADD MemtoReg= = ALU Data In <6:2> MemWr= <:5> WrEn Adr Data <:5> CS6C L27 Single-Cycle CPU Control (2) Garcia, Spring 27 UCB
The Single Cycle Datapath during Store? 3 26 2 op rs rt immediate Data {R[rs] + SignExt[imm6]} = R[rt] RegDst= Rd RegWr= busw npc_sel= imm6 Rs 5 5 Rw Ra Rb RegFile 6 5 ExtOp= Extender busa busb 6 instr fetch unit zero ALUSrc= Instruction<3:> <2:25> Rs Rd Imm6 ALUctr= MemtoReg= = ALU Data In <6:2> MemWr= <:5> WrEn Adr Data <:5> CS6C L27 Single-Cycle CPU Control (3) Garcia, Spring 27 UCB
The Single Cycle Datapath during Store 3 26 2 op rs rt immediate Data {R[rs] + SignExt[imm6]} = R[rt] RegDst=x Rd RegWr= busw npc_sel=+4 imm6 Rs 5 5 Rw Ra Rb RegFile 6 5 ExtOp=sign Extender busa busb 6 instr fetch unit zero ALUSrc= Instruction<3:> <2:25> Rs Rd Imm6 ALUctr=ADD MemtoReg=x = ALU Data In <6:2> MemWr= <:5> WrEn Adr Data <:5> CS6C L27 Single-Cycle CPU Control (4) Garcia, Spring 27 UCB
The Single Cycle Datapath during Branch? 3 26 2 op rs rt immediate if (R[rs] - R[rt] == ) then Zero = ; else Zero = RegDst= Rd RegWr= busw npc_sel= imm6 Rs 5 5 Rw Ra Rb RegFile 6 5 ExtOp= Extender busa busb 6 instr fetch unit zero ALUSrc= Instruction<3:> <2:25> Rs Rd Imm6 ALUctr= MemtoReg= = ALU Data In <6:2> MemWr= <:5> WrEn Adr Data <:5> CS6C L27 Single-Cycle CPU Control (5) Garcia, Spring 27 UCB
The Single Cycle Datapath during Branch 3 26 2 op rs rt immediate if (R[rs] - R[rt] == ) then Zero = ; else Zero = RegDst=x Rd RegWr= busw npc_sel=br imm6 Rs 5 5 Rw Ra Rb RegFile 6 5 ExtOp=x Extender busa busb 6 instr fetch unit zero ALUSrc= Instruction<3:> <2:25> Rs Rd Imm6 ALUctr=SUB MemtoReg=x = ALU Data In <6:2> MemWr= <:5> WrEn Adr Data <:5> CS6C L27 Single-Cycle CPU Control (6) Garcia, Spring 27 UCB
Instruction Fetch Unit at the End of Branch op rs rt immediate if (Zero == ) then PC = PC + 4 + SignExt[imm6]*4 ; else PC = PC + 4 npc_sel Zero imm6 4 PC Ext 3 Adder Adder 26 MUX npc_sel ctrl Mux 2 Inst PC Adr 6 Instruction<3:> What is encoding of npc_sel? Direct MUX select? Branch inst. / not branch Let s pick 2nd option npc_sel zero? MUX x Q: What logic gate? CS6C L27 Single-Cycle CPU Control (7) Garcia, Spring 27 UCB
Administrivia Dan s office hours this week only have been moved to Friday @ 3pm Everything up through HW3 has a grade P is still being addressed to find ways to give broken submissions more partial H4 is being graded now H5 and P2 are being graded soon H6 is on deck CS6C L27 Single-Cycle CPU Control (8) Garcia, Spring 27 UCB
Step 4: Given Datapath: RTL Control Instruction<3:> Inst Adr Op <26:3> <:5> Fun <:5> <:5> <6:2> <2:25> Rs Rd Imm6 Control npc_sel RegWr RegDst ExtOp ALUSrc ALUctr MemWr MemtoReg DATA PATH CS6C L27 Single-Cycle CPU Control (9) Garcia, Spring 27 UCB
inst A Summary of the Control Signals (/2) Register Transfer add R[rd] R[rs] + R[rt]; PC PC + 4 ALUsrc = RegB, ALUctr = ADD, RegDst = rd, RegWr, npc_sel = +4 sub R[rd] R[rs] R[rt]; PC PC + 4 ALUsrc = RegB, ALUctr = SUB, RegDst = rd, RegWr, npc_sel = +4 ori R[rt] R[rs] + zero_ext(imm6); PC PC + 4 ALUsrc = Im, Extop = Z,ALUctr = OR, RegDst = rt,regwr, npc_sel = +4 lw R[rt] MEM[ R[rs] + sign_ext(imm6)]; PC PC + 4 ALUsrc = Im, Extop = sn, ALUctr = ADD, MemtoReg, RegDst = rt, RegWr, npc_sel = +4 sw MEM[ R[rs] + sign_ext(imm6)] R[rs]; PC PC + 4 ALUsrc = Im, Extop = sn, ALUctr = ADD, MemWr, npc_sel = +4 beq if ( R[rs] == R[rt] ) then PC PC + sign_ext(imm6)] else PC PC + 4 npc_sel = br, ALUctr = SUB CS6C L27 Single-Cycle CPU Control (2) Garcia, Spring 27 UCB
A Summary of the Control Signals (2/2) See func We Don t Care :-) Appendix A op add sub ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite npcsel Jump ExtOp ALUctr<2:> x Add x Subtract Or Add x x Add x x x Subtract x x x? x x R-type 3 26 2 6 6 op rs rt rd shamt funct add, sub I-type op rs rt immediate ori, lw, sw, beq J-type op target address jump CS6C L27 Single-Cycle CPU Control (2) Garcia, Spring 27 UCB
Boolean Expressions for Controller RegDst = add + sub ALUSrc = ori + lw + sw MemtoReg = lw RegWrite = add + sub + ori + lw MemWrite = sw npcsel = beq Jump = jump ExtOp = lw + sw ALUctr[] = sub + beq (assume ALUctr is ADD, : SUB, : OR) ALUctr[] = or where, rtype = ~op 5 ~op 4 ~op 3 ~op 2 ~op ~op, ori = ~op 5 ~op 4 op 3 op 2 ~op op lw = op 5 ~op 4 ~op 3 ~op 2 op op sw = op 5 ~op 4 op 3 ~op 2 op op beq = ~op 5 ~op 4 ~op 3 op 2 ~op ~op jump = ~op 5 ~op 4 ~op 3 ~op 2 op ~op add = rtype func 5 ~func 4 ~func 3 ~func 2 ~func ~func sub = rtype func 5 ~func 4 ~func 3 ~func 2 func ~func How do we implement this in gates? CS6C L27 Single-Cycle CPU Control (22) Garcia, Spring 27 UCB
Controller Implementation opcode func AND logic add sub ori lw sw beq jump OR logic RegDst ALUSrc MemtoReg RegWrite MemWrite npcsel Jump ExtOp ALUctr[] ALUctr[] CS6C L27 Single-Cycle CPU Control (23) Garcia, Spring 27 UCB
Peer Instruction RegDst busw RegWr Clk Rd Mux imm6 5 5 Rs 5 Rw Ra Rb -bit Registers 6 npc_sel busb Extender busa ALUctr A. MemToReg= x & ALUctr= sub. SUB or BEQ? Clk ExtOp B. ALUctr= add. Which signal is different for all 3 of: ADD, LW, & SW? RegDst or ExtOp? C. Don t Care signals are useful because we can simplify our PLA personality matrix. F / T? Mux ALUSrc Instruction Fetch Unit ALU Data In Clk Instruction<3:> Zero <2:25> WrEn <6:2> Rs MemWr Adr Data Rd <:5> <:5> Imm6 Mux MemtoReg ABC : SRF : SRT 2: SEF 3: SET 4: BRF 5: BRT 6: BEF 7: BET CS6C L27 Single-Cycle CPU Control (24) Garcia, Spring 27 UCB
Summary: Single-cycle Processor 5 steps to design a processor. Analyze instruction set datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic Formulate Logic Equations Design Circuits Processor Control Input Datapath Output CS6C L27 Single-Cycle CPU Control (25) Garcia, Spring 27 UCB
Bonus slides These are extra slides that used to be included in lecture notes, but have been moved to this, the bonus area to serve as a supplement. The slides will appear in the order they would have in the normal presentation CS6C L27 Single-Cycle CPU Control (26) Garcia, Spring 27 UCB
J-type The Single Cycle Datapath during Jump 3 op 26 Jump= Instruction<3:> npc_sel= Instruction Rd Fetch Unit RegDst = Clk Mux RegWr = Rs ALUctr = Rs Rd Imm6 TA26 5 5 5 MemtoReg = busa Zero MemWr = Rw Ra Rb busw -bit Registers busb Clk WrEn Adr imm6 25 6 Extender target address New PC = { PC[3..28], target address, } Mux ALUSrc = ALU Data In Clk <2:25> <6:2> Data <:5> jump <:5> Mux <:25> ExtOp = CS6C L27 Single-Cycle CPU Control (27) Garcia, Spring 27 UCB
The Single Cycle Datapath during Jump J-type 3 op 26 Jump= Instruction<3:> npc_sel=? Instruction Rd Fetch Unit RegDst = x Clk Mux RegWr = Rs ALUctr =x Rs Rd Imm6 TA26 5 5 5 MemtoReg = x busa Zero MemWr = Rw Ra Rb busw -bit Registers busb Clk WrEn Adr imm6 25 6 Extender target address New PC = { PC[3..28], target address, } Mux ALUSrc = x ALU Data In Clk <2:25> <6:2> Data <:5> jump <:5> Mux <:25> ExtOp = x CS6C L27 Single-Cycle CPU Control (28) Garcia, Spring 27 UCB
Instruction Fetch Unit at the End of Jump J-type New PC = { PC[3..28], target address, } Jump npc_sel Zero 3 op 26 25 Inst Adr target address Instruction<3:> jump npc_mux_sel 4 imm6 Adder Adder Mux Clk PC How do we modify this to account for jumps? CS6C L27 Single-Cycle CPU Control (29) Garcia, Spring 27 UCB
Instruction Fetch Unit at the End of Jump J-type New PC = { PC[3..28], target address, } Jump npc_sel Zero imm6 3 4 op 26 Adder 25 npc_mux_sel Adder Mux TA 26 target address 4 (MSBs) Mux Inst Clk PC Adr jump Instruction<3:> Query Can Zero still get asserted? Does npc_sel need to be? If not, what? CS6C L27 Single-Cycle CPU Control (3) Garcia, Spring 27 UCB