Design Rule Optimization of Regular layout for Leakage Reduction in Nanoscale Design Anupama R. Subramaniam, Ritu Singhal, Chi-Chao Wang, Yu Cao Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287 USA 01/23/2008 ASPDAC 2008 1
Lithography Trend and Yield Constraints Yield issues due to device scaling: Yield will be limited by physical dimension instead of traditional particle defects. Device will be distorted due to Lithography limitations, Mask misalignment, Etching, Oxide growth, System defects and Random effects. Lithography limits: When Critical Dimension (CD) is getting smaller than optical wave length. Functional yield (defects) : - Shorts for dense feature - Opens for isolated features. Parametric yield (process variation): - Edge placement error for CD. - Power and Performance impact. 1 micron 0.1 365nm 248nm 180nm 130nm 90nm 65nm Process Generation Source: Mark Bohr, Intel Lithography Wavelength 193nm 45nm 32nm 157nm Gap 13nm EUV 1000 nm 100 0.01 10 1980 1990 2000 2010 2020 Sub-wavelength Lithography 01/23/2008 ASPDAC 2008 2
Post Lithography Gate Shape Post Litho Non Rectilinear Gate (NRG) Impact: Shortening of poly line end can cause device failure. Sub-threshold leakage may increase by more than ~15x compared to ideal layout. Overall yield impact. Ids (ua / um) 1.E-01 1.E-02 1.E-03 1.E-04 1.E-05 1.E-06 Ideal Layout Post Lithography Ideal Layout DAC 2007 Post Litho Aerial Image Ideal Layout Post Lithography Aerial Image 1.E-07 Non-Rectilinear Gate (NRG) 1.E-08 1.E-09 15x 0 0.2 0.4 0.6 0.8 1 1.2 Vgs (v) Leakage current fluctuation with ideal layout versus post litho NRG Model. Poly Gate Diffusion 01/23/2008 ASPDAC 2008 3
Regular Layout Follows the concept of single pitch and single orientation. Restrictive Design Rule (RDR) was proposed to effectively enhance yield and minimize the process variation. Minimize variation in gate length due to distortion caused by lithography. Random layout showing gate, diffusion and contacts location. Dummy poly gates Why do we need Regular Layout Optimization and RDR Prediction: As the interaction between Layout and Leakage becomes more pronounced, there is a growing demand to predict and optimize the Regular Layout under RDR for low power designs. Regular layout showing gate, diffusion and contacts. location. 01/23/2008 ASPDAC 2008 4
Lithography Basics: Projection Lithography Basics: -3-2 2-1 1 0 Higher Order Diffracted Light 3 Lens Resolution: Diffraction Limited. In a smaller feature size, Larger Diffraction. Fewer diffraction order can be captured Loss of image details. Pitch λ R = = CD= k1 2 NA n Refractive Index f Focal Distance D Lens Diameter NA Numerical Aperture θ max λ Max Focus angle Optical Wave Length 01/23/2008 ASPDAC 2008 5 k1 : Process dependent adjustment factor Practical lower limit k1 ~= 0.25 K1 can be determined by resist capability, tool control, reticle pattern adjustment and other process control.
Defocus Defocus Tolerance: Depth Of Focus (DOF): Range of Focus for which the resist profile remains within specs. 2 λ CD DOF ± k2 ± k2 2 2 NA k1 λ DOF can t be too low because the low image definition and contrast can alter CD and limit exposure latitude. Variation in surface height of processed wafer must be less than the optical DOF. There is a negative effect between DOF and Resolution. That means the better the resolution, the worse the DOF. HIGHER R (SMALL DOF ) CAN FOCUS ON A OR B BUT NOT A AND B SIMULTANEOUSLY A Resist Wafer LARGE NA; SMALL DOF B SMALL NA; LARGE DOF 01/23/2008 ASPDAC 2008 6
Resolution Enhancement Techniques (RET) Litho process window is defined by adjusting R and DOF along with other process specific parameters. RET: Resolution Enhancement Techniques. Amplitude, Direction, Phase and Wavelength of optical system can be controlled to improve Resolution. RET Benefits: Better Resolution. RET Limits: High Mask Cost. Huge Turnaround Time for yield verification due to large data volume. Requires the Layout to follow the concept of Single pitch and single orientation. Impact on Layout Rule / Design Restriction. 01/23/2008 ASPDAC 2008 7
RET approaches: Optical Proximity Correction (OPC). Phase Shift Mask (PSM) attenuated PSM / alternating PSM. Off Axis Illumination (OAI). Allows some of the higher order diffracted light to be captured and hence can improve resolution (by decreasing k 1 ). Amplifies certain pitch at the cost of others. Sub Resolution Assist Feature (SRAF). Dummy poly feature are placed in between two poly gates where the poly pitch is greater than the optimal pitch for OAI. 01/23/2008 ASPDAC 2008 8
Regular Layout Optimization under RDR Critical Design Rules impact to CD: 1 st order effect to PS and PDC-S. 2 nd order effect to PEX, W, CW, AEX etc.. Critical design rule index Drawn Poly Gate Post Litho Poly Gate Drawn Diffusion Post Litho Diffusion SRAF L Design Rule (nm) Poly Pitch Poly Gate Length Rule Index PP L=(LW) PEX W Poly Gate Width Poly Space W PS=(LS) CW Contact Width CW W(p,n) Poly End Cap PEX PSWDC PDC-S Poly to Diffusion Contact Space PDC-S AEX PP PS Active Extension Active Width Nmos AEX W d =W n Post litho aerial image super imposed on top of ideal layout illustrating critical design rule index used for optimization. Active Width Pmos W d =W p 01/23/2008 ASPDAC 2008 9
Validation suite for Regular Layout Optimization Calibre - Post Lithography Aerial Image Simulation for NRG: λ=157nm; NA=0.95; n=1.437; OAI along with SRAF are added into consideration. Post lithography aerial image simulation model combined with NRG leakage model is suitable for leakage analysis for Regular layout optimization using RDR. Benchmark Circuits: NAND gate, XOR gate and 1bit full adder. Regulate Layout: We follow the concept of single pitch and single orientation to alleviate the leakage induced by NRG effect. 1.2 1.0 Wdeff PS=97.5 nm 0.8 0.6 CD 0.4 0.2 0.0 20 24 28 32 38 42 48 52 56 Leff (nm) Normalized PDF of post litho, post etch effective channel length (Etch effect ~=30nm). Leff = CD etch effect PDF 01/23/2008 ASPDAC 2008 10
Priority of Optimization for Layout Parameters 70 65 PS PEX L 10 0 80 Poly space (PS) has 1 st order impact on CD and in turn leakage energy. Optimized for leakage CDmin (nm) 60 55 50 60 40 Poly end extension (PEX) has 2 nd order impact on CD. Critical for circuit operation. Optimized for manufacturability. 45 0.5 1.0 1.5 2.0 2.5 3.0 3.5 20 PEX ~= 1.5L (considering process variation) Normalized Parameters CDmin sensitivity to poly space (PS), poly end extension (PEX) and gate length ( L). L process window is in the range of 60nm to 75nm depending on design requirement. Cdmin is affected profoundly by PS. 01/23/2008 ASPDAC 2008 11
Post Litho Effective Poly Width 600 500 Pre Litho Poly W=325nm Pre Litho Poly W=455nm W eff has marginal impact with respect to PS. Post Litho Poly Weff (nm) 400 300 200 100 0 Optimal PS Poly width (W) can be optimized for better manufacturability. W= Wd + 2PEX. where Wd - diffusion width. 25 75 125 175 225 PS (nm) Post litho effective poly width (Weff ) with respect to PS optimization. 01/23/2008 ASPDAC 2008 12
Finding optimal Poly Space for Regular Layout 16 14 Area Eoff Diffusion Contact = 85nm 4.5 3 Leakage energy (Eoff) is sensitive to CD min obtained from aerial image simulation, and PS has a strong connection with CD. Cell Area (um 2 ) 12 10 8 Optimal PS for Leakage and Area 50 80 110 140 170 200 PS (nm) Finding optimal poly space (PS) considering leakage energy (Eoff) and area trade off. 1.5 0-1.5 Eoff (pj ) Thus, once we have the optimal PS, Eoff impact and area penalty can also be optimized. Compared to un-optimized regular layout for benchmark circuits, 73% reduction Eoff with 10% area penalty can be achieved in our optimal simulation. 01/23/2008 ASPDAC 2008 13
Active Energy and Delay Impact due to RDR 140 120 Delay Eactive 70 60 There is a marginal impact on the cell delay and active power. Cell Delay (ps) 100 80 60 40 20 0 Functional failure observed 50 80 110 140 170 200 PS (nm) 50 40 30 20 10 0 Eactive (fj ) Impact of active energy (Eactive) and speed (Tpd) due to PS optimization. Circuit speed (Tpd) has ~12.5% slow down compared to un-optimized regular design. On the other hand, active energy (Eactive) can be improved by ~12%. 01/23/2008 ASPDAC 2008 14
Effect of Defocus NRG parameters (nm) 100 80 60 40 20 Lmin Lmax Mean Sigma Variation in Lmin due to defocus : +6.8nm to -7.7nm Positive defocus range : reduce leakage and slow down the circuit speed due to Lmin increase 0-75 -50-25 0 25 50 75 Defocus (nm) The impact of defocus on post litho NRG parameters for optimized layout. Negative defocus range : increase the leakage as well as speed and could cause fatal failure due heavy leakage caused by reduction in Lmin 01/23/2008 ASPDAC 2008 15
Optimized RDR parameters for Regular Layout Optimized RDR Parameter Optimized Value (nm) Drawn Poly Gate PP 162.5 Post Litho Poly Gate PS 97.5 PDC-S 87.5 Drawn Diffusion Post Litho Diffusion SRAF L CW 85 PEX W PEX 97.5 W 455 L 65 W(p,n) CW AEX 172.5 PSWDC PDC-S PP = L + PS = LW + LS AEX PP PS PDC-S = [(2 PS) + L CW]/ 2 PSWDC = CW + (2PDC-S) AEX = CW + PDC-S + X X Active overlap of contact. X can be eliminated considering 1 st order approximation. 01/23/2008 ASPDAC 2008 16
Comparative Analysis of Benchmark Layouts Layout Design Style T pd (ps) E active (fj) Area (um2) E off (fj) NAND Typical Regular 33.58 1.316 1.187 0.0228 Optimized Regular 37.66 1.536 1.231 0.0146 Optimized vs Typical Regular (%) 12.15 16.72 3.71-36.12 XOR Typical Regular 90.82 7.53 4.260 52.63 Optimized Regular 97.56 7.21 4.612 13.97 Optimized vs Typical Regular (%) 7.42-4.20 8.26-73.46 One bit full Adder Typical Regular 104.00 19.56 9.341 184.5 Optimized Regular 117.00 17.25 10.173 50.15 Optimized vs Typical Regular (%) 12.50-11.81 8.91-72.82 01/23/2008 ASPDAC 2008 17
Conclusion With optimized regular layout, E off (off-state power consumption) due to NRG is reduced by ~73% for PS=97.5nm with area penalty of ~9% on the benchmark standard cells. Marginal impact on Eactive and Tpd of ~5% to 12.5% for 1bit full adder in 65nm process technology. Proposed RDR prediction method and regular layout optimization technique can be efficiently applied during design phase of product cycle to help reduce energy consumption and improve product yield. 01/23/2008 ASPDAC 2008 18
Thank You! 01/23/2008 ASPDAC 2008 19
Questions? Comments Concerns 01/23/2008 ASPDAC 2008 20
Backups 01/23/2008 ASPDAC 2008 21
CD Variation Estimation 2-D Aerial Image Simulation Method Using Projection Litho Model. Modulation Transfer Function (MTF) (Plummer pg. 251) P Fourier Transform of Mask Transmittance LS LW (DAC2005: RET aware Fast Litho simulation) 01/23/2008 ASPDAC 2008 22
Problem Description Photolithography- OPC Yield: Percentage of Manufactured chip that meet product specification (ie. power, performance and area specs) Litho illumination Impact: Edge Placement Error for Critical Dimension (CD): EPE ( CD) = drawn layout mask CD printed CD in wafer Results in parametric yield (process variation). -ve EPE (poly gate) Leakage impact. +ve EPE (poly gate) Performance impact. Optical Proximity Correction (OPC) can be used to compensate somewhat for diffraction effects. Sharp features are lost because higher spatial frequencies are lost due to diffraction. These effects can be calculated and can be compensated for. This improves the resolution by decreasing k 1. 01/23/2008 ASPDAC 2008 23
Photolithography-OAI OAI systems focus the light at the entrance pupil of the objective lens. This captures diffracted light equally well from all positions on the mask. This method improves the resolution by bringing k 1 down. Off-axis illumination also allows some of the higher order diffracted light to be captured and hence can improve resolution (by decreasing k1). 01/23/2008 ASPDAC 2008 24
Photolithography- Phase Shift Masks Extends resolution capability of current optical lithography Takes advantage of the wave nature of light PSM changes the phase of light by 180 in adjacent patterns leading to destructive interference rather than constructive interference Improves MTF of aerial image on wafer. Making k 1 smaller. allow sharper resist images and/or smaller feature sizes for a given exposure system. 01/23/2008 ASPDAC 2008 25
Aerial Image Simulation Model Post Lithography Aerial Image Simulation: Calibre workbench used for post litho aerial image simulation. Model based OPC. TCCALC engine with scalar diffraction model. Technology node 65nm; Illumination wavelength λ=157nm; Numerical aperture NA=0.95 (maximum theoretical limit); Refractive index n=1.437; Due to regular layout style, OAI combined with SRAF is added benefit. Resist thickness ~=125nm assumed (ITRS requirement < 225nm. CD calculated at 30% of maximum image intensity 01/23/2008 ASPDAC 2008 26
NRG Leakage Simulation Model Leakage Simulation using NRG model: PTM 65nm technology model with Leff in place of gate length in spice simulation. Verilog-A model for transistors used in integrating NRG Leff model with spice simulator. NRG leakage mode requires the PDF of Leff obtained from post litho simulation to have Gaussian distribution. min L e = L min + ln( σw / Wc) Wc = ~5nm from post litho aerial image simulation min L e max L e max L e L eff =µ ln( σ ) = L Fuction of Lmin and sigma of all lengths that form the gate section. Leakage has exponential dependence on this parameter Fuction of mean gate length and sigma min e + L αvgs α( Vgs) 2 + 1 Post lithography aerial image simulation model combined with NRG leakage model is suitable for Regular layout optimization using RDR for leakage. max L = L e L e min Fitting parameter 01/23/2008 ASPDAC 2008 27
Preliminary Results (contd ) Critical design rule index and parameter range used for layout optimization. Design Rule (nm) Rule Index Minimum value Maximum value Poly Pitch PP 130 200 Poly Gate Length L=(LW) 60 85 Poly Gate Width W 325 650 Poly Space PS=(LS) 65 195 Contact Width CW 65 85 Poly End Cap PEX 33 180 Poly to Diffusion PDC-S 60 130 Contact Space Active Extension AEX 65 260 Active Width Nmos W d =W n 130 195 Active Width Pmos W d =W p 195 260 Final optimized parameters for regular layout vs typical regular layout. Optimized Layout Parameter Typical value (nm) Optimized Value (nm) PP 146 162.5 PS 81 97.5 PDC-S 71 87.5 CW 80 85 PEX 65 97.5 W 455 455 L 65 65 AEX 151 172.5 01/23/2008 ASPDAC 2008 28