Su Dong SLAC Summer Institute Aug/2/2012 1
LHC is exceeding expectations in many ways Design lumi 1x10 34 Design pileup <µ>~24 Rapid increase in luminosity Even more dramatic pileup challenge Z->µµ event with 25 pileup vertices 2
LHC Roadmap 3
The Path to High Luminosity LHC reached today s performance at a much faster pace than anyone could have anticipated. LHC took a somewhat different path to reach today s performance with a somewhat different configuration compared to the original design. LHC detectors performed remarkably well to survive the challenge of rapid luminosity increase (and the even more rapid pileup growth). Are we going to be as lucky for the next phase of luminosity challenge? Do we have solutions for the upcoming challenges? Current LHC detectors took >10 years to build. Do we have a timely strategy? 4
LHC Configuration Scenarios Config year Bunch/ spacing Bunch /Beam Protons /bunch ε n (µm) Xing angle (µrad) β* (m) Peak L (cm -2 s -1 ) Mean Pileup Events design 25ns 2808 1 10 11 3.75 280 0.55 1.0x10 34 25.5 `Phase-0 50ns 1404 1.7 10 11 2.5 270 0.5 1.7x10 34 86 +LINAC4 50ns 1404 2.5 10 11 3.75 320 0.5 2.5x10 34 125 `Phase-2 25ns 2808 2.0 10 11 2.5 420 0.2 6.9x10 34 173 `Phase-2 50ns 1408 3.3 10 11 3.75 520 0.2 6.2x10 34 311 Based on Oliver Bruning s Charmonix-2011 projections Phase-2 5
Some Known Limitations Degraded performance of silicon sensors close to interactions point due to radiation damage. Data bandwidth bottlenecks at various stages of data pipeline due to the nonlinear Luminosity*Occupancy growth. L1 calorimeter trigger segmentation granularity limiting background suppression performance. L1 muon trigger fake suppression capability. L1 muon Pt resolution preventing raising Pt threshold beyond ~40 GeV. Tracking pattern recognition fake rate at high occupancy. 6
Phase 0/1 Pixel Detectors ATLAS IBL (phase-0) CMS new Pixel (phase-1) Insertable B-Layer (IBL) to be installed in 2014 inside present pixel detector Complete replacement of pixel system in 2018 7
ATLAS Pixel Insertable B-Layer (IBL) First hit at R=33mm (Present B-layer at R=55mm) Pixel size 100x250µm (Present pixel 100x400µm) IBL later material ~1.5% (Present pixel ~3%/layer) d 0 z 0 1 GeV trk 1 GeV trk 8
ATLAS IBL Source test 64cm 9
3D Silicon Sensors Original proposal by Sherwood Parker pixel cell n+ p+ 90 o 75 o Initial pioneering R&D at Stanford Nanofabrication Facility. 3D sensors on IBL is the first HEP application. Radiation hard, active edge Primary candidate sensor pixel upgrade innermost layer LHC Detector Upgrade IBL stave 10
Pixel Upgrade b-tag performance ATLAS IBL CMS new pixel 4-Layer Pixel with IBL 3-Layer Pixel DOE Lab Energy Frontier Comparative Review 2012 11
CMS Phase-1 Pixel 12
HL-LHC Tracking Upgrade L = 1x10 33 13
Tracking at HL-LHC L = 5x10 34 14
HL-LHC Tracker ATLAS Phase-2 Tracker Layout Study All silicon tracking: typically 10 double-sided Si strip hits + 4 pixel hits; η <2.5 15
Tracker Implementation Desires Would like to have infinitesimal granularity for best resolution Should only consume minimal power Should be extremely light in material It should be very radiation hard Has infinite bandwidth for shipping data There should be just a few cables to connect It s better to only cost pocket change 16
The R&D Work for Reality DC-DC CMS strip tracker end cap Just before for installation... 2mm CO2 cooling Data Transmission 17
ATLAS Phase-1 Muon Small Wheel New small wheel MicroMegas + stgc For precision Pt and trigger nsw 18
CMS Phase-1 Muon Trigger Complete instrumentation of the staged ME4 chambers 19
L1 Muon Pt Threshold Problem CMS ATLAS is similar with RPC,TGC only L1 trigger L1 rate at HL-LHC forces the raise of L1 muon Pt threshold, but resolution limitation would result in random removal of all high Pt muons if threshold exceeds ~30 GeV. L1 track (+mu) trigger to improve Pt resolution (CMS, ATLAS) L1 muon trigger with MDT (ATLAS) 20
L1 Track Trigger for HL-LHC Many possible different topologies but implementations all very difficult. 21
Phase-2 Trigger Strategy Time (µs) L0 ~500 Khz L1 ~200 Khz L1 algorithm only using data from ROIs in L0 trigger Much less demanding than self-seeded L1 track trigger working 40Mhz => more versatile L1 track trigger LHC Detector Upgrade 22
ATLAS L1 Muon Trigger with MDT 23
xtca platform for Trigger & DAQ CMS current trigger plant CMS µtca trigger shelf ATCA = Advanced Telecommunication Computing Architecture 24
Reconfigurable Cluster Element Concept Resources per RCE Xilinx Virtex 5 FX70 FPGA with built-in crossbar & user firmware application space 4 GByte memory 6 channels of data I/O up to 12.5 Gb/s per channel. 40 Gb/s Ethernet network output 128 DSP tiles 25
Cluster On Board (COB) V4 4 Data Processing Modules (DPM) Dual RCE (6 MGT), or Single RCE (6 MGT), or Single RCE (30 slow I/O ports) 1 Data Transport Module () 1 control RCE 24 port x 40G switching capacity 2x40Gb/s Ethernet port Front TTC interface (FTM) Rear Transition Module (): User interface via P3 RCE 1 RCE 2 DPM 1 1-40 GE DPM 3 RCE 3 RCE 4 RCE 5 RCE 6 RCE 7 RCE 8 front panel 1 GE RCE P3 switch P2 1-40 GE 1-12.5 gbits/sec 1-40 GE front panel IPMC clock base fabric P1 Shelf Back-Plane 26
COB (V4) with Gen-I Mezzanine IPMI controller FTM (to be built) for TTC interface 24-port 10-GE switch 1 of 4 DPMs (with GEN-I RCEs) Power/ J-tag/ I 2 C PICMG 3.8 P3 with 120 pairs of user I/O 27
DPM 1 DPM 1 f r ontpanel DPM 3 f r ontpanel DPM1 DPM 3 f r ontpanel DPM2 DPM2 DPM3 DPM 1 f r ontpanel DPM1 f r ontpanel DPM2 DPM2 RCE 7 RCE 8 DPM3 DPM 3 RCE 1 RCE 2 DPM 1 RCE 3 RCE 4 f r ontpanel RCE 5 RCE 6 f r ontpanel RCE 7 RCE 8 DPM 1 DPM 3 DPM 3 DPM 1 f r ontpanel DPM 3 f r ontpanel RCE 1 RCE 2 DPM 1 RCE 3 RCE 4 RCE 5 RCE 6 RCE 7 RCE 8 DPM 3 f r ontpanel RCE 1 RCE 2 DPM1 RCE 3 RCE 4 f r ontpanel DPM2 RCE 5 RCE 6 DPM2 RCE 7 RCE 8 DPM3 DPM 1 f r ontpanel f r ontpanel RCE 5 RCE 6 f r ontpanel DPM 3 DPM 1 DPM2 DPM2 DPM3 RCE 1 RCE 2 RCE 3 RCE 4 RCE 7 RCE 8 DPM1 DPM 3 Ethernet topology in a 14-slot ATCA shelf RCE 1 RCE 2 RCE 3 RCE 4 RCE 5 RCE 6 RCE 7 RCE 8 RCE 7 RCE 8 RCE 1 RCE 2 DPM 1 RCE 5 RCE 6 RCE 3 RCE 4 RCE 3 RCE 4 RCE 5 RCE 6 The full mesh ATCA backplane: RCE 5 RCE 6 RCE 7 RCE 8 RCE 1 RCE 2 DPM 3 RCE 7 RCE 8 RCE 1 RCE 2 RCE 3 RCE 4 RCE 3 RCE 4 RCE 5 RCE 6 Any slot has 40Gb/s bandwidth with each other slot in the shelf simultaneously. RCE 1 RCE 2 RCE 3 RCE 4 RCE 5 RCE 6 RCE 7 RCE 8 RCE 1 RCE 2 RCE 7 RCE 8 RCE 5 RCE 6 RCE 3 RCE 4 RCE 1 RCE 2 RCE 7 RCE 8 RCE 1 RCE 2 RCE 3 RCE 4 RCE 5 RCE 6 RCE 7 RCE 8 Compare to VME as single bus of 40MB/s RCE 5 RCE 6 RCE 3 RCE 4 RCE 1 RCE 2 RCE 7 RCE 8 RCE 5 RCE 6 RCE 3 RCE 4 RCE 1 RCE 2 1-40 GE x 28 40 GE 28