Serial : 1. PT_CS_A_Computer Organization_230418 Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: E-mail: info@madeeasy.in Ph: 011-45124612 CLASS TEST 2018-19 COMPUTER SCIENCE & IT Subject : Computer Organization Date of test : 23/04/2018 Answer Key 1. (b) 7. (d) 13. (d) 19. (d) 25. (b) 2. (d) 8. (a) 14. (d) 20. (b) 26. (a) 3. (b) 9. (a) 15. (a) 21. (b) 27. (c) 4. (c) 10. (c) 16. (c) 22. (b) 28. (b) 5. (a) 11. (d) 17. (c) 23. (a) 29. (c) 6. (b) 12. (b) 18. (a) 24. (c) 30. (a)
CT-2018 CS Computer Organization 7 Detailed Explanations 1. (b) Number of words in control memory = 256 16 = 4096 words Address field = 12 bits 16 = 2 4 and 52 < 2 6 The length of control word = Flag Control signal Address = 4 bit + 6 bit + 12 bit = 22 bits/word 2. (d) Computer uses addressing mode technique for giving program versatility to user by providing facilities as a pointer to memory counters for loop control and to reduce number of bits in the field of instruction. Addressing modes are used in specifying rules for modifying or interpreting address field of the instruction. So all options are correct. 3. (b) Dirty bit is used to represent the status of cache whether it has been defined after copying from main memory to cache. Dirty bit = 0 shows no modification and dirty bit = 1 shows modification. 4. (c) For making use of pointer in programs, indirect addressing mode is used. Pointer stores the address of an variable and indirect addressing mode stores address of effective address in instruction. Position independent code makes use of relocation concept which is implemented by the use of relative addressing mode which uses relocation register to set the difference of logical and physical address. Immediate addressing mode provides the value directly in the instruction which is suitable to be used for constant operands of the program. 5. (a) 1 sec 50 kbyte 1 byte 1 50k = 20 10 6 sec = 20 µsec For interrupt driven mode it takes 50 µsec So performance achieved when interrupt driven used over programmed I/O ETprog IO S = = 20 ETINT IO 50 = 0.4 6. (b) ET non-pipe ET pipe = Average CPI Cycle time (non-pipe) = 4 0.33 nsec = 1.65 nsec = Average CPI pipe Cycle time (pipe) = 1 0.5 nsec = 0.5 nsec ETnon-pipe Speed-up = = 1.65 ETpipe 0.5 = 3.3 7. (d) Microprogramed control unit uses variable logic to interrupt instruction. Vertical microprogramed control unit require an additional hardware. Hardwired control unit is implemented in RISC processor. So, both (a) and (b) are false. 8. (a) DMA in a burst mode i.e., the DMA interface gains bus mastership prior to the start of a block transfer and maintains control of the bus until the whole block is transferred.
8 Computer Science & IT 9. (a) The actual transfer time needed = (128 B) = 2.56 msec (50 kbps) Added to this is the time to transfer bus control at the beginning and end of transfer, which is 250 + 250 = 500 nsec This additional time is neglisible. So that transfer time can be considered as 2.56 msec. Op-code 32 bits Register Main memory address 10 bits 19 bits Number of bits for op-code = log 2 1024 = 10 bits Number of bits for main memory address = 512 k = 19 bits Number of bits for required = 32 (19 10) = 32 29 = 3 bits 10. (c) Apply Amdhal s law F = 80%, S = 20, overall speed-up = F (1 F) + S 1 = 0.8 (1 0.8) + 20 1 = 4.16 11. (d) S1: Compulsory miss can be reduced by increasing the line size i.e., reduce number of lines. S2: Conflict miss are occur when too many blocks are mapped into same line or set. So by increasing the associativity i.e. increases the size of set and increases the number of sets. S3: Capacity miss can be reduced by increasing the cache memory size. All of the three statements are true. 12. (b) Biased exponent = 18 + 64 = 82 Representing 82 in binary (82) 2 = (1010010) 2 Representing mantissa in binary (0.625) 10 = (0.10100000) Floating point representation is as follows: Sign bit Exponent Mantissa 0 1010010 10100000 5 2 A 0 13. (d) All the above statements are correct. S1: Reference bit some times called access bit used in page table entry to show if page is replaced or not. S2: In hierarchial memory access, CPU perform read and write operation only on level 1 memory. If miss occur then data is first transferred to level 1 then CPU access data. S3: In simultaneous memory access, CPU perform read and write operation on any level of memory i.e. not necessary to take data first into level 1 memory than access it. 14. (d) 32 14 bit 9 bit 9 bit 2 14 two address instructions are possible. Here 400 two addresses are needed so (2 14 400) op-codes are free. We can store (2 14 400) 2 9 one address instructions.
CT-2018 CS Computer Organization 9 15. (a) Write through protocol update cache and main memory simultaneously where write back first cache is updated and marked by dirty bit then main memory is updated. Dirty bits are used by only write back protocol to know which cache block is updated. 16. (c) Total number of blocks = 10 16 2 B = 2 8 6 2 B Total number of sets = 256 4 = 64 SET Modified bit Valid bit TAG Total TAG size will be 22 bits 1 1 20 6 6 Total size of meta data will be 22 256 bytes = 704 bytes 8 17. (c) T memory = 200 ns H read = 0.8 T cache = 10 ns H write = 1 (by default for write through) f read = 80% f write = 20% T avg read = (0.8 10) + (0.2 200) = 8 + 40 = 48 ns T avg write = 1 200 = 200 ns T avg = f read T avg read + f write T avg write = 0.8 48 + 0.2 200 = 78.4 ns 18. (a) C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 C 9 C 10 C 11 C 12 C 13 C 14 C 15 32 WORD I 2 I 3 I 4 I 5 I 6 I 7 I 8 IF ID EX IF ID IF 2 3 4 5 6 So total 13 instruction are executed. K = 5, n = 13, t p = 10 nsec ET = (K + n 1)t p = (5 + 13 1)10 nsec = 17 10 = 170 nsec 19. (d) Main memory size = 32768 blocks 1 block = 512 words = 32768 512 words = 2 15 2 9 = 2 24 words
10 Computer Science & IT Main memory takes 24 bits. Block size = 512 words = 2 9 words Number of bits for block size = 9 bits. Number of blocks in set associative = 128 Number of blocks in one set = 4 Number of sets in cache = 128 / 4 = 32 = 2 5 Number of bits in set offset = 5 bits TAG Number of TAG bits = 24 (9+5) = 10 bits. 24 SET WORD 10 5 9 20. (b) Line offset = log 2 (2 m ) = m bits Word offset = log 2 (2 p ) = p bits Address field size = log 2 (2 n )= n bits Tag bits per line = n (m+p) Tag size = Number of cache lines Number of tag bits per line = 2 m (n (m+p)) 21. (b) T average (write) = H w T w + (1 H w ) (T m + T w ) Maximum updations (T w ) = Max (update time in cache memory, update time in main memory) = Max (40, 50) = 50 nsec T m = Time to access main memory to reallocates in cache T average (write) = 0.35 (50) + (1 0.35) [40 + 50] = 0.35 (50) + (0.65) (90) = 17.5 + 58.5 nsec = 76 nsec 22. (b) Window size = Local Register + (In register + Out register) + Global register = L + 2C + G = 10 + (2 6) + 10 = 20 + 12 = 32 Register file size = W (L + C) + G = 4 (10 + 6) + 10 = 4 (16) + 10 = 64 + 10 = 74 23. (a) Fetch and decode stage takes = 20 cycles One byte transfer take 30 cycle. 128 bytes take = 30 cycles 128 = 3840 cycles Total execution time = 20 + 3840 = 3860 cycles 1 i.e. 3860 = 38.60 nsec 100 G
CT-2018 CS Computer Organization 11 24. (c) 8 byte instruction storage: 2016 2017 2018 2019 2020 2021 2022 2023 2024 Fetch Instruction Register PC = 2024 Effective address = PC + Relative value = 2024 + ( 11) = 2013 25. (b) Format of single precision floating point is 32 bits S Exponant Mantissa 1 bit 8 bits 23 bits 0 1 0 0 0 0 1 0 0 101000000000...00 26. (a) Hexadecimal representation Value = 1.M 2 E 127 = 1.1010 2132 127 = (1.1010) 2 2 5 = 1.625 2 5 = (52) 10 16 52 16 3 4 Hexadecimal representation is (34) H. Memory I/O A 31 A 30 A 29 A 28 A 3 A A A 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 Μ Μ Μ Μ 1 1 0 1 1 1 1 0 1 1 1 1 2 1 0 Memory address space: 15 2 28 I/O address space = 1 2 28
12 Computer Science & IT 27. (c) Cache data size = 16 words Block size = 4 words Number of cache block = 16 4 = 4 0 1 2 3 16 13 2 6 10 11 3 2 2% 4 = 2 13% 4 = 1 6% 4 = 2 16% 4 = 0 11% 4 = 3 3% 4 = 3 10% 4 = 2 2% 4 = 1 13% 4 = 1 Cache Total # misses = 8 misses 28. (b) Average of time = {(0.2 0) + (0.2 0) + (0.4 16) + (0.2 12)} = {6.4 + 2.4} = 8.8 cycles So, average of time = 8.8 nsec 1 operand 8.8 nsec # number of operands in 1 sec Number of operands = 1 operand 8.8 nsec = 0.113636 109 operand/sec Operand fetch rate = 113.636 million words/sec 29. (c) 2.5 memory reference per instruction 1000 2.5 400 instructions. instruction per 1000 reference. Now 200 = 260 120 x+ 2 x 400 400 x = 400 200 500 x = 80000 500 x = 160 2x = 320 30. (a) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I 0 IF ID EX EX WB IF IF ID ID EX EX EX WB I 2 IF IF ID ID EX EX WB WB I 3 IF IF ID EX WB I 4 IF IF IF ID ID EX WB WB It requires 16 clock cycles.