Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008, ver. 1.1 Introduction LVDS is becoming the most popular differential I/O standard for high-speed transmission in the industry. The advantages of LVDS include high noise tolerance in the form of common-mode rejection, low power, and low noise generation. Improved signal to noise rejection of LVDS allows signal swing to be dropped to only a few hundred millivolts, which in turn enables faster data rates. However, many high-speed applications require more than just point-to-point communication. The desire for multipoint communication has spawned a new variant of LVDS called Bus LVDS (BLVDS), which extends the capability of LVDS to multipoint configuration such as high-speed backplane applications. There are several bus topologies for BLVDS I/O standard, such as multi-drop bus with single or double termination, and multipoint. This application note describes how to implement BLVDS interface in Cyclone III, Stratix III, and Stratix IV devices for high-performance multipoint application. Performance analysis of a multipoint application with the Cyclone III BLVDS example is also shown in this application note. The following topics are discussed in this application note: Overview of Bus LVDS BLVDS Technology in Altera Devices Power Consumption of BLVDS Design Example Performance Analysis Overview of Bus LVDS Figure 1 illustrates a typical multipoint BLVDS system which consists of a number of transmitters and receiver pairs (transceivers) that are connected to the bus. This configuration provides bidirectional half duplex communication while minimizing interconnect density. Any transceiver can assume the role of transmitter, with the remaining transceivers acting as receivers (for example, only one transmitter can be active at a time). Bus traffic control, either through protocol or hardware solution is typically required to avoid driver contention on the bus. The performance of a multipoint BLVDS is greatly affected by the capacitive loading on the bus and termination on the bus. This section explains the calculations of the effective differential impedance of a fully loaded bus (referred to as effective impedance) and the propagation delay through the bus. Other multipoint BLVDS design considerations include fail-safe biasing, connector type and connecter pinout, bus trace layout on the PCB, and driver edge rate specifications. Detailed description of each factor is beyond the scope of this application note. November 2008 Altera Corporation Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices
2 2 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices Overview of Bus LVDS Figure 1. Multipoint BLVDS R T R T R T R T R T R T The effective impedance depends on the bus trace characteristic impedance Z o and capacitive loading on the bus. The connectors, the stub on the plug-in card, the packaging, and the receiver input capacitance all contribute to capacitive loading, which reduces the bus effective impedance. Equation 1 can be used to approximate the effective differential impedance of the loaded bus, Z eff. Equation 1. * Z eff = Z diff C O + C O (NC L /H) C O = Z diff * + C O C d Where Z diff (Ω) 2 * Z O = the differential characteristic impedance of the bus C O (pf/inch) = characteristic capacitance per unit length of the bus C L (pf) = capacitance of each load N = number of loads on the bus H (inch) = d * N = total length of the bus d (inch) = spacing between each plug-in card C d (pf/inch) = C L /d = distributed capacitance per unit length across the bus The increment in load capacitance or closer spacing between plug-in cards reduces the effective impedance. To optimize the system performance, it is important to select low capacitance transceiver, low capacitance connector, and keep each receiver stub length between the connector and the transceiver I/O pin as short as possible. Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008 Altera Corporation
Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices 2 3 Overview of Bus LVDS Figure 2 illustrates the effects of distributed capacitance on the normalized effective impedance. Figure 2. Normalized Effective Impedance vs. Cd/Co 1.1 1.0 0.9 0.8 0.7 Z eff / Z diff 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 1 2 3 4 5 6 7 8 9 10 C d / C o Termination is required at each end of the bus while the data flows in both directions. It is important to match the termination resistor to the effective impedance to reduce reflections and ringing on the bus. For a system with C d /C o = 3, the effective impedance is 0.5 times of Z diff. With double terminations on the bus, the driver would see an equivalent load of 0.25 times of Z diff. This reduces the signals swing and the differential noise margin across the receiver inputs if standard LVDS driver is used. BLVDS driver addresses this issue by increasing the drive current to achieve similar voltage swing at the receiver inputs. The propagation delay (t PD = Z o * C o ) is the time delay through the transmission line per unit length. It depends on the characteristic impedance and characteristic capacitance of the bus. For a loaded bus, the effective propagation delay can be calculated with Equation 2. The time for the signal to propagate from a driver A to a receiver B can then be calculated as t PDEFF * length of line between A and B. November 2008 Altera Corporation Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices
2 4 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices BLVDS Technology in Altera Devices Equation 2. t PDEFF = 1 t PD * + C d Co BLVDS Technology in Altera Devices In Cyclone III, Stratix III and Stratix IV devices, BLVDS interface is supported in any row or column I/O banks that are powered by a V CCIO of 2.5-V and is supported on all differential I/O pins, except clock pins in these I/O banks. The BLVDS transmitter uses two single-ended (SE) output buffers with the second output buffer programmed as inverted, while the BLVDS receiver uses a dedicated LVDS input buffer. In multi-drop application, either input or output buffer is used depending on if the device is intended for driver or receiver. In multipoint application, the output buffers and input buffer share the same I/O pins. An output enable (OE) signal is required to tri-state the output buffers when not transmitting or when the LVDS input buffer is receiving signal. Figure 3. BLVDS I/O Buffers in Cyclone III, Stratix III, and Stratix IV devices Output Data OE SE Output Buffer Near-End Series Termination Input Data Diff Input Buffer To FPGA Core Bi-directional Pins Output Data OE SE Output Buffer (inverted) In Cyclone III devices, there is a BLVS I/O standard to support BLVDS interface, in which 2.5-V Differential SSTL current strength is used as the BLVDS current strength. The available current strength options are 8 ma, 12 ma (default), and 16 ma. The slew rate settings are slow, medium, and fast (default), in which the corresponding settings in Quartus II software are 0, 1, and 2, respectively. On-chip series and parallel termination are not supported in a Cyclone III device BLVDS I/O standard. Pad placement rules for BLVDS I/O should follow those of LVDS I/O standard. f For more information about Cyclone III BLVDS I/O features and electrical specifications, refer to the Cyclone III Device I/O Features chapter in volume 1 of the Cyclone III Device Handbook and the DC and Switching Characteristics chapter in volume 2 of the Cyclone III Device Handbook. Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008 Altera Corporation
Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices 2 5 Power Consumption of BLVDS In Stratix III and Stratix IV devices, BLVDS interface can be implemented using 2.5-V Differential SSTL Class I or II, depending on the current strength requirement. The current strength and slew rate options are based on those available for the 2.5-V Differential SSTL I/O standard in Stratix III and Stratix IV devices. The slew rate settings in Quartus II software are 0, 1, 2, and 3 where 0 is slow slew rate and 3 is fast slew rate. On-chip series termination for the output buffer should not be enabled. External resistor at the output buffer should be used to provide impedance matching to the stub on the plug in card. On-chip differential termination for the differential input buffer should not be enabled because the bus termination is usually implemented using external termination resistors at both ends of the bus. Table 1 summarizes the I/O standards and features for implementing BLVDS in Cyclone III, Stratix III, and Stratix IV devices. Table 1. I/O standard and features support for BLVDS interface Current Strength Option (ma) Device I/O Standard V CCIO (V) Column I/O Row I/O Slew Rate Option Cyclone III BLVDS 2.5 8, 12, 16 8, 12, 16 slow, medium, fast Stratix III Differential SSTL-2 Class I or II 2.5 8, 10, 12, 16 8, 12, 16 slow, medium, medium fast, fast Stratix IV Differential SSTL-2 Class I or II 2.5 8, 10, 12, 16 8, 12, 16 slow, medium, medium fast, fast f f For more information about Stratix III 2.5-V Differential SSTL I/O standard electrical specifications and features, refer to the Stratix III Device I/O Features chapter in volume 1 of the Stratix III Device Handbook, and the DC and Switching Characteristics chapter in volume 2 of the Stratix III Device Handbook. For more information about Stratix IV 2.5-V Differential SSTL I/O standard electrical specifications and features, refer to the Stratix IV Device I/O Features chapter in volume 1 of the Stratix IV Device Handbook, and the DC and Switching Characteristics chapter in volume 4 of the Stratix IV Device Handbook. Power Consumption of BLVDS One of the benefits of BLVDS is its low power consumption. Compared to other high performance bus technology such as GTL that uses more than 40 ma, BLVDS typically drives out current in the range of 10 ma. As an example, based on Cyclone III Early Power Estimator (EPE) estimation, for a typical power characteristics Cyclone III device in ambient temperature of 25 C, the average power consumption of a BLVDS bidirectional buffer at data rate of 50 MHz and output enabled 50% of the time is around 17 mw. Figure 4 illustrates the BLVDS I/O entry in the Cyclone III EPE. BLVDS with the same setting in Stratix III and Stratix IV devices consumes about the same amount of power. For Stratix III and Stratix IV devices, select 2.5-V Differential SSTL Class I or Class II under I/O standard column in Stratix III and Stratix IV EPE. November 2008 Altera Corporation Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices
2 6 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices Design Example Prior to designing the device, you can use the Excel-based Cyclone III/Stratix III/Stratix IV EPE version 8.0 to get a magnitude estimate of the BLVDS I/O power consumption. For input and bidirectional pins, the BLVDS input buffer is always enabled. It consumes power when there is any activity on the bus (for example, other transceivers are sending and receiving data on the bus, but the Cyclone III device is not the intended recipient). If you use the Cyclone III/Stratix III/Stratix IV BLVDS as an input buffer in multi-drop or as a bidirectional buffer in multipoint application, Altera recommends entering a toggle rate that includes all the activities on the bus, not just the activities intended for the Cyclone III/Stratix III/Stratix IV BLVDS. Figure 4. Example of BLVDS I/O Data Entry in Cyclone III EPE After your design is completed, Altera recommends using the Quartus II PowerPlay Power Analyzer to perform an accurate BLVDS I/O power analysis. The PowerPlay Power Analyzer estimates power based on the specifics of the design after place-and-route is completed. The PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities which, combined with the detailed circuit models, can yield very accurate power estimates. f f For more information about Cyclone III EPE and the Quartus II PowerPlay Power Analyzer, refer to the Cyclone III Early Power Estimator User Guide and the PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook. For more information about Stratix III and Stratix IV EPE, refer to the Stratix III and Stratix IV Early Power Estimator User Guide. Design Example The design example illustrates how to instantiate BLVDS I/O buffer in Cyclone III, Stratix III and Stratix IV devices using ALTIOBUF megafunction in the Quartus II software. You must explicitly specify the following in your design: A differential input buffer Two SE output buffers with OE controlled by the same signal A signal splitter which connects the two SE output buffers Assign I/O standard to the bidirectional pins with the BLVDS I/O standard for Cyclone III devices, or 2.5-V Differential SSTL Class I or Class II for Stratix III or Stratix IV devices Its functions are to receive a serial data stream from the FPGA core through doutp input port, create an inverted version of the data, and transmit the data through the two SE output buffers connected to the p and n bidirectional pins. During a read operation, the differential input buffer receives the data from the bus through the p and n bidirectional pins, and sends the serial data to the FPGA core through din port. Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008 Altera Corporation
Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices 2 7 Design Example The OE port provides output enable signal from the FPGA core to enable or disable the SE output buffers. The OE signal should be kept low to tri-state the output buffers during read operation. The function of the AND gate is to stop the transmitted signal from going back into the FPGA core while the differential input buffer is always enabled. f You can download the design examples from the application notes web page at www.altera.com/literature/lit-an.jsp. Figure 5. Design Example of a Block Diagram The block diagram of the design example in the Quartus II software is illustrated in Figure 5. Procedure f For more information about the ALTIOBUF megafunction, refer to the I/O Buffer Megafunction (ALTIOBUF) User Guide. The following steps describe the design flow for the design example. It is assumed that you are familiar with creating a new project in the Quartus II software. The illustrations in this section assumes Cyclone III device. They are applicable to Stratix III and Stratix IV devices. Make sure you select the right device. 1. To create the SE output buffers, instantiate ALTIOBUF Megafunction using MegaWizard Plug-in Manager. Configure the module as an output buffer, enter 1 for the What is the number of buffers to be instantiated box, and check the Use output enable port(s) option as shown in Figure 6. November 2008 Altera Corporation Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices
2 8 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices Design Example Figure 6. Configuring BLVDS SE Output Buffer 2. To create the differential input buffer, instantiate ALTIOBUF megafunction. Configure the module as an input buffer, enter 1 for the What is the number of buffers to be instantiated box, and check the use differential model option as shown in Figure 7. Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008 Altera Corporation
Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices 2 9 Design Example Figure 7. Configuring BLVDS Differential Input Buffer 3. Instantiate the signal splitter function. To do so, in the Edit menu, select Insert Symbol. Select pdo symbol under Project directory. This is a custom function that comes with the design example. By using this function, the inversion of the data input from the core is implemented in the IO element to ensure minimum skew between the p and n output signals. 4. Connect the modules and the input and output ports as shown in Figure 5. 5. In Assignment Editor, assign BLVDS I/O standard to the bidirectional p and n pins for Cyclone III devices as shown in Figure 8. For Stratix III or Stratix IV devices, assign Differential 2.5-V SSTL Class I or II. You can also set the current strength and slew rate options. Otherwise, the Quartus II software assumes the default settings. Figure 8. BLVDS I/O Assignment in Quartus III Assignment Editor 6. Compile and perform timing simulation using the vector waveform file (BLVDS.vwf). Figure 9 illustrates the simulation waveforms. November 2008 Altera Corporation Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices
2 10 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices Performance Analysis Figure 9. Example of Timing Simulation Results Performance Analysis Performance analysis of a multipoint BLVDS based on the Cyclone III BLVDS input output buffer information specification (IBIS) model simulation in HyperLynx is presented in this section. The analyses demonstrate the impacts of bus termination, loading, driver and receiver characteristics, and locations on the performance of the system. You should use Stratix III or Stratix IV 2.5-V Differential SSTL IBIS model for the simulation if you use Stratix III or Stratix IV devices. f System Setup You can download the Cyclone III and Stratix III IBIS models at http://www.altera.com/support/software/download/ibis/ibsibis_index.jsp?gsa_pos=1&wt.oss_r=1&wt.oss=ibis. Figure 10 illustrates the schematic of a multipoint topology loaded with ten Cyclone III BLVDS transceivers (named U1, U2, U10). The bus transmission line is assumed to be a stripline of characteristic impedance of, characteristic capacitance of 3.6 pf per inch and length 10 inches. The bus differential characteristic impedance is approximately 100 Ω. The spacing between each transceiver is 1 inch. The bus is terminated at both ends with termination resistor R T. Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008 Altera Corporation
Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices 2 11 Performance Analysis Figure 10. Multipoint BLVDS with Cyclone III BLVDS Transceivers 3.3 V 3.3 V 130 KΩ 130 K Ω R T R T 100 KΩ GND 100 K Ω GND OE Cyclone III Device OE Cyclone III Device OE Cyclone III Device R S R S R S R S R S R S U1 U2 U10 Output data Input data Output data Input data Output data Input data Fail-safe biasing resistors of 130 kω and 100 kω are used to pull the bus to a known state when all the drivers are tri-stated, removed or powered off. The magnitude of the fail-safe resistors should be one to two orders higher than R T to prevent excessive loading to the driver and waveform distortion. The mid-point of the fail-safe bias should be close to the offset voltage of the driver (+1.25-V) to prevent a large common-mode shift from occurring between active and tri-state bus conditions. The bus can be powered off by common 2.5-V or 3.3-V power supplies. The Cyclone III BLVDS transceivers assume default 12 ma drive strength and slow slew rate settings, unless otherwise stated. The pin capacitance of each transceiver is 6 pf. The stub on each BLVDS transceiver is a 1-inch microstrip of characteristic impedance of and characteristic capacitance of 3 pf per inch. The capacitance of the connection (connector, pad, and via in PCB) of each transceiver to the bus is assumed to be 2 pf. Hence, the total capacitance of each load is approximately 11 pf. For 1-inch load spacing, the distributed capacitance is equal to 11 pf per inch. An impedance matching resistor R S is placed at the output of each transceiver to reduce reflection caused by the stubs, and also to attenuate the signals coming out of the driver. November 2008 Altera Corporation Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices
2 12 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices Performance Analysis Bus Termination Substituting the bus characteristic capacitance and the distributed capacitance per unit length of the above setup into Equation 1, the effective impedance of the fully loaded bus is 52 Ω. R T should be matched to 52 Ω for optimum signal integrity. Figure 11 to Figure 14 illustrate the effects of matched-, under-,and over-termination on the differential waveform (V ID ) at the receiver input pins. The data rate is 100 Mbps. For Figure 11 and Figure 12, U1 acts as the transmitter and U2 to U10 are the receivers, whereas for Figure 13 and Figure 14, U5 is the transmitter and the rest are receivers. For both cases, under-termination (R T = 25 Ω) results in reflections and the noise margin is greatly reduced, in some case even violated the receiver threshold, V TH = ± 100 mv. When R T is changed to, there is a substantial noise margin with respect to V TH and the reflection is negligible. Figure 11. Effect of Bus Termination (Driver in U1, Receiver in U2) 0.6 0.4 RT = 50 Ohm RT = 25 Ohm RT = 85 Ohm +VTH -VTH 0.2 V ID (V) 0.0-0.2-0.4-0.6 5 10 15 20 25 30 35 Time (ns) Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008 Altera Corporation
Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices 2 13 Performance Analysis Figure 12. Effect of Bus Termination (Driver in U1, Receiver in U10) 0.6 0.4 RT = 50 Ohm RT = 25 Ohm RT = 85 Ohm +VTH -VTH 0.2 V ID (V) 0.0-0.2-0.4-0.6 5 10 15 20 25 30 35 Time (ns) November 2008 Altera Corporation Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices
2 14 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices Performance Analysis Figure 13. Effect of Bus Termination (Driver in U5, Receiver in U6) 0.6 0.4 RT = 50 Ohm RT = 25 Ohm RT = 85 Ohm +VTH -VTH 0.2 V ID (V) 0.0-0.2-0.4-0.6 5 10 15 20 25 30 35 Time (ns) Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008 Altera Corporation
Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices 2 15 Performance Analysis Figure 14. Effect of Bus Termination (Driver in U5, Receiver in U10) 0.6 0.4 RT = 50 Ohm RT = 25 Ohm RT = 85 Ohm +VTH -VTH 0.2 V ID (V) 0.0-0.2-0.4-0.6 5 10 15 20 25 30 35 Time (ns) The relative position of the driver and receiver on the bus also affects the received signal quality. It is observed that the nearest receiver to the driver experiences worst transmission line effect because at this location, the edge rate is the fastest. This is made worse when the driver is located at the middle of the bus. For example, compare Figure 11 and Figure 13, V ID at receiver U6 (driver at U5) shows larger ringing than that at receiver U2 (driver at U1). On the other hand, edge rate is slowed down when receiver is located further away from the driver. The largest rise time recorded is 1.14 ns with the driver located at one end of the bus (U1) and the receiver at the other end (U10) of the bus. November 2008 Altera Corporation Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices
2 16 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices Performance Analysis Stub Length Figure 15 compares the V ID at U10 when stub length is increased from 1 inch to 2 inches and the driver is at U1. Longer stub length not only increases the flight time from the driver to the receiver, but also results in larger load capacitance, which causes larger reflection. Figure 15. Effect of Increasing Stub Length (Driver in U1, Receiver in U10) 0.5 0.4 1 inch stub 2 inch stub 0.3 0.2 0.1 V ID (V) 0.0-0.1-0.2-0.3-0.4-0.5 12.0 14.0 16.0 18.0 20.0 22.0 24.0 26.0 28.0 Time (ns) Stub Termination It is important to match the driver impedance to the stub characteristic impedance. Placing a series termination resistor R S at the driver output greatly reduces adverse transmission line effect caused by long stub and fast edge rates. In addition, R S can be changed to attenuate the V ID to meet the specification of the receiver. Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008 Altera Corporation
Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices 2 17 Performance Analysis Figure 16 compares the V ID at U2 and U10 when U1 is transmitting. Figure 16. Effect of Stub Termination (Driver in U1, Receiver in U2 and U10) 1.2 0.8 RS=50 Ohm; U2 RS=50 Ohm; U10 RS=0 Ohm; U2 RS=0 Ohm; U10 0.4 V ID (v) 0.0-0.4-0.8-1.2 5 10 15 20 25 30 35 Time (ns) Driver Slew Rate Figure 17 shows the driver slew rate effect. Comparison is made between slow and fast slew rate with 12 ma drive strength. The driver is at U1 and the differential waveforms at U2 and U10 are examined. Fast slew rate helps to improve rise time, especially at the receiver furthest from the driver. However, faster slew rate also magnifies ringing due to reflection. November 2008 Altera Corporation Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices
2 18 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices Performance Analysis Figure 17. Effect of Driver Edge Rate (Driver in U1, Receiver in U2 and U10) 0.6 fast; U2 slow; U2 fast; U10 0.4 slow; U10 0.2 V ID (V) 0.0-0.2-0.4-0.6 5.0 10.0 15.0 20.0 25.0 30.0 35.0 Time (ns) Overall System Performance The highest data rate supported by a multipoint BLVDS is determined by looking at the eye diagram at the furthest receiver from a driver. At this location, the edge rate of the transmitted signal has slowed the most and affects the eye opening. Even though the quality of the received signal and the noise margin goal depend on the applications, the wider the eye opening the better. However, the receiver nearest to the driver should also be checked because the transmission line effects tend to be worse if the receiver is located closer to the driver. Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008 Altera Corporation
Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices 2 19 Summary Figure 18 illustrates the eye diagrams at U2 (red curve) and U10 (blue curve) for a data rate at 400 Mbps. Random jitter of 1% unit interval is assumed in the simulation. The driver is at U1 with default current strength and slew rate settings. The bus is fully loaded with optimum R T =. It is seen that the smallest eye opening is at U10, which is furthest from U1. The eye height sampled at 0.5 unit interval is 692 mv and 543 mv for U2 and U10, respectively. There is substantial noise margin with respect to V TH = ±100mV for both cases. Figure 18. Eye Diagram at 400 Mbps (Driver in U1, Receiver in U2 and U10) Summary Multipoint BLVDS offers an efficient solution for multipoint backplane applications. A good multipoint design should consider the capacitive load and termination on the bus to obtain better signal integrity. Minimizing the load capacitance can be achieved by selecting transceiver with low pin capacitance, connector with low capacitance and keeping the stub length short. November 2008 Altera Corporation Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices
2 20 Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices Referenced Documents Cyclone III, Stratix III and Stratix IV devices provide low cost, low power solution to the implementation of BLVDS interface in multipoint backplane applications. In addition, the programmable features drive strength and slew rate options enable system designers to customize their multipoint system for maximum performance. The designer should perform simulation or measurement based on their specific system setup and application to determine the maximum data rate supported. Referenced Documents This application note references the following documents: Cyclone III Device I/O Features chapter in volume 1 of the Cyclone III Device Handbook DC and Switching Characteristics chapter in volume 2 of the Cyclone III Device Handbook Cyclone III Early Power Estimator User Guide PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook I/O Buffer Megafunction (ALTIOBUF) User Guide Stratix III Device I/O Features chapter in volume 1 of the Stratix III Device Handbook DC and Switching Characteristics chapter in volume 2 of the Stratix III Device Handbook Stratix IV Device I/O Features chapter in volume 1 of the Stratix IV Device Handbook DC and Switching Characteristics chapter in volume 2 of the Stratix IV Device Handbook Stratix III and Stratix IV Early Power Estimator User Guide Implementing Bus LVDS Interface in Cyclone III, Stratix III, and Stratix IV Devices November 2008 Altera Corporation
Document Revision History Table 2. Document Revision History Table 2 shows the revision history for this application note. Date and Document Version Changes Made Summary of Changes November 2008 Updated to new template v1.1 Updated Introduction chapter July 2008 v1.0 Updated BLVDS Technology in Altera Devices chapter Updated Power Consumption of BLVDS chapter Updated Design Example chapter Replaced Figure 5 on page 7 Updated Procedure chapter Updated Performance Analysis chapter Updated Bus Termination chapter Updated Summary chapter Initial release 101 Innovation Drive San Jose, CA 95134 www.altera.com Technical Support www.altera.com/support Copyright November 2008. Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.