UART. Embedded RISC Microcontroller Core Peripheral

Features New Enhanced Baud Rate Generator Generates Any Required Baud Rate Maximum 6 Mbps (0.35 µm) High Baud Rates at Low Crystal Clock Frequencies 6-, 7-, 8- or 9-bit Data Noise Filtering and Noise Error Detection Automatic Parity Generation and Parity Error Detection Overrun Detection Framing Error Detection False Start Bit Detection Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete Fully Static Operation: 0 to 50 MHz (0.35 µm) Up to 100% Fault Coverage with Scan Test Description The AVR Embedded RISC Microcontroller Core is a low-power, CMOS, 8-bit microprocessor based on the AVR enhanced RISC architecture. With this core, Atmel supplies a full-duplex Universal Asynchronous Receiver and Transmitter (). Figure 1. Pin Configuration Embedded RISC Microcontroller Core Peripheral cp2 ireset runmod dbus_in[7:0] dbus_out[7:0] out_en AVR Control AVR Control cs adr[2:0] iore iowe rx_en rxd txd tx_en rxcirq IRQ txc_irqack txcirq IRQ test_se udreirq Scan Test test_si1 test_si2 test_so1 test_so2 Scan Test Rev. 1130C 01/01 1

Table 1. Pin Description Pin Name Description Direction Comments AVR Control cp2 CPU Clock Input Any register in the will update its contents only on the positive edge of cp2. ireset Synchronous Reset Input When high, ireset will reset internal registers by reading the value on dbus_in, which is forced to zero by the AVR Core. runmod Running Mode Input When high, runmod enables normal functioning of internal logic and interface logic. When low, it disables internal logic. dbus_out[7:0] Data Bus Output Output Valid only when accompanied by a strobe on out_en dbus_in[7:0] Data Bus Input Input Data bus input out_en Output Enable Strobe Output When high, out_en indicates that the requires control of the data bus. cs Chip Select Input When high, adr, iore and iowe are used to access internal I/Os. When low, the cannot be accessed in either read or write mode. adr[2:0] I/O Address Input Valid only when accompanied by a strobe on iore or iowe iore I/O Read Strobe Input Used to read the contents of the I/O location addressed by adr iowe I/O Write Strobe Input Used to update the contents of the I/O location addressed by adr txd Transmit Line Output Transmit data line rxd Receive Line Input Receive data line tx_en Transmit Enable Output When high, tx_en indicates that the transmit line is enabled. rx_en Receive Enable Output When high, rxd_en indicates that the receive line is enabled. Interrupt Request (IRQ) rxcirq Receive Complete IRQ Flag Output This flag (RXC bit in the Status Register) is cleared by ireset or by a read in Data Register and set when a character has been received. txcirq Transmit Complete IRQ Flag Output This flag (TXC bit in the Status Register) is cleared either by ireset, by writing a one to the TXC bit or by an acknowledge provided by txc_irqack. This flag is set when transmit is completed. udreirq UDR Empty IRQ Flag Output This flag (UDRU bit in the USART Status Register) is set by ireset or when data transmission begins and is cleared by a write in Data Register. txc_irqack Transmit Complete IRQ Acknowledge Signal Input When high, this signal indicates that the transmit complete interrupt request has been acknowledged. Test Scan test_se Test Scan Enable Input Test scan enable (active high) test_si1, test_si2 test_so1, test_so2 Test Scan Inputs Input Scan chain inputs Test Scan Outputs Output Scan chain outputs 2

Chip Select (cs) The has the ability to be remapped inside the AVR I/O address range. To access the internal I/O locations of the, the following conditions must be true: 000 adr[2:0] 101 cs = 1 Under these conditions, iore, iowe and adr are used to access the internal I/Os for reading or writing. The cs input may result in the decoding of the three AVR adr MSBs. To obtain the Base Address (BaseAdr) for addressing, use the following code: cs = (adr[5:3] == cs_adr) The binary value {cs_adr[2:0], 000} is the Base Address (BaseAdr) for addressing. Table 2 shows the corresponding BaseAdr for each cs_adr value and the restrictions that are applied. Table 2. BaseAdr Correspondence and Restrictions cs_adr BaseAdr Comments 000 0x00 Allowed 001 0x08 Allowed 010 0x10 Allowed 011 0x18 Allowed 100 0x20 Allowed 101 0x28 Allowed 110 0x30 Allowed 111 0x38 Not Allowed The three bits of adr give the offset, which locates the register required, as shown in Table 3. Table 3. adr Offset and Register adr[2:0] Register 000 I/O Data Register UDR 001 Status Register USR 010 Control Register A UCRA 011 Control Register B UCRB 100 Baud Rate Register Low UBRRLO 101 Baud Rate Register High UBRRHI 11x Unused. Other peripherals may use these addresses. 3

Data Transmission A block diagram of the transmitter is shown in Figure 2. Figure 2. Transmitter dbus_in[7:0] dbus_out[7:0] 8 cp2 /(UOSR + 1) cs adr[2:0] BAUD out_en ireset runmod iore iowe PARITY 8-12-BIT TX rx_en rxcirq txd rxd tx_en txc_irqack MPCM PAR CHRL PE NE CONTROL REGISTER B (UCRB) CONTROL REGISTER A (UCRA) STATUS REGISTER (USR) txcirq udreirq Data transmission is initiated by writing the data to be transmitted to the I/O Data Register (UDR). Data is transferred from UDR to the Transmit Shift Register when: a new character has been written to UDR after the stop bit from the previous character has been shifted out. The shift register is loaded immediately. a new character has been written to UDR before the stop bit from the previous character has been shifted out. The shift register is loaded when the stop bit of the character currently being transmitted has been shifted out. When data is transferred from UDR to the shift register, the UDRE ( Data Register Empty) bit in the Status Register (USR) is set. When this bit is set (one), the is ready to receive the next character. At the same time as the transfer of data from the UDR to the 8-bit-to-12-bit shift register, bit 0 of the shift register is cleared (start bit). If parity is used (PAR not equal to 100), bit Character Length (CHRL) + 1 is loaded with the parity selected and bit Character Length + 2 is set (stop bit). Otherwise, bit Character Length + 1 is set (stop bit). On the baud rate clock following the transfer operation to the shift register, the start bit is shifted out on the TXD pin. The data then follows, with LSB first. When the stop bit has been shifted out, the shift register is loaded if any new data has been written to the UDR during the transmission. During loading, UDRE is set. If there is no new data in the UDR to send 4

when the stop bit is shifted out, the UDRE flag will remain set until UDR is written again. When no new data has been written and the stop bit has been present on TXD for one bit length, the TX Complete Flag (TXC) in USR is set. When CHRL = 11 in the Control Register B (UCRB), transmitted and received characters are 9 bits long plus a start bit, possible parity bit (if used) and stop bit. The ninth data bit to be transmitted is the TXB8 bit in the UCRA. This bit must be set to the required value before a transmission is initiated by writing to the UDR. The TXEN bit in UCRA enables the transmitter when set (one). Data Reception Figure 3 shows a block diagram of the receiver. Figure 3. Receiver dbus_in[7:0] dbus_out[7:0] cp2 /(UOSR + 1) cs adr[2:0] rxd 8-12-BIT RX ireset runmod iore iowe txc_irqack MPCM CHRL PAR CONTROL REGISTER B (UCRB) CONTROL REGISTER A (UCRA) PE NE STATUS REGISTER (USR) PARITY CHECK out_en rx_en tx_en txd txcirq udreirq rxcirq The receiver front-end logic samples the signal on the RXD pin at a frequency (UOSR + 1) times the baud rate. While the line is idle, one single sample of logical zero is interpreted as the falling edge of a start bit, and the start bit detection sequence is initiated. Following the 1-to-0 transition, the receiver samples the RXD pin at samples (UOSR/2) + 1, (UOSR/2) + 2, and (UOSR/2) + 3. If two or more of these three samples are found to be logical ones, the start bit is rejected as a noise spike and the receiver starts looking for the next 1-to-0 transition. If, however, a valid start bit is detected, sampling of the data bits following the start bit is performed. These bits are also sampled at samples (UOSR/2) + 1, (UOSR/2) + 2, and (UOSR/2) + 3. The logical value found in at least two of the three samples is taken as the bit value. All bits are shifted into the transmitter shift register as they are sampled. Sampling of an incoming character is shown in Figure 4. 5

Figure 4. Sampling Received Data Note: This figure is valid for UOSR = 15 (16 samples per bit, no parity, 8-bit Character Length When the stop bit enters the receiver, the majority of the three samples must be one to accept the stop bit. If two or more samples are logical zeros, the framing error (FE) flag in the Status Register (USR) is set. Before reading the UDR register, the user should always check the FE bit to detect framing errors. Whether or not a valid stop bit is detected at the end of a character reception cycle, the data is transferred to UDR and the RXC flag in USR is set. UDR is in fact two physically separate registers: one for transmitted data and one for received data. When UDR is read, the Receive Data Register is accessed, and when UDR is written, the Transmit Data Register is accessed. If 9-bit data word is selected (the CHRL = 11 bit in the Control Register B, UCRB), the RXB8 bit in UCRA is loaded with bit 9 in the Transmit Shift Register when data is transferred to UDR. If parity is used, the parity error flag (PE) in the Status Register (USR) is set (Error) or cleared according to the parity selected, PAR in Control Register B (UCRB). For each bit of the received character including the parity bit (if used) and the stop bit, noise is detected by using three samples. If the three samples are not identical, the line is considered noisy and the NE bit in USR is set. If, after having received a character, the UDR has not been read since the last receive, the overrun (OR) flag in UCRA is set. This means that the last data byte shifted into the shift register could not be transferred to the UDR and has been lost. The OR flag is buffered, and is updated when the valid data byte in UDR is read. Thus, the user should always check the OR flag after reading the UDR in order to detect any overruns if the baud rate is high or CPU load is high. By clearing the RXEN bit in the UCRA, the receiver is disabled. Multi-processor Communication Mode The multi-processor communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address byte to find out which MCU has been addressed. If a particular slave MCU has been addressed, it will receive the following data bytes as normal, while the other slave MCUs will ignore the data bytes until another address byte is received. For an MCU to act as a master MCU, it should enter 9-bit transmission mode (CHRL = 11 in UCRB). The ninth bit must be one to indicate that an address byte is being transmitted and zero to indicate that a data byte is being transmitted. For the slave MCUs, the mechanism appears slightly different for 8-bit and 9-bit reception modes. In 8-bit reception mode (CHRL = 10 in UCRB), the stop bit is one for an address byte and zero for a data byte. In 9-bit reception mode (CHRL = 11 in UCRB), the ninth bit is one for an address byte and zero for a data byte, whereas the stop bit is always high. The following procedure should be used to exchange data in multi-processor communication mode: 1. All slave MCUs are in multi-processor communication mode (MPCM in UCRB is set). 2. The master MCU sends an address byte and all slaves receive and read this byte. In the slave MCUs, the RXC flag in UCRA will be set as normal. 3. Each slave MCU reads the UDR and determines if it has been selected. If so, it clears the MPCM bit in UCRB, otherwise it waits for the next address byte. 4. For each received data byte, the receiving MCU will set the receive complete flag (RXC in UCRA). In 8-bit mode, the receiving MCU will also generate a framing error (FE in UCRA set), since the stop bit is zero. The other slave MCUs, which still have the MPCM bit set, will ignore the data byte. In this case, the UDR and the RXC or FE flags will not be affected. 5. After the last byte has been transferred, the process repeats from step 2. 6

Control I/O Data Register UDR Bit 7 6 5 4 3 2 1 0 BaseAdr + 0 MSB LSB UDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 The UDR is actually two physically separate registers sharing the same I/O address. When writing to the register, the Transmit Data Register is written. When reading from UDR, the Receive Data Register is read. Status Register USR Bit 7 6 5 4 3 2 1 0 BaseAdr + 1 RXC TXC UDRE FE OR PE NE USR Read/Write R R R R R R R R Initial value 0 0 1 0 0 0 0 0 The USR is a read-only register providing information on the status. Bit 7 RXC: Receive Complete This bit is set (one) when a received character is transferred from the Receiver Shift Register to the UDR. The bit is set regardless of any detected framing errors. When the RXCIE bit in UCRA is set, the Receive Complete interrupt will be raised when RXC is set (one). RXC is cleared by reading UDR. When interrupt-driven data reception is used, the Receive Complete Interrupt routine must read UDR in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates. Bit 6 TXC: Transmit Complete This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift Register has been shifted out and no new data has been written to UDR. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCRA is set, setting of TXC causes the Transmit Complete interrupt to be raised. TXC can be cleared by hardware when executing the corresponding interrupt handling vector. This is acheived by decoding the irqackad and irqack signals from the AVR embedded core and generating the txc_irqack signal. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the bit. Bit 5 UDRE: Data Register Empty This bit is set (one) when a character written to UDR is transferred to the Transmit Shift Register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDRIE bit in UCRA is set, the Transmit Complete interrupt is raised when UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven data transmission is used, the Data Register Empty Interrupt routine must write UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt routine terminates. UDRE is set (one) during reset to indicate that the transmitter is ready. Bit 4 - FE: Framing Error This bit is set if a Framing Error condition is detected, i.e., when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one. 7

Bit 3 OR: Overrun Flag This bit is set if an Overrun condition is detected, i.e., when a character already present in the UDR is not read before the next character has been shifted into the Receiver Shift Register. The OR bit is buffered, which means that it will be updated once the valid data still in UDR is read. The OR bit is cleared (zero) when data is received and transferred to UDR. Bit 2 PE: Parity Error This bit is set whenever the parity of the received character does not match current parity (PAR bits in UCRB). The PE bit is updated at each new received character. Bit 1 NE: Noise Error This bit is set when noise has been detected (three samples not identical) during the last reception (including the parity and the stop bit). The NE bit is updated at each new received character. Bit 0 Reserved Bit This bit always reads as zero. Control Register A UCRA Bit 7 6 5 4 3 2 1 0 BaseAdr + 2 RXCIE TXCIE UDRIE RXEN TXEN RXB8 TXB8 UCRA Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial value 0 0 0 0 0 0 1 0 Bit 7 - RXCIE: RX Complete Interrupt Enable When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Complete Interrupt routine to be executed provided that global interrupts are enabled. Bit 6 - TXCIE: TX Complete Interrupt Enable When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Complete Interrupt routine to be executed provided that global interrupts are enabled. Bit 5 - UDRIE: Data Register Empty Interrupt Enable When this bit is set (one), a setting of the UDRE bit in USR will cause the Data Register Empty Interrupt routine to be executed provided that global interrupts are enabled. Bit 4 - RXEN: Receiver Enable This bit enables the receiver when set (one). When the receiver is disabled, the RXC, OR and FE status flags cannot become set. If these flags are set, turning off RXEN does not cause them to be cleared. Bit 3 - TXEN: Transmitter Enable This bit enables the transmitter when set (one). If disabling the transmitter is requested while transmitting a character, the transmitter is not disabled before the character in the shift register plus any following character in the UDR has been completely transmitted. Bit 2 - Reserved Bit This bit always reads as zero and should always be written as zero. Bit 1 - RXB8: Receive Data Bit 8 When CHRL = 11, RXB8 is the ninth data bit of the received character. Bit 0 - TXB8: Transmit Data Bit 8 When CHRL = 11, TXB8 is the ninth data bit in the character to be transmitted. 8

Control Register B UCRB Bit 7 6 5 4 3 2 1 0 BaseAdr + 3 MPCM PAR2 PAR1 PAR0 CHRL1 CHRL0 UCRB Read/Write R R/W R/W R/W R/W R R/W R/W Initial value 0 1 0 0 0 0 1 0 Bit 7 Reserved Bit This bit is a reserved bit and is always read as zero and should be written as zero. Bit 6 MPCM: Multi-processor Communication Mode This bit is used to enter multi-processor communication mode. The bit is set when the slave MCU waits for an address byte to be received. When the MCU has been adressed, the MCU switches off the MPCM bit and starts data reception. Bits 5..3 PAR: Parity Mode Selection These bits select the parity to be generated when transmitting and checked when receiving. The following modes can be selected: PAR Mode 000 Even parity 001 Odd parity 010 Parity forced to 0 (space) 011 Parity forced to 1 (mark) 1xx No parity The actual sequence of bits transmitted and received by the is: Start bit + 6, 7, 8 or 9 (depending on CHRL) Data Bits + Parity Bit (only if parity is used) + Stop Bit Note that the default value after reset is 100, i.e., no parity is used. Bit 2 Reserved Bit This bit is a reserved bit and is always read as zero and should be written as zero. Bits 1..0 CHRL: Character Length These bits select the width of the data words to be transmitted and received according to the following table: CHRL Character Length 00 6 bits 01 7 bits 10 8 bits 11 9 bits Note that the default value after reset is 10, i.e., 8-bit characters are used. 9

Baud Rate Generator The baud rate generator is a frequency divider that generates baud rates according to the following equation: BAUD = ----------------------------------------------------------------- fcp2 ( UOSR + 1) ( UBRR + 1) where: BAUD = Baud rate fcp2 = Master Clock frequency UBRR = Contents of the Baud Rate Register, UBRR (0-2047) UOSR = Contents of the Oversampling Register (7-31) For standard crystal frequencies, the most commonly used baud rates can be generated by using the UBRR and UOSR settings in Table 4. UBRR and UOSR values that yield an actual baud rate differing less than 2% from the target baud rate are in bold face in the table. However, the use of baud rates with more than 1% error is not recommended, as high error ratings give less noise resistance. Baud Rate Register Low UBRRLO Bit 7 6 5 4 3 2 1 0 BaseAdr + 4 UBRR7 UBRR6 UBRR5 UBRR4 UBRR3 UBRR2 UBRR1 UBRR0 UBRRLO Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 The UBRRLO holds the eight least significant bits of the 11-bit UBRR internal register that define the baud rate used by specifying the number of clock cycles between two consecutive samples. See Data Reception on page 5. Baud Rate Register High UBRRHI Bit 7 6 5 4 3 2 1 0 BaseAdr + 5 UOSR4 UOSR3 UOSR2 UOSR1 UOSR0 UBRR10 UBRR9 UBRR8 UBRRHI Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 1 1 1 1 0 0 0 Bits 7..3 UOSR: Over Sampling Register This value defines the number of samples to take for each bit interval. See Data Reception on page 5. Together with the UBRR, UOSR is used to generate an accurate baud rate. Permitted values for UOSR are from 7 to 31. Note that default value is 15, so 16 samples are taken per bit interval by default. Bits 2..0 UBRR High Bits These are the three most significant bits of the 11-bit baud rate register (UBRR). 10

Table 4. UBRR Settings at Various Crystal Frequencies Baud Rate 1 MHz % Error 1.8432 MHz % Error 2400 UOSR=15 UBRR=25 0.16 UOSR=15 UBRR=47 0.00 4800 UOSR=15 UBRR=12 0.16 UOSR=15 UBRR=23 0.00 9600 UOSR=25 UBRR=3 0.16 UOSR=15 UBRR=11 0.00 14400 UOSR=22 UBRR=2 0.64 UOSR=15 UBRR=7 0.00 19200 UOSR=25 UBRR=1 0.16 UOSR=15 UBRR=5 0.00 28800 UOSR=16 UBRR=1 2.12 UOSR=15 UBRR=3 0.00 38400 UOSR=12 UBRR=1 0.16 UOSR=15 UBRR=2 0.00 57600 UOSR=16 UBRR=0 2.12 UOSR=15 UBRR=1 0.00 115200 UOSR=8 UBRR=0 3.55 UOSR=15 UBRR=0 0.00 Baud Rate 2 MHz % Error 2.4576 MHz % Error 2400 UOSR=15 UBRR=51 0.16 UOSR=15 UBRR=63 0.00 4800 UOSR=15 UBRR=25 0.16 UOSR=15 UBRR=31 0.00 9600 UOSR=25 UBRR=7 0.16 UOSR=15 UBRR=15 0.00 14400 UOSR=22 UBRR=5 0.64 UOSR=18 UBRR=8 0.19 19200 UOSR=25 UBRR=3 0.16 UOSR=15 UBRR=7 0.00 28800 UOSR=22 UBRR=2 0.64 UOSR=16 UBRR=4 0.39 38400 UOSR=25 UBRR=1 0.16 UOSR=15 UBRR=3 0.00 57600 UOSR=16 UBRR=1 2.12 UOSR=20 UBRR=1 1.58 115200 UOSR=16 UBRR=0 2.12 UOSR=20 UBRR=0 1.58 Baud Rate 3 MHz % Error 3.2768 MHz % Error 2400 UOSR=24 UBRR=49 0.00 UOSR=20 UBRR=64 0.02 4800 UOSR=24 UBRR=24 0.00 UOSR=21 UBRR=30 0.10 9600 UOSR=23 UBRR=12 0.16 UOSR=30 UBRR=10 0.10 14400 UOSR=15 UBRR=12 0.16 UOSR=18 UBRR=11 0.19 19200 UOSR=12 UBRR=11 0.16 UOSR=18 UBRR=8 0.19 28800 UOSR=12 UBRR=7 0.16 UOSR=18 UBRR=5 0.19 38400 UOSR=12 UBRR=5 0.16 UOSR=16 UBRR=4 0.39 57600 UOSR=12 UBRR=3 0.16 UOSR=18 UBRR=2 0.19 115200 UOSR=12 UBRR=1 0.16 UOSR=27 UBRR=0 1.59 11

Baud Rate 3.6864 MHz % Error 4 MHz % Error 2400 UOSR=15 UBRR=95 0.00 UOSR=15 UBRR=103 0.16 4800 UOSR=15 UBRR=47 0.00 UOSR=15 UBRR=51 0.16 9600 UOSR=15 UBRR=23 0.00 UOSR=15 UBRR=25 0.16 14400 UOSR=15 UBRR=15 0.00 UOSR=30 UBRR=8 0.44 19200 UOSR=15 UBRR=11 0.00 UOSR=15 UBRR=12 0.16 28800 UOSR=15 UBRR=7 0.00 UOSR=22 UBRR=5 0.64 38400 UOSR=15 UBRR=5 0.00 UOSR=25 UBRR=3 0.16 57600 UOSR=15 UBRR=3 0.00 UOSR=22 UBRR=2 0.64 115200 UOSR=15 UBRR=1 0.00 UOSR=16 UBRR=1 2.12 Baud Rate 4.9152 MHz % Error 5 MHz % Error 2400 UOSR=15 UBRR=127 0.00 UOSR=14 UBRR=138 0.08 4800 UOSR=15 UBRR=63 0.00 UOSR=25 UBRR=39 0.16 9600 UOSR=15 UBRR=31 0.00 UOSR=25 UBRR=19 0.16 14400 UOSR=30 UBRR=10 0.10 UOSR=28 UBRR=11 0.44 19200 UOSR=15 UBRR=15 0.00 UOSR=25 UBRR=9 0.16 28800 UOSR=18 UBRR=8 0.19 UOSR=28 UBRR=5 0.64 38400 UOSR=15 UBRR=7 0.00 UOSR=25 UBRR=4 0.16 57600 UOSR=16 UBRR=4 0.39 UOSR=28 UBRR=2 0.22 115200 UOSR=20 UBRR=1 1.59 UOSR=21 UBRR=1 1.36 Baud Rate 7.3728 MHz % Error 8 MHz % Error 2400 UOSR=15 UBRR=191 0.00 UOSR=15 UBRR=207 0.16 4800 UOSR=15 UBRR=95 0.00 UOSR=15 UBRR=103 0.16 9600 UOSR=15 UBRR=47 0.00 UOSR=28 UBRR=29 0.05 14400 UOSR=15 UBRR=31 0.00 UOSR=14 UBRR=36 0.10 19200 UOSR=15 UBRR=23 0.00 UOSR=15 UBRR=25 0.16 28800 UOSR=15 UBRR=15 0.00 UOSR=30 UBRR=8 0.44 38400 UOSR=15 UBRR=11 0.00 UOSR=25 UBRR=7 0.16 57600 UOSR=15 UBRR=7 0.00 UOSR=22 UBRR=5 0.64 115200 UOSR=15 UBRR=3 0.00 UOSR=22 UBRR=2 0.64 12

Baud Rate 10 MHz % Error 11.0592 MHz % Error 2400 UOSR=14 UBRR=277 0.08 UOSR=15 UBRR=287 0.00 4800 UOSR=25 UBRR=79 0.16 UOSR=15 UBRR=143 0.00 9600 UOSR=25 UBRR=39 0.16 UOSR=15 UBRR=71 0.00 14400 UOSR=28 UBRR=23 0.44 UOSR=15 UBRR=47 0.00 19200 UOSR=25 UBRR=19 0.16 UOSR=15 UBRR=35 0.00 28800 UOSR=28 UBRR=11 0.64 UOSR=15 UBRR=23 0.00 38400 UOSR=25 UBRR=9 0.16 UOSR=15 UBRR=17 0.00 57600 UOSR=28 UBRR=5 0.22 UOSR=15 UBRR=11 0.00 115200 UOSR=28 UBRR=2 0.22 UOSR=15 UBRR=5 0.00 Baud Rate 14.7456 MHz % Error 18.432 MHz % Error 2400 UOSR=15 UBRR=383 0.00 UOSR=15 UBRR=479 0.00 4800 UOSR=15 UBRR=191 0.00 UOSR=15 UBRR=239 0.00 9600 UOSR=15 UBRR=95 0.00 UOSR=15 UBRR=119 0.00 14400 UOSR=15 UBRR=63 0.00 UOSR=15 UBRR=79 0.00 19200 UOSR=15 UBRR=47 0.00 UOSR=15 UBRR=59 0.00 28800 UOSR=15 UBRR=31 0.00 UOSR=15 UBRR=39 0.00 38400 UOSR=15 UBRR=23 0.00 UOSR=15 UBRR=29 0.00 57600 UOSR=15 UBRR=15 0.00 UOSR=15 UBRR=19 0.00 115200 UOSR=15 UBRR=7 0.00 UOSR=15 UBRR=9 0.00 Scan Test Configuration The AVR standard peripheral has been designed with full scan methodology, which results in 100% maximum fault coverage. The coverage is maximum if all non-scan inputs can be controlled and all non-scan outputs can be observed. In order to achieve this, the ATPG vectors must be generated on the entire circuit (top-level), which includes the AVR. The scan test pins can then be connected for serial or parallel scan. 13

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