Characterizing Your PLL-based Designs To Manage System Jitter Rob Sleigh Greg D. Le Cheminant Agilent Technologies Copyright 2008 Agilent Technologies Page 1 Outline A review of digital communications system receiver architectures The important role of Phase locked Loops (PLL) and how they impact jitter performance Characterizing performance (emphasis on PLL Page 2 PLL-Based Designs Manage System Jitter 1
Digital receivers need a clock to control the time when the decision is made on each incoming bit Data Input Decision Circuit Data Output Clock Input Page 3 Where does the receiver clock come from? Clock embedded in the data stream Clock distributed as a lower rate reference clock Transmitter clock sent directly to the receiver A Phase-locked Loop is often used to create the receiver clock Page 4 PLL-Based Designs Manage System Jitter 2
Clock Multiplier PLL converts a Reference Clock to a full-rate System Clock for the Receiver Reference Clock Input Phase Detector Frequency Divider N VCO Full rate clock used at either the transmitter or the receiver Page 5 Receiver PLL can derive a clock from the incoming data stream Data Input D-Flip Flop Data Output Phase Detector VCO Page 6 PLL-Based Designs Manage System Jitter 3
What is the behavior of the PLL when the input signal has jitter? Closed loop φout gain = φin A( = 1+ A( = G( = G( e jφ ( Data Input Phase Detector Phase Error Amplifier Voltage Controlled Oscillator (VCO) Recovered Clock Page 7 VCO can track the jitter of the incoming signal Closed loop φout gain = φin A( = = G( = 1+ A( G( e jφ ( Data Input Phase Detector Phase Error Amplifier Voltage Controlled Oscillator (VCO) Recovered Clock The phase detector effectively extracts the jitter from the input data and tunes the VCO allowing it to track the jittered input Page 8 PLL-Based Designs Manage System Jitter 4
Jitter tracking is frequency dependent Closed loop φout gain = φin A( = = G( = 1+ A( G( e jφ ( Data Input Phase Detector Phase Error Amplifier Voltage Controlled Oscillator (VCO) Recovered Clock Loop gain A( is frequency dependent and generally is large at low frequencies (closed loop gain ~1) and diminishes at high frequencies (closed loop gain approaches 0) Low frequency jitter is transferred to the clock output and high frequency jitter is not Page 9 PLL Jitter Transfer Function (JTF) indicates how the jitter on the recovered clock tracks the jitter of the input φout A( jφ ( Closed loop gain = = = G( = G( e φin 1+ A( Loop Response and OJTF 1.2 1 Jitter Multiplier 0.8 0.6 0.4 0.2 0 1.0E+3 10.0E+3 100.0E+3 1.0E+6 10.0E+6 100.0E+6 Frequency (Hz) Page 10 PLL-Based Designs Manage System Jitter 5
What impact does the JTF have on a receiver and its ability to tolerate jitter? Data Input Decision Circuit Data Output Clock Input Allowing jitter to transfer from the data to the receiver clock can be a good thing. This allows the decision circuit to track the jittered data and still make decisions in the center of the bit period Page 11 What is the effective jitter from the perspective of the receiver decision circuit? Jitter Multiplier 1.2 1 0.8 0.6 0.4 0.2 Loop Response and OJTF As the jitter frequency increases, jitter transferred to the recovered clock rolls off Jitter tracking at the decision circuit is reduced 0 1.0E+3 10.0E+3 100.0E+3 1.0E+6 10.0E+6 100.0E+6 Frequency (Hz) Page 12 PLL-Based Designs Manage System Jitter 6
From the receiver s perspective, the PLL performs a jitter high-pass OJTF Jitter Multiplier 1.2 1 0.8 0.6 0.4 0.2 jφ ( = 1-G( = 1 G( e All the higher frequency Loop Response and OJTF 0 1.0E+3 10.0E+3 100.0E+3 1.0E+6 10.0E+6 100.0E+6 Frequency (Hz) jitter on the data stream is observed at the decision circuit Jitter observed at the decision circuit is effectively the complement of the PLL jitter transfer function The receiver Observed Jitter Transfer Function (OJTF) effectively acts like a jitter high-pass filter Page 13 To take advantage of the PLL jitter filtering properties, it is useful to observe jitter in the frequency domain Magnitude Frequency Offset frequency Page 14 PLL-Based Designs Manage System Jitter 7
E5052B (SSA : Signal Source Analyzer) provides a wide variety of clock oscillator measurements including the phase noise/jitter spectrum Component Evaluation Reference Source Phase Noise VCO Phase Noise AM Noise Tuning Sensitivity Oscillator/PLL Circuit Design Loop Filter (PLL Response) Phase Noise RF Transient Spurs Harmonics Verification/Test at Operating Conditions Microphonic Phase-hits Page 15 Using the hardware clock recovery system of the 86100C DCAj wide-bandwidth sampling oscilloscope ADC Data or Clock Input Phase Detector VCO Similar to PLL s discussed earlier, the output of the phase detector is effectively the demodulated jitter of the input. Monitoring this signal with an analog-to-digital converter and transforming the results into the frequency domain provides the jitter spectrum Page 16 PLL-Based Designs Manage System Jitter 8
Spectral lines indicate periodic jitter elements 1E-6 100E-9 Jitter Spectrum SSC and its odd harmonics 10E-9 Seconds (rm 1 MHz PJ (and harmonic 10E-15 1E-15 33 khz 1 MHz 1E+3 10E+3 100E+3 1E+6 10E+6 100E+6 Delta Frequency (Hz) Jitter Spectrum / Phase Noise Application Rev 0.5 Jitter magnitude in seconds rms versus jitter frequency in Hz (log-log scale) Page 17 The floor of the signal (without tone is effectively the spectrum of the random jitter Jitter Spectrum 1E-6 100E-9 10E-9 1E-9 Seconds (rm 100E- 15 100E- 12 10E-12 1E-12 100E- 15 1E-9 100E- 12 10E-12 1E-12 10E-15 1E-15 1E+3 10E+3 100E+3 1E+6 10E+6 100E+6 Delta Frequency (Hz) Jitter Spectrum / Phase Noise Application Rev 0.5 Page 18 PLL-Based Designs Manage System Jitter 9
Measuring the Jitter Transfer (and Observed Jitter Transfer) Functions Jitter transfer definition: The amount of jitter at the output of a device compared to the jitter that was on the input of the device Page 19 Provide a jittered signal at the DUT input and measure the jitter at the output Pattern Generator Data D.U.T Frequency Synthesizer (Clock) Clock (for calibration) Sinusoid Generator (Jitter modulation) Jitter receiver (clock recovery) Page 20 PLL-Based Designs Manage System Jitter 10
Stimulus: N4903 JBERT (jittered clock or data) Alternate: Any PG or source that can be modulated with a 33250 function generator (81134, 81142A etc.) Page 21 Stimulus: Jittered Clock sources N5182A MXG 81150A Pulse Function Arbitrary Noise Generator OR Page 22 PLL-Based Designs Manage System Jitter 11
Response receiver: 86100C DCAj with 86108 or 83496B Page 23 Examples of device types Clock recovery circuit Clock multiplier circuit Transmitter with ref. clock Repeater circuit Page 24 PLL-Based Designs Manage System Jitter 12
Measurement result examples Page 25 86100CU-400 PLL and Jitter Spectrum Measurement Software controls hardware Software: Automated PLL Bandwidth Testing Fast, Accurate measurements Flexible system architecture Microsoft Excel based SW Free web download www.agilent.com/find/jtf Features: - Measure Phase Locked Loop (PLL) Performance and Jitter Spectrum - PCI-SIG Approved for PCI Express 2.0 PLL Compliance Testing - Automated report generation Page 26 PLL-Based Designs Manage System Jitter 13
Increasing JTF measurement accuracy What are the main sources of inaccuracy? Jitter source flatness and repeatability Jitter receiver flatness and repeatability Page 27 Measurement calibration removes source and receiver unflatness Since the source and receiver are used in both the input and the output measurements, the system unflatness can be determined with a through calibration Calibration measurement response DUT measurement response Jitter transfer= Jitter output/jitter input =(Jitter source)(cable(jitter receiver) =(Jitter source)(cable(dut jitter output response)( jitter receiver =DUT measurement/cal measurement Page 28 PLL-Based Designs Manage System Jitter 14
Calibration when input and output rates do not match If the input to the DUT is at one rate, and the output is another (e.g. clock multiplier) how can a valid calibration be performed? Example: PCI-Express 5 Gb/s transmitter with a 100 MHz reference clock input Jitter receiver needs to observe 2 rates, possible source of measurement uncertainty Solution: Set 86100 receiver at 5 Gb/s. Create 100 MHz reference clock with 25 1 s and 25 0 s pattern from BERT Page 29 What if DUT jitter conflicts with jitter stimulus? If DUT has a significant periodic jitter tone at one of the stimulus frequencies, jitter transfer result could be distorted Solution: 86100C jitter receiver can observe the DUT unstimulated jitter spectrum and has the opportunity to adjust stimulus frequencies to avoid a collision Page 30 PLL-Based Designs Manage System Jitter 15
Putting the puzzle together Knowing both the jitter spectrum and the jitter transfer allows a system level analysis of how jitter is propagating and being controlled in a communications system The jitter spectrum (left) combined with the JTF/OJTF results with the jitter spectrum as seen by the receiver (right). PLL OJTF performs a jitter highpass * = Measure Jitter Spectrum (from device) Measure OJTF * = (e.g. clock recovery PLL) Predict Observed Jitter Spectrum (seen by receiver) Page 31 Low-jitter components contribute to overall jitter budget, but can be difficult to measure Examples: VCO and/or divider circuits in PLL s Residual jitter of the oscilloscope can be larger than the jitter of the DUT Page 32 PLL-Based Designs Manage System Jitter 16
New capabilities for analyzing very low jitter circuit elements (clock or data) Residual jitter of sampling scopes hit ~200 fs in 2002 (Agilent 86107A Precision Timebase) When precision timebase is integrated with sampling channels and the HW clock recovery system, scope jitter floor is below 60 fs Allows ultra-low jitter measurements of precision devices Page 33 86108A Precision Waveform Analyzer: A gold standard for waveform analysis New plug-in module for the 86100C DCAj 2 CH at >32 GHz Low noise, ultra-low jitter (<60fs typical) Precision waveform measurements Integrated clock recovery for single connection measurement (no trigger required) PLL/Jitter Transfer/Jitter Spectrum ~0 trigger to sample delay allows accurate analysis in the presence of SSC Page 34 PLL-Based Designs Manage System Jitter 17
Conclusions PLL s provide opportunities to manage jitter in high-speed serial bus communications Combining knowledge of the jitter spectrum and the jitter transfer/observed jitter transfer can lead to optimal designs Test systems available to provide accurate analysis Page 35 PLL-Based Designs Manage System Jitter 18