BOUNDARY SCAN TESTING FOR MULTICHIP MODULES Stephen C. Hilla Environmental Research Institute of Michigan P.O. Box 134001 Ann Arbor, Michigan 48 1 13 An application of boundary scan testing in the development of a multichip module based image processing computer is presented. The application uniquely combines boundary scan testing and probe card technology with electrically programmable substrates to thoroughly test the multichip modules during and after assembly. Boundary scan testing is used extensively to test components and verify interconnect in this application where access to internal nodes on the module is extremely limited. 1.O Introduct i oq This paper describes several ways in which boundary scan testing (compliant with the IEEE Standard 1149.1) is being used in the development of a multichip module (MCM) based image processing computer. The computer contains 12 MCMs densely stacked in an enclosure approximately the size of a shoe box. This ultra high density project provides a unique opportunity for boundary scan testing to be exercised to its fullest extent. Throughout the MCM assembly process and during system integration, boundary scan testing is used to test component-to-component interconnects and perform limited amounts of functional testing. Without boundary scan testing, this type of application would not be practical. Provided below is a description of the testing techniques being employed which uniquely combine boundary scan testing and probe card technology with electrically programmable substrates to test the MCM during and after assembly. Also presented are several techniques which are being used to enhance the test coverage. These techniques include: the control of the system clock with the 1149.1 scan chain: the use of user defined "test data registers" within ASICs; and the distribution of the scan chain across multiple modules for system testing. Many of the techniques presented are tailored for this unique application. However, these techniques can also be incorporated into a variety of other applications involving boundary scan testing. The term "multichip module'' describes many different types of miniaturized, high density, electronic assemblies. In this application, the MCM consists of a four inch diameter, electrically programmable, silicon substrate which serves as the "Silicon Circuit Board" for the unpackaged die which are attached to the substrate. This silicon-on-silicon application also uses multiple layers of programmable substrates to reduce the cost of the MCMs and increase testability, see Figure 1. The larger of the two silicon substrates is referred to as the "base wafer". The base wafer has a limited number of die attached to it and in most cases the die consist of buffers which are placed near the outer edge of the wafer. These buffers are used to transmit and receive signals to and from other modules in the system. The base wafer can support as many as four smaller silicon substrates, approximately 1.25 in2, which are referred to as "secondary substrates". These secondary substrates, much like the base wafer, contain a large number of routing resources which can be electrically fused together to meet the interconnect requirements of the components. The secondary substrate's surface is essentially a grid of die attachment sites, thus making it the primary component carrier. The actual substrate programming is done using two probes to apply a relatively large potential (approximately 40 volts) across an antifuse element[l]. The unprogrammed antifuses serve as high impedance paths, or open circuits, between the vertical and horizontal routing resources. A potential placed across the antifuse "blows" the fuse and creates an electrical short between the selected resources. The substrates are first programmed and then the bare die components are attached. Electrical connection between the component's I/O pads and the substrate are established using wire bonds. After the secondary substrate is assembled, it is then attached to the base wafer. Wire bonds are again used to electrically connect the secondary substrate to the base wafer. The entire assembly is placed 224 INTERNATIONAL TEST CONFERENCE 1992 0-81 86-31 67-8192 $3.00 1992 IEEE
Secondary Substrate Base wafer in a frame which provides both structural support and components themselves. Identifying faulty components, electrical access to the YO, see Figure 2. The ~ n~ec~or~ su'bstrates, and wire bonds early on in the assembly process (which are part of the frame) are electrically con greatly reduces the overall cost of the MCMs. the base wafer through a wire bonded to the base w assembly is called a "module". During several stages of the assembly process described above, boundary scan testing is used to verify e component-to-component interconnects and to test the Thie Fit application of boundary Scan testing occurs during the early stages of the MCM assembly process. After the nents are attached to the secondary substrate and the e ~ ~ connections ~ ~ ~ are c made ~ using i wire bonds, the Flex Circuit Connector =-+ Flex Circuit wafer Figure 2. Fully ~~~b~ Wafer with Connector Frame Attached 225
substrate is placed in a test fixture which aligns the needles on a probe card with the VO pads located on the outer edge of the substrate. The probe card is a custom fiberglassepoxy printed circuit board (PCB) which has a circular opening in the middle that is slightly larger than the substrate being tested, see Figure 3. The hole is lined with one or more rows of needles which are electrically Therefore, by electrically connecting the probe card needles to the scan component's VO pins, the probe card can be software configured to interface with almost any digital design implemented on the secondary substrates! By scanning in the appropriate output control bit, each bidirectional I/O pin within the probe card components is configured to be either an input or outpus the output can Needle \ PCB 13.. Resistor / Networks 1 Scan Path Figure 3. Secondary Substrate Probe Card with Boundary Scan Components connected to components on the probe card. In this particular application, the secondary substrate probe card contains 280+ needles which touch down on the substrate's YO Pads. Attached to the probe card are several components which have boundary scan capability. These components are used solely for their scan capability. The functional logic within the components is unused. The components selected were specifically chosen because each pin on the components is configurable as either an input or output under the control of the scan chain, see Figure 4. also be configured into a high impedance state (tri-stated). The pull-up resistor (seen in Figure 4) is used to pull the tri-stakd output up to a known state (+5 volts). Four of the probe card needles are dedicated to the four 1149.1 signals (TCK, TMS, TDI, TDO). This permits the boundary scan components on the substrates to be included in the same scan chain as the components on the probe card. All of the scan components, both on the probe card and the substrate, are controlled through a single 1149.1 interface residing on the probe card, refer to figure 3. A scan chain controller connects to the probe card through +5v 1 Resistor\ Probecard Boundary i" SCan 4 Cells \ V Boundary Scan Component I/O Pin Figure 4. Electrical Interface between probe Card and Substrate 226
this interface. The controller consist of a personal computer (PC) containing special purpose hardware and software. A separate probe card, similar to the one used to test the secondary substrates, is used to test the base wafer. This probe card is much larger and it has over 400 needles. The base wafer probe card is used at several different stages in the assembly process, particularly after each segment is attached. Surprisingly, the alignment of such a large number of needles with the 1/0 pads on the base wafer requires very little time and effort, The probe cards provide access to most, if not all, of the I/O pads on the periphery of the substrates. This allows the electrical connections between the I/O pads and the components to be easily tested if the components have boundary scan capability. Two examples are later presented which describe how the interconnects are tested when the components have boundary scan capability and when they do not. The programmable feature of the substrates provides access to many of the internal nodes. Since the programming (Pgm) pads at the end of the routing resources are located on the periphery of the substrate, the internal signals can be observed with the probe card, see Figure 5. The programming pads also serve as the I/O pads on the secondary substrate. On the base wafer, the programming pads and the YO pads are separate entities. Therefore, by combining programmable substrates with probe card technology, nearly all of the internal and external electrical nodes are readily observable. Typically, a small number of nets and nodes cannot be accessed with the scan chain. For these cases, the testing is done by manually probing the substrate. 3 1 Interconnect Testing The electrical interconnects are comprised of both the routing resources on the substrate and the bond wires. The interconnects on the substrates are verified by transmitting data from one Boundary Scan Cell (BSC) to another. In this case, the components with scan capability are located om both the probe card and on the substrate. Test vectors are scanned into BSCs on either the probe card or substrate, transmitted over the interconnects, and then captured by a separate set of BSCs. Frequently the test vectors must travel through components, such as random logic, before they can be captured by another scan device. When this occurs, the test vectors are no longer simple patterns; they must be specifically written for the logic they encounter. A!s an example, a test sequence used to test both the Components and interconnects involves applying data to the inputs on the secondary substrate using the probe card's BSCs. The first component encountered by the test vectors is a non-scannable FIFO RAM device. Multiple scan cycles are used to toggle the write clock (WCLK) and write enable (WE) pins on the FIFO to "write" a byte of data into the FIFO. To verify this operation, an ASIC device with boundary scan capability, also located on the substrate, is used in a similar fashion to "read" the other side of the FIFO. This type of mixed testing, both Figure 5. Programming Pads Serve as Access Points for Capturing Internal Signals 227
functional and interconnect, is frequently used since many of the devices do not have scan capability. 3.2 Functional Testing The probe cards are not only used for verifying connectivity but also for performing limited amounts of functional testing. Since the 110 pads on the periphery of the substrate can be simultaneously read or written with the probe card devices, parallel vectors can be applied to the inputs as will occur during normal operation. The only difference is the clock speed during probe card testing (TCK < 6 MHz) is much slower then during normal operation. In synchronous designs, as in this application, it is often necessary to toggle the system clock a specified number of times to allow the scan vectors to propagate through nonscannable, registering devices. To achieve this functionality, the system clock is controlled through the scan chain by inserting a boundary scan component in the path of the system clock before it is distributed to the components on the substrate. During normal operation, the boundary scan component is transparent and passes the clock signal from input to output. However, during boundary scan testing, the output pin is under the control of the scan chain and can be single stepped. As an example, during base wafer interconnect testing, the scan chain controller scans data into the probe card scan components which then apply the data to the input pins on the wafer. The system clock is toggled one time to allow the data to propagate through the registers located inside the input buffers. Internal to the wafer are several ASIC devices with boundary scan capability. The ASIC's input pins capture the data coming from the input buffers. The captured data is scanned back to the scan chain controller for analysis. In this example, not only are the interconnects tested but the registered input buffers are also tested. One of the goals in this MCM project is to add boundary scan capability to all of the ASICs being designed. Once the scan logic is added, additional features are considered to enhance the testability of both the ASIC and the MCM. As an example, two of the ASKS include one of the optional features of the 1149.1 standard. In these two ASICs, a user defined "test data register"[2] [3] was added to the selection of scan registers (bypass and boundary scan) which can be placed between TDI and TDO during the Shift-DR controller state. These optional data registers are selected by scanning in the appropriate user defined instruction. In one ASIC, a 12 bit configuration register can optionally be placed in the scan path to allow the ASIC to be configured through the 1149.1 interface. During normal operation, this configuration register is loaded by an adjacent component on the MCM. However, during testing, this component is held in reset and therefore the ASIC required loading through other means. The actual use of this user defined test data register is described in the text that follows. The configuration register is placed in the scan path by scanning in the user defined instruction. Next, the appropriate configuration bits are shifted into the test data register to configure the ASIC into the desired operating mode. The ASIC is then taken out of the test mode and placed in normal operating mode. With the ASIC configured, data is then applied to its inputs. The system clock is toggled once to register the data present at the inputs. The data then propagate through the ASIC. Finally, the outputs of the ASIC are captured using another boundary scan component, in this case another ASIC, located on the substrate. The captured data is scanned back to the scan chain controller were it is compared to a set of expected results. A second example which describes the use of a user defined test data register involved the merging of an ASIC manufacturer's internal scan chain with the 1149.1 boundary scan chain. The ASIC's internal scan chain linked all of the internal registers serially into a large shift register (45OCh bits long). By placing this internal scan chain in the 1149.1 scan path, the entire ASIC can be preloaded into any desired state. In addition, it allows the current state of the ASIC to be captured and scanned back to the scan chain controller for analysis. The same vectors which are used to test the ASIC after it is manufactured can be reapplied using the 1149.1 interface. Using this "preload" capability, the ASIC can be configured to allow functional testing during the MCM assembly process. A fully assembled module is tested prior to system integration to verify the 400+ interconnects located between the module's connectors and the input buffers on the base wafer. This testing is accomplished using custom hardware which is referred to as the "module test board". The module test board is functionally identical to the probe cards; the only difference is the probe card needles are replaced with connectors which mate with the connectors on the Module Under Test (MUT), see Figure 6. The module test board provides access to all of the VO pins on the MUT. In addition, the scan components on the MUT can be accessed through the four pins on its connector dedicated to the 1149.1 signals. Thus, the scan components on the h4ljt can be placed in the scan chain along with the scan components on the module test board. The interconnects between the connectors and the base wafer are tested by transferring data between the scan components on the module test board and those on the MUT. The input buffers on the MUT are custom ASICs with boundary scan capability. Therefore, the actual testing consists of transferring test vectors from the module test board to the input buffers. The data is then captured at the input buffers and scanned back to the scan chain controller for analysis. 228
Module, Under Test Figure 6. Stand-Alone Module Test Setup To further test the module, parallel vectors are applied to the input pins using the boundary scan components on the module test board. The system clock is single stepped an appropriate number of times in order to advance the test vectors to the point where they can be captured by an internal boundary scan component or they propagate off the module and are captured by the module test board's boundary scan components. Once again, controlling the system clock through the scan chain allows numerous components to be functionally tested and reduces the need for manual probing. 5.0 Svstem Testing The testing described up to this point has focused on a single module or subassemblies within the module. This section presents techniques for performing boundary scan resting on the entire system containing multiple modules. The scan chains on the modules are connected to one another by distributing the 1149.1 signals across the system backplane. One module is dedicated as the "host module" for the 1149.1 interface. It contains the interface between the scan chain controller and the rest of the modules in the system, see Figure 7. The host module buffers the scan chain control signals TCK and TlvIS before they are distributed across the backplane; it also buffers the TI11 signal before it travels to the first module in the system. Each module then buffers these three signals (TCK, TMS, and TDI) at the point they are received off the backplane. This reduces the loading on the signals and improves the signal quality. Both TCK and TMS are terminated at the end of the backplane with an appropriate pair of resistors. The TDI and TDO signals are daisychained across the backplane from one module to the next. When the TDO signal exits the last module on the backplane, it is looped back to the host module. On the host module, it is buffered and passed to the scan chain controller. Interface Figure 7. Multiple Modules on a Single Scan Chain 229
Secondary Scan Paths 1149.1 Signals 7 on Backplane Figure 8. Scan Path Linker Adds Hierarchy to System Scan Chain primary Scan Path The 12 multichip modules in the image processing computer communicate to one another over a backplane. Since each module's interface to the backplane is comprised of buffers with boundary scan capability, it is easy to verify the module-@-module connections. The scan chain controller drives test patterns out onto the backplane from one module's interface and captures them at the inputs of another. The captured data is then scanned back to the controller where it is compared to a set of expected results. This technique is especially helpful in identifying problems associated with high pin count connectors such as bent pins or dirty contacts. A typical interconnect verification algorithm consists of a walking "1" and a walking "0" test. To reduce the length of the scan chain, and to facilitate the testing of partially assembled modules, each module contains a Scan Path Linker[4] which partitions the primary scan chain into multiple secondary scan chains, see Figure 8. By scanning in the appropriate control word, the scan path linker selects one or more of the secondary scan path and includes it in the primary scan path. When the testing is focused on a single module in the system, the remainder of the module's scan path linkers are issued the "bypass" instruction. Those modules then function as one bit shift register in the primary scan chain. This technique of introducing a layer of hierarchy into the system scan chain simplifies the complexity of the chain and increases its reliability. 5.0 Conclusion3 Boundary scan testing is playing a vital role in the development of MCMs. The 1149.1 compatible components on the MCMs alone provide limited test coverage. By adding boundary scan components to the probe cards and by taking advantage of the access gained through the programming pads, the necessary level of testability is achieved. The difficulties associated with non-scannable components is overcome by employing techniques which allow these components to be functionally exercised: the system clock is controlled with the scan chain; and two of the ASICs contain user defined test data registers so they can be configured with the scan chain. Through the combination of these testing techniques, the development of a high performance, MCM based, image processing computer is becoming a reality. References [I] H. Stopper, L.C. Harris and S. Choksi, "High Density Multi-Chip Module using an Electrically Programmable Interconnect Substrate," 199 1 NEPCON East Proceedings, pp. 189-198,1991. [2] C.M. Maunder and R.E. Tulloss, "The Test Access Port and Boundary Scan Architectures," IEEE Computer Society Press Tutorial, pp. 191-198, 1990. - [3] IEEE Standard 1149.1 1990, "Standard Test Access Port and Boundary Scan Architecture." [4] Texas Instruments Inc., "Scan Path Linkers with 4- Bit Identification Buses, SN54ACT8997 & SN74ACT8997," TI0286-D3597, April 1990. My thanks go to Jeff Banker, Joe Samson, Brian Smith, Paul Kortesoja, Sandy Harris, Paul Mohan, Bob Horner and John Ackenhusen for their editing comments. Most 230
importantly, I want to thank my loving wife (Cheryl) for all the support and encouragement she gives me. This project is being supported in part by the U.S. Army through CECOM Night Vision Electro-optics Directorate under contract #DAALO2-89-K-O057. 23 1