Boundary Scan. Sungho Kang. Yonsei University

Transcription

1 Boundary Scan Sungho Kang Yonsei University

2 Outiline Introduction TAP Controller Instruction Register Test Data Registers Instructions Hardware Test Innovations PCB Test Conclusion 2

3 Boundary Scan Improve testability by reducing the requirements placed on the physical test equipment Also called JTAG (Joint Test Action Group) Boundary Scan Standards IEEE P Why use it? Testing interconnections among chips Testing each chip Snapshot observation of normal system data Why testing boards? To test board is easier than to test systems Board Test Philosophy As a sorting process As a repair driver As a process monitor 3

4 Boundary Scan Chip Architecture The scan paths are connected via the test bus circuitry Connection from TDI to Sin Connection from TDO to Sout The normal I/O terminals of the application logic are connected through boundary scan cells to the chips I/O pads Operation An instruction is sent serially over the TDI line into the instruction register The selected test circuitry is configured to respond to the instruction The test instruction is executed and then test results can be shifted out of selected registers and transmitted over the TDO to the bus master Possible to shift new data into registers using the TDI while results are shifted out and transmitted over the TDO line 4

5 Boundary Scan Chip Architecture 5

6 Board Test Board containing 4 chips with one serial test path Application logic Application logic TDI Application logic Application logic TDO 6

7 Cost of Boundary Scan Costs 4 or 5 pins - Test Access Port (TAP) 16 state machine - TAP controller Boundary scan register Bypass register - one stage Instruction register - 2 or more stages Impacts Enhanced diagnosis Reduced test-repair looping Standardized tests Reuse of tests Reduced access problems 7

8 Boundary Scan Subject Indicator Design Engineering - IC design - - Reusable test vectors + - Test pattern generation ++ - Board design time - - Board prototyping ++ Manufacture - Test pattern generation ++ - Test time ++ - Material costs - - Diagnosis ++ - Repair + - Retest + - Test equipment costs ++ Commisioning - Diagnosis and repair ++ Field Maintenance - Diagnosis ++ - Replacement and repair + Marketing - Time-to-market ++ 8

9 Test Access Port Consisting of the ports associated with TMS, TCK, TDI and TDO TCK: Test Clock Operate BS part of the ICs synchronously and independently of the built-in system clock TDI : Test Data In Data is shifted in at the rising edge TDO: Test Data Out Data is shifted out at the falling edge TMS: Test Mode Select TMS signals are sampled at the rising edge Controls transitions of controller TRST : Test Reset (Optional) TAP's test logic is asynchronously forced into its reset mode when a logic 0 is applied to TRST 9

10 Test Bus Each chip is considered to be a bus slave and the bus is assumed to be driven a bus master Ring Connection One TMS Star Connection Each chip is associated with its own TMS signal Hybrid Connection Combined 10

11 Ring and Star Test Bus Application chips Application chips TDI TC K TMS #1 TDI TC K TMS #1 Bus master TDO Bus master TDO TDO TDI TMS TCK TDI TC K TMS TDO #2 TDO TDI TMS1 TMS2 TMSN TCK TDI TC K TMS TDO #2 TDI TC K TMS #N TDI TC K TMS #N TDO TDO 11

12 Functions of TAP Controller Generate clock and control signals required for the correct sequence of operations Provide signals to allow loading the instructions into the Instruction Register Provide signals to shift test data into (TDI) and test result data out of (TDO) the shift registers Perform test actions such as capture, shift and test data 12

13 TAP Controller State Diagram Non-shaded states : auxiliary Do not initiate a system action but are included to provide process control 1 0 Test-Logic- Reset Run-Test/Idle Select-DR-Scan Select-IR-Scan Capture-DR 1 Capture-IR 0 0 Shift-DR 0 Shift-IR Exit1-DR 1 Exit-IR Pause-DR 0 Pause-IR Exit2-DR Exit2-DR 1 1 Update-DR Update-IR

14 TAP Controller State Diagram Test-Logic-Reset The test logic is disabled so that the application logic can operate in its normal mode Run-Test/Idle Control state that exists between scan operations and where an internal test, such as built-in self test can be executed Select-DR-Scan Temporary control state If TMS is held low then a scan data sequence for the selected test data register is initiated, starting with a transition to the state Capture-DR Capture-DR Data can be loaded in parallel into the test data registers selected by the current instruction 14

15 TAP Controller State Diagram Shift-DR Test data registers specified by the data in the instruction register, and which lie between TDI and TDO, are shifted one position A new data value enters the scan path via TDI and a new data value now is observed at TDO Other registers hold their state Exit1-DR All test data registers selected by the current instruction hold their state Pause-DR The test data registers in the scan path between TDI and TDO hold their state Often necessary during the transmission of long test sequences Allow synchronization between TCK and system clock signals 15

16 TAP Controller State Diagram Exit2-DR All test data registers selected by the current instruction hold their state Update-DR Test data registers specified by the current instructions and having a latched parallel output feature are loaded from their associated shift registers -IR Similarly defined The states that control instruction register operate similarly to those controlling the test-data registers Instruction register is implemented using a latched parallel output feature 16

17 Test-Logic-Reset All test logic is disabled i.e. all system logic operates normally Whatever the state is, it will enter the Test-Logic-Reset state when the TMS signal is high for at least 5 rising edge of TCK Controller remains this state while TMS is high If TRST is present, it can be used to force the controller to the Test-Logic-Reset state at once Mode Shift/Load TDO Serial Out Mode Test/Normal System Data Mux System Data Mux 1D 1D TDI Serial In Clock Update 17

18 Run-Test/Idle Controller state between the various scan operations Once the controller is in this state, it will stay there as long as the TMS is low The current instruction does not change while the controller is in this state 18

19 Capture-DR Data is parallel-loaded from the parallel inputs into the selected test data register The register retains its previous state if it does not have a parallel input or if capturing is not required for the selected test The action takes place at the rising edge of TCK Mode Shift/Load TDO Serial Out Mode Test/Normal System Data Mux System Data Mux 1D 1D TDI Serial In Clock Update 19

20 Shift-DR The previously captured data is shifted out towards the TDO, one shift register stage on each rising edge of TCK Mode Shift/Load TDO Serial Out Mode Test/Normal System Data Mux System Data Mux 1D 1D TDI Serial In Clock Update 20

21 Update-DR The shifting process has been completed Test data registers may be provided with a latched parallel output This prevents the parallel output from changing while data is shifted into the associated shift register path When these test data registers are selected by an instruction, the new data is latched into their parallel outputs in this state at the falling edge of TCK Mode Shift/Load TDO Serial Out Mode Test/Normal System Data Mux System Data Mux 1D 1D TDI Serial In Clock Update 21

22 Capture-IR Previously shifted-in instruction data is parallel-loaded into the shift-register stage of the instruction register Design specific data may be loaded into a shift register stage which may not be set to a fixed value The IR-path between TDI and TDO can be checked as to whether or not the instructions can be shifted in correctly or not Actions takes place at the rising edge of TCK 22

23 Shift-IR The previously captured data is shifted out towards the TDO, one shift-register stage on each rising edge of TCK Selected test data registers retain their previous state 23

24 Update-IR The shifted-in instruction data is loaded from the shift register stage into the parallel instruction register The new instruction becomes valid when the TAP controller is in this state All the test data shift register stages which are selected by the current instruction retain their previous values Actions takes place at the falling edge of TCK 24

25 Instruction Register Allows instruction to be shifted into chip Can be used to specify operations to be executed and select test data registers Each instruction enables a single serial test data register path between TDI and TDO Instruction may vary per IC on the board Serial-in parallel-out register 25

26 Instruction Register IR must contain at least 2 shift-register-based cells which can hold instruction data These 2 mandatory cells are located nearest to the serial outputs, i.e. they are the least significant bits Used in locating faults through the IC's Set up Instruction Update IR Parallel in/parallel out Clock TDI Shift IR Shift Register 0 1 TDO Capture IR Design specific data 26

27 Instruction Register IR operations in each TAP controller state Controller state Shift register stage Parallel output Test-Logic-Reset Undefined Set to give the IDCODE(or BYPASS) Capture-IR Load 01 into LSBs and Retain last state design-specific data or fixed values into MSBs Shift-IR Shift towards serial Retain last state output Exit1-IR Retain last state Retain last state Exit2-IR Retain last state Retain last state Paste-IR Retain last state Retain last state Update-IR Retain last state Load from shift register stage into decoder All other states Undefined Retain last state 27

28 Test Data Registers Required Boundary Scan Register Bypass Register Optional Device Identification Register : specifies manufacturer, part number, and variant Design Specific Register : for self test, internal scan paths, etc. Unique Name Fixed Length 28

29 Test Data Registers Test data registers Boundary -scan register Device identification register Optional User test data registers Optional M U X Bypass register TDI Decoding logic Instruction register M U X Output buffer TDO DR clocks and controls TMS TCK T A P c o n t r o l l e r IR clocks and controls STATUS Select Enable 29

30 Test Data Registers Operation of the test data register Controller state Action Capture-DR Load data at parallel input into shift-register stage Parallel output register or latch retains last state Shift-DR Shift data towards serial output Parallel output register or latch retains state Exit1-DR Retain last state Exit2-DR Retain last state Pause-DR Retain last state Update-DR Load parallel output register or latch from shift register stage Shift register stage retains state All other Registers which have a parallel output maintain their control states last state of the output Otherwise undefined 30

31 Bypass Register Single stage shift register When selected, the shift register is set to 0 on the rising edge of TCK with TAP controller in its Capture-DR state Provide a minimum length serial path for the test data from TDI to TDO Test cycle is shortened Diagnosis time is shortened 31

32 Boundary Scan Register Series of boundary scan cells Features Allow testing of circuitry external to the IC Allow testing of the core logic Allow sampling and examination of the input and output signals without interfering the operation of the core logic Can stay idle 32

33 Boundary Scan Cells Allow testing of board interconnections Control of each output pin Observation of all pin states Boundary scan cells at Input pins Output pins Bi-directional pins Output driver enables Direction controls 33

34 Boundary Scan Cells Implementation of boundary scan cell Normal Mode When Mode Test/Normal = 0, data passes from IN to OUT Then the cell is transparent to the application logic Scan Mode Mode Shift/Load =1 and clock pulses are applied to Clock Capture Mode The data on IN can be loaded into the scan path by setting Mode Shift/Load =0 and applying one clock pulse to Clock 34

35 Boundary Scan Cells Update Mode Once the 1st FF is loaded, either by a capture or scan operation, its value can be applied to OUT by setting Mode Test/Normal=1 and applying clock pulse to Update Minimum boundary scan cell configuration for input pins Preferrable in delay sensitive circuits 35

36 Cells at 2-State Output Pins Can be set only at a high or low logic level One boundary scan cell is sufficient to observe or control the state of the pin Boundary scan cell should be designed to avoid the following problems An external block may contain asynchronous logic that will be set into undesirable states when shifting patterns appear at its input Boundary scan output signals may be fed into a clock input of the external block, which may produce hazardous effects if the logic is not shielded from the shifting patterns 36

37 Cells at 3-State Output Pins 2 boundary scan cells per pin are needed to observe and control the state of the pin Cell configuration at a 3-state output pin 37

38 Cells at 3-State Output Pins When 2 or more 3-state pins are present (e.g. connected to a bus) is is allowable to control the respective enable stages with one boundary scan cell One boundary scan cell controls several 3-state outputs 38

39 Cells at Bidirectional Pins Bidirectional pins may be either a 2-state or a 3-state pin One boundary scan cell controls several 3-state outputs Control cell may have an extra input for Reset signal 39

40 Device ID Register 32 bit shift-register, parallel-in and serial out Provide binary information about the manufacturer's name, part number and version number of IC Applications In the factory, it allows verification that the correct IC has been mounted on the proper place When IC has been replaced, the version number of the replacement can be checked, and if required the test program can be modified It may be desirable to blindly interrogate a PCB design by a controller unit in order to determine the type of each component on each board location without further functional knowledge of the design When a PCB is added to a configuration at system level, the system test program can be adjusted to the new PCB and the ICs mounted on it The correct programming of off-line programmed ICs can be checked 40

41 Device ID Register Structure of a Device ID Register If optional Device ID register is not present, Bypass register is chosen when IDCODE is executed If the first bit shifted out of the component during a test data scan is 0 it can be deduced that component has no Device ID register Device ID Design 41

42 Design Specific Register The manufacturer may add test data registers dedicated to his own design The manufacturer may decide whether he makes the instructions for the design specific register available in his component catalogue or not Otherwise he needs the design specific registers only for his own in-house testing 42

43 Instructions Mandatory BYPASS SAMPLE/PRELOAD EXTEST Optional INTEST RUNBIST IDCODE USERCODE CLAMP HIGHZ Design specific 43

44 BYPASS Every chip must have a BYPASS register which is a test data register of length 1 Provides a single bit connection through the chip data shifted through chip without affecting chip shorten path to target chip Binary code must be all 1's If the optional device ID is not present, BYPASS instruction is forced into the latches at the parallel outputs of the Instruction Register when the TAP controller is in its Test-Logic-Reset 44

45 SAMPLE/PRELOAD Used to take snapshot of normal system operation stage into the parallel instruction register Allows the data on I/O pads of a chip to be sampled Useful for debugging of prototypes in the development phase of a board design Used to load values into boundary Scan cells After power-up, the data in boundary scan registers at the output cells are not known 45

46 SAMPLE Instruction In the sampling mode, data are captured with the TAP controller in its Capture-DR state at the rising edges of TCK Subsequently these data can be shifted out in the Shift-DR state of the controller Sampled data can be scanned out while the board remains in normal operation 0 Test-Logic- Reset 0 Run-Test/Idle 1 Select-DR-Scan 0 Capture-DR 0 Shift-DR 1 0 Exit1-DR 1 Dataflow 0 Pause-DR 0 Update-DR 0 46

47 PRELOAD When the user prepares an EXTEST by shifting in beforehand the data which must be driven out from the chip's output pins into the PCB net using the TAP controller in its Update-DR state 0 Test-Logic- Reset 0 Run-Test/Idle 1 Select-DR-Scan 0 Capture-DR 0 Dataflow during PRELOAD instruction Shift-DR 1 Exit1-DR 0 1 Update-DR 0 47

48 EXTEST Used to test circuitry external to a chip, such as the board interconnect While this instruction is executed, the core logic is isolated from the I/O pins The test data is loaded beforehand into the boundary scan register stages using SAMPLE/PRELOAD The loading of test vectors is concluded by bridging the TAP controller to the Update-DR state On the falling edge of TCK the test vectors are transferred to the parallel output stage At the receiving ends of the net, the cells at the input pins capture the test result with the controller in its Capture-DR state The next step shifts out the test results from the input pin cells towards TDO 48

49 EXTEST Dataflow during EXTEST instruction During the time of execution of the EXTEST, only one system pin is driving a net at a time while the other connected output pins are kept at HIGHZ This avoids boundary scan cells at the output pins being overdriven with an unknown signal value 49

50 EXTEST Shift-DR Shift stimulus data in from TDI through the registers to the cells related with the output pins of the IC Update-DR Update these output cells and apply stimuli to the board interconnections Capture-DR Capture the status of the board's interconnections at the input pins of the receiving IC Shift-DR Shift out the results through the BSR towards TDO for examination 1 0 Test-Logic- Reset 0 Run-Test/Idle 1 Select-DR-Scan 0 Capture-DR 0 Shift-DR 1 Exit1-DR Update-DR

51 INTEST Used to apply a test vector to the application logic via the boundary scan path and to capture the response from this logic Slow speed testing Gives complete controllability and observability of the I/O pads of a chip For device containing dynamic logic such as DRAM memories, refreshment of data cells may require a much higher frequency than can be obtained with this test method Use RUNBIST 51

52 INTEST Dataflow during INTEST instruction 1 Test-Logic- Reset 0 0 Run-Test/Idle 1 Select-DR-Scan 0 Capture-DR 0 Shift-DR 1 Exit1-DR 0 1 Update-DR

53 INTEST This cycle is repeated for each test pattern INTEST instruction is loaded into instruction register Then the test data register is loaded with test data The inputs to the application logic are driven by the input boundary scan cells and output pads of the chips are output boundary scan cells The scan path is loaded while in the control state Shift-DR In the Update-DR state these data get applied to the inputs of the application logic Repeating a load-test-data register cycle, the test results are captured when in state Capture-DR After this, another test pattern can be loaded into the boundary scan path while the results are sent back to the bus master 53

54 INTEST Shift-DR Shift the data in through the registers to the cells related with the input pins of the IC Update-DR Update these input cells and apply stimuli to the core logic Capture-DR Capture the status of the core logic outputs in the output cells of the IC Shift-DR Shift out the results through the BSR of the IC for examination 54

55 RUNBIST Allows for the execution of a self test process The test is executed while TAP controller is in the Run- Test/Idle state Must select the boundary scan register to be connected between TDI and TDO All inputs to the application logic are driven by the boundary scan register during the execution of this instruction The timing constraints have been added to ensure that the tests of all components involved are completed in one test run When the self test is running, the boundary scan cells are used to hold the component's output to a fixed value The signals generated in the core logic during the self test cannot enter the PCB nets When RUNBIST is applied, the test results of all versions of a component must be the same 55

56 CLAMP Used to control the output signals of a component to a constant level by means of a boundary scan cell In such cases the Bypass Register is connected in the TDI-TDO path on the PCB This instruction is used for instance with cluster testing, where it can be necessary to apply static guarding values to those pins of a logic circuitry which are not involved in a test The required signal values are loaded together with all test vectors, both at the start of the test and each time a new test pattern is loaded Increase the test pattern and slightly reduce the overall test rate 56

57 IDCODE If a Device Identification Register is included, the IDCODE is forced into the Instruction Register's parallel output latches while the TAP controller is in its Test-Logic-Reset state This means of accesses to the Device Identification Register permits blind interrogation of components assembled onto a PCB, making it possible to determine what components are mounted on a board 57

58 USERCODE Must provided by the manufacturer if the Device Identification Register is included in a component and the component is user-programmable This instruction is only required if the programming can not be determined through the use of the test logic When selected, this instruction loads the userprogrammable identification code into the Device Identification Register at a rising edge of TCK and TAP controller in its Capture-DR state 58

59 HIGHZ Force all outputs of a component to an inactive drive state Application is found in situations where a conventional incircuit test is still required The in-circuit tester may drive signals back to the component's output pins where hazards may occur if its output impedance is not high 59

60 Boundary Scan Design Language IC PCB System Documentation BSDL(VHDL) EDIF - / Description Design Automatic - - BS inserter Design Logic Disassembly Disassembly Verification Analyzer Test ATPG for BS TPG BS TPG Preparation inserted BS logic 60

61 BSDL Boundary Scan Description Language A subset of VHDL case-insensitive free-form multi-line terminated form In a full VHDL-based system, the BSDL information is passed through the VHDL analyzer into a compiled design library, from where the boundary scan data are extracted by referencing the appropriate attributes Elements that are mandatory for are not included 61

62 Hardware Test Innovations Provisions at Board Level Concurrent Sampling Boundary Scan Master Memory Board Testing System-Level Test Support Embedded Go/No-Go Test with Boundary Scan System Backplane Test Bus On-Chip Provisions Boundary Scan on WSI Designs Boundary Scan on Multichip Modules Boundary Scan on Mos Designs Digital Bus Monitor Adjustable Scan Path Lengths Path Delay Measurements 62

63 Concurrent Sampling At predetermined instants and intervals during the continuous execution of the functional self tests, data are strobed by the BS cells at the chip s I/O pins Sample-scan cycles Features Chip I/O values of interest can be sampled safely only if the sample clock(s) can be synchronized to the board system clock(s) Usually all Boundary Scan chips receive the same copy of the sample clock Sampled signals to be compressed must not have indeterminate value because they will corrupt the compressor response If there are on a board N Boundary-Scan registers each having an assumed equal length of M, then NM bits must be stored in the onboard memory tester The mask data are stored in a NM Mask RAM(N words of M bits) A relatively small chip area is required 63

64 Concurrent Sampling Board structure TDI Core Core TDO Core MISAR Costs Compared with functional testing alone, this method improves the effectiveness of both defect detection and diagnosis To avoid explicit bit by bit monitoring of the I/O signals, the responses are compressed RAM 64

65 Boundary Scan Master(BSM) Parallel-serial protocol conversion device to provide a board-level BIST requiring minimal hardware and software development effort A dedicated bus master providing the parallel-serial interface between the board tester and the TAP is useful 65

66 Boundary Scan Master(BSM) Features Within the BSM the ATPG comprises six registers Test resource control, determining the source of the tests applied to the board units and the destination of the responses Selection of one of the four possible vector sequences that the ATPG is able to generate: pseudo-random, walking sequence(walking ones and zeros), counting sequence(up or down), constant output (ones or zeros) Control of the program counter logic Control of the vector length for each scan path Storage of the counts of the stimuli cells in the scan path Containing the signature analysis register(sar) and a pseudorandom pattern generator, both 32 bits Scan Sequence Modifier(SSM) which modifies a test sequence to ensure that no conflict will occur before it is passed to the BS chain Enhance the efficiency of ATPG and control SAR 66

67 Boundary Scan Master(BSM) Features The SSM interacts with the ATPG(generator mode) and the SAR(deterministic mode) SAR is the final destination of the TDI signals A '1' in a location of TVI identifies a control cell at the corresponding location of the BS chain A '0' in a location of TVI implies that the cell is either a stimulus (TVO is 1) or a response cell (TVO is 0) Costs Board-level BIST targeted towards automated generation of test stimuli and compressing the responses to a signature, is provided at the cost of an extra IC The BSM is capable of running a five-step test: the BSM self-test, the BS path integrity test, the board interconnect test, activating the device(ic) BIST and perform a cluster test 67

68 Memory Board Testing MCERT Chip Memory Control, Error Regulation and Test Chip 68

69 Memory Board Testing Features The control section of the chip has 17 registers The chip accepts 36 bits of data(32 data bits and 4 parity bits) and 34 bits of address (30 address bits and 4 parity bits) from a source requesting access to the memory or to the internal register The MCERT chip is designed to execute user defined memory test algorithms The march test register allow user defined test algorithms for memory marching Test features in the memory test mode A memory test may be done on selected banks of memory Tests may be stopped on the occurrence of the first memory error and restarted from the last failing location A failing location is identified by the bank that failed, the address that failed and the data bit that failed At the end of a successful memory test, all the memory locations are automatically initialized with the correct check bit values 69

70 Memory Board Testing Costs By using one VLSI chip on a board, the factory costs are significantly reduced through both less test development and test equipment costs The throughput is also greatly increased due to reduced test times The MCERT provided BIST facility is accessible by the system user as well as by the factory personnel 70

71 Embedded Go/No-Go Test Power-On-Self-Test (POST) unit Checks on failures at power-up time and resets/initializes all digital system logic The POST provides an external signal(static) to the enable/disable logic for the I/O bus in order to prevent bus conflicts To perform the tests using the embedded CPU, serialized test vectors are required An extremely simple routine can be used to shift the test vectors into the Boundary-Scan chains on the POST logic 71

72 System Backplane Test Bus Creating a system-level test ring requires that the system design includes an appropriate way to make all on-board TAP signals available to the system backplane Bringing out the TAPs of all boards to the system backplane and using a suitable multiplexing scheme that selects one or more board-level TAPs Easy to design but will a large number of wires Daisy-chaining the board TDI-TDO pins to form a system-level test ring on the backplane A huge drawback is that when the system is left with an empty slot for a board, the system test ring is broken in arbitrary positions The might be cured with some physical connections but it remains clumsy Using a dedicated chip to link the board-level TAPs and test rings to a structural test and maintenance bus on the system backplane The disadvantage of the two can be avoided 72

73 System Backplane Test Bus System testing architecture System Backplane Test Bus BT-Link Unit TMS TCK Local Test Ring Board-1 BT-Link Unit TMS TCK Local Test Ring Board-n TDI TMS TCK TDO Test and Maintenance Unit On-board System Logic 73

74 System Backplane Test Bus System testing architecture The system backplane, providing a electro-mechanical construction that holds the slots into which the printed circuit boards(pcbs) are put Each slot is numbered(1...n) and is identified by its Slot-ID The backplane test bus consists of the TDI, TMS, TCK and TDO connections The local test ring, which is the daisy-chained connection of the on-board TAPs of the ICs compliant with the The BT-Link unit, a Backplane Test Bus Link providing the interface between the local test ring(on-board logic) and the system backplane The Test and Maintenance Master (T M Master) is a control unit for the backplane test procedures 74

75 System Backplane Test Bus Costs The architecture uses a backplane test bus and a BT-Link unit Advantages It uses only one chip-to-system test access protocol (the test control design and the test software is simpler) With the optional Status Pins and Status Registers a back-door interrogation of the on-board status is possible, without invoking the on-board's test ring The system can be enhanced so that the BT-Link unit contains a module's identification, like the component's Device-ID 75

76 BST on WSI Designs With wafer probe testing, full size I/O pads and large output drivers to drive the capacitance introduced by the probes and the input circuitry of the tester are needed The driving of such buffer with its associated power consumption is not needed for inter-cell signal connections, as provided by the BS serial test interface The allows a system level test of all chips, provided that all chip TAP connections are addressed by system test bus If a chip has a very small size, then the implementation of a BS Register would result in too much overhead of wafer area 76

77 BST on Multichip Modules MCMs are modules built up of dies on top of several dielectric and metallization layers supported by a ceramic multi-layer substrate Guidelines The larger the size of an interconnect feature, the lower the probability is that a defect in it will adversely affect the circuit performance ASIC probe pad drivers contribute to the signal propagation delay due to their capacitances ICs having a typical timing spec may lead to overall timing outside the designed range if the signal paths of several ICs are put in series A die may be placed on the wrong place in a circuit To cope with the fact that not all ICs on the MCM are designed with a BS facility, at least all Module I/O pins should be connected to a BS register cell Full test of on-module memory should be provided by some onmodule logic 77

78 BST on Multichip Modules Test strategy for MCMs Test the connections to the MCM I/O pins This test is of utmost importance because the module I/O pins provide the only access to the tester Test the IEEE Std TAP and BS infra-structure integrity and the IDCODES Essential to first check, diagnose and correct these items before any other test is performed Test the chip interconnections on opens and shorts Test the on-module's bus integrity This check verifies that no opens exist at the output and/or bidirectional pins of those ICs which are bussed together Test the on-module device integrity Dies may be damaged during the module's fabrication process Therefore tests like RUNBIST and INTEST verify the functionality of the individual devices 78

79 BST on MOS design Instruction decoding All instructions are fully decoded and documented as a unique opcode TAP Controller Extra effort are required to imply circuitry for an asynchronous reset of the TAP controller Boundary-Scan Cells A design philosophy seeking for a minimum design effort leads to modular approach to the cell layout INTEST Instruction The biggest problem is to find a way that provides utility in the stimuli and responses which can be generated by the user SAMPLE/PRELOAD Instruction A typical SAMPLE problem is that there is no instant that all the pins are in a logically valid state A synchronization mechanism for the various clocks is necessary 79

80 BST on MOS design Timing skew problem There can be a timing skew in the phase difference of TCK pulses as measured at one device and at the BS cell Within the device, there is a timing skew between the system and the test logic operation Timing skew exists also in the IEEE Std Boundary-Scan logic itself 80

81 Digital Bus Monitor Potential problem regarding the speed of BS testing In order to fetch stable data from the boundary of the target IC, the scan clock(tck) should be synchronized to the rate at which data are traversing through the boundary A system clock which is used as scan clock, may be too fast for the IEEE Std TAP and the SAMPLE/PRELOAD instruction can not be executed In a typical board design not all ICs operate at the same system clock Difficult to obtain valid data from all IC boundaries with one sample operation To circumvent these problems, additional board logic could be design and implemented 81

82 Digital Bus Monitor Features First enable an IC's boundary test logic to sample system data and secondly access the result for analysis When the DBM is enabled via the serial input from the test bus, it is synchronized with the functional circuitry Then data trace and/or data compaction is performed at speed on the data flow and the trace data and/or signature collected can be accessed via the test bus for processing It supports all required BSCAN test instructions as well as dedicated instructions supporting the data trace and signature analysis test operations The latter operations can be controlled either by the test bus or by internal DBM control signals 82

83 Adjustable Scan Path Lengths A way to improve scan test efficiency is to reduce the test vector length dynamically on the places and in those circumstances where it is appropriate Partitioning a scan test data register Sufficient to only change the value in the cells of the register back-end while retaining the current values in register front-end Requires a smaller number of shift cycles than a complete scan For a set of stimulus vectors the partitioning should maximize the probability that at least one cell of the mostly addressed back-end must change while minimizing the probability that at least one cell of front-end must change 83

84 Adjustable Scan Path Lengths Algorithm to find the optimal partitioning Compute for each scan cell the number of times its value changes for a given set of stimuli Compute for each scan cell the probability that its value changes from one stimulus vector to the next Sort the cells in descending probability and renumber them from 1 to B being the number of the mostly addressed back-end cells and B+1 to T (of Total) being the numbers of remaining cells of front-end For B=1 to T-1 calculate the above described probabilities PB and PF Select the value of B which produces the smallest number of vectors Two observations The above procedure can be used to estimate the optimal B With a reduced amount of scan cells in the test path a negative impact on the fault coverage can be expected 84

85 Path Delay Measurements Static errors last permanently These errors are repeatable and can be detected independent of the operating environment Timing dependency All nodes of the circuitry may pass all desired signal transition tests but at a different speed than that specified Internal clock signals The internal clock delay, the skew and the at-speed set-up times of the various logic elements have to be considered as part of the internal path-delays Only the internal clock is a dedicated and reliable mechanism designed to enable the IC's internal logic elements (e.g. flip-flops) to operate accurately 85

86 Path Delay Measurements Path selection Use the results of timing analyses, from where a number of the longest paths can be selected and their paths can be selected and their path-delays measured Include sufficient paths in the subset in order to cover to cover all different types of primitive cells/circuit block so that errors due to the wrong characterization of these cells can be identified Select those internal paths that pass through circuit nodes that are most heavily used Double strobe flip-flop The internal flip-flops of the IC are designed so that they can be loaded with arbitrary initial values using the normal scan techniques as well as simultaneously storing a different final value in them It is possible to transfer the final value in place of the initial value under control of the regular system clock 86

87 PCB Test Testing integrity of the BSCAN chain PCB faults Test algorithm Diagnostics Cluster testing Test flow 87

88 Testing Integrity of Bscan Chain Functions need to be tested The power supply lines to the components must be correct Hard to check Additional equipment and measurements for actual faults The IC s boundary scan implementations must be correct The TCK and TMS signals must be present and be correct The TDI and TDO signals must be present and be correct If present, optional TRST must be correct The TDI-TDO connections between the boundary scan components on the board 88

89 Test Steps Reset Instruction register shift After this is successfully completed, TCK, TMS, TDI and TDO nets are connected properly Also all IRs loaded the initial capture value Identification register shift TRST connection check 89

90 PCB Production Faults Unlike in IC testing, a faulty PCB in the production stage is usually repaired Therefore board testing requires not only the fault detection but also a diagnosis of the fault A fault is said to occur when the measured signal value of a device does not conform to the expected value In order to diagnose the fault, a certain knowledge of the device under test is required Occurrence and detection of production faults Technology dependent Diagnosis becomes difficult It is not always clear which type of fault is responsible for the test pattern measured Various occurring fault considered separately 90

91 Considering Opens Opens are frequently considered as one of the single net faults which are categorized as follows Stuck-at one Stuck-at zero Stuck-open The net at an input pin is floating The number of possible combinations in a net with p nodes C(i,p) = p! / [ (p-i)! i! ] The total number of partitioning a net of p nodes into two parts is given by 2 p-1-1 In case of opens, it is sufficient when the number of test patterns equals to the number of output pins and all receiving input pins on the net are read 91

92 Considering Shorts OR-short If the driving power on the net is such that a 1 dominates AND-short If the driving power on the net is such that a 0 dominates Weak-short If the resulting logical power on the net is not known but lies between 0 and 1 Multiple-short shorts between more than 2 nets Testing for all possible shorts would require an exponentially growing number of test vectors For 2-net shorts C(2,n) = n(n-1)/2 92

93 Considering Multiple Faults Is substantial information added to the single level fault model? Is a partial multiple fault test the most economic solution? Can a subset of the total possible multiple faults after a diagnostic with an acceptable fault coverage? Multiples faults that are not diagnosed Stuck-open Wired-OR Stuck-open Wired-OR Wired-OR Stuck-open 93

94 Coming to a Model Three fault types are to be detected and diagnosed Stuck-at Stuck-open Shorts Or-shorts, AND-shorts, Weak-shorts Only those stuck-open faults are considered which isolate an output from a net Only 2-short faults need to be detected Multiple faults at one net are not considered 94

95 Test Algorithm An integrity test of boundary scan chain on a PCB should precede any boundary scan testing procedure For any separate net, one and only one driving output must be active at any time This is to avoid short conditions on the net 95

96 Binary Counting Test Sequence Only two vectors are needed to detect any short Vectors for short detection V1 V2 Net1 0 0 Net2 0 1 Net3 1 0 Net4 1 1 The vectors V can be applied in parallel Test time is determined by Ølog 2 (n)ø If the test vectors are applied through a boundary scan, test time is p Ølog 2 (n)ø where p is the number of shift operations If the all-0 and all-1 test patterns are avoided for the short test the same test vectors can be used to detect both short and stuck-at faults Ølog 2 (n+2)ø vectors are necessary and sufficient to to test a set of n nets on both type of faults 96

97 Binary Counting Test Sequence Algorithm Step1 : Assign each of the n interconnect nets a successive number, starting with 1 Step2 : Calculate the value of Ølog 2 (n+2)ø in order to find the number of patterns needed Step3 : Assign each of driving node the calculated number of bits with a bit pattern having a binary value equal to the number assigned to the net concerned Vectors for short detection of 6 connections V1 V2 V3 Net Net Net Net Net Net

98 Minimal Weight Sequence Used when no design and process information of the PCB is available The designer decides the needed number of PTVs in the binary counting sequence Then the STVs are generated such that first all STVs with only one bit with 1 are produced, next those vectors possessing two 1s etc. The value 1 represents the weight A minimum of ones are generated 98

99 Minimal Weight Sequence STVs generated in minimal weight sequence 4 bit STVs Weight Net Net Net Net Net Net Net Net Net Net Net Net

100 Walking One Sequence If there are N nets, then after N shifts of the total chain the logical 1 has walked over the all nets, one at a time The total sequence just takes N vectors It guarantees full diagnosis It works well for single fault situations and for independent co-existing of the same type Test patterns are easy to generate and test result is easily measured by a simple counter It is suited for go/no-go test but the application time is long Netlist information is needed A walking zero sequence can also be used 100

101 Diagonally Independent Sequence Example 1 X X X 0 1 X X X where X can be either 0 or 1 The row represents the STVs and the column represents the PTVs This can be used for diagnosis of all type of faults, unrestricted shorts, opens, stuck-ats, etc Aliasing and confounding test results can be eliminated with the aid of this sequence The sequence is easy to generate 101

102 Maximal Independent Set Potential weight depends on the bit positions of the highest and lowest bit with a value 1 in a STV For a non-zero vector v=(b 0,b 1 b n.b m ) where b n =b m =1, the potential weight w is given by w=m-n+1 The vector set exhibits a very regular pattern The subsets with equal potential weight are diagonally independent 102

103 Order Independent Test Sequence Consider scan chain with N cells Binary counting sequence Ølog 2 (n+2)ø vectors are required where n is the number of output cells For scan, each vector is n+2 bits and the vector is padded with N- (n+2) zeros to accommodate N bit chain length The zeros are padded in the proper order depending on the order of I/O cells Requires the structural information Instead, use Ølog 2 (N+2)ø vectors No information about PCB needed Structure or order independent Long test sequence 103

104 2 Net Shorts The detection of all 2-net shorts may not be uniquely diagnosable because a stuck-at fault may cause the same test results Test results for nets 1 and 2 shorted driving signals sensed signal vector vector vector Test results for nets 2 and 4 shorted driving signals sensed signal vector vector vector

105 Multiple Net Shorts The multiple short makes the test result of the 2-net short Test results for nets 1, 3 and 5 shorted driving sensed after repair of signals signal 3+5 shorted vector vector vector This can be solved using additional test vectors This set consists of the complements of the former vectors, which are simply generated by inverting the binary values of the first vectors Required test vectors : 2Ølog 2 (n+2)ø 105

106 Multiple Net Shorts Test vectors original complement Net Net Net Net Net Net Test results for nets 1, 3 and 5 shorted driving result if result if signals (compl.) shorted shorted vector vector vector

107 Aliasing Test Results An aliasing test results exists when the faulty response of a set of shorted nets is the same as the fault-free response of another net In this case it cannot be determined whether or not the fault-free net is involved in the short 107

108 Confouding Test Results It may happen that 2 or more independent shorts occur in a set of nets on a PCB A confounding test result may occur when the test results from the multiple independent faults are identical It cannot be determined if these faults are independent The degree of a confounding test result is defined as the maximum number of potentially independent faults that all have the same test result A full diagnosis after a one-step test procedure is only possible if neither a confounding nor an aliasing test result exists 108

109 Single Test Step Tests A set of test patterns is applied and the response is analyzed at once for fault detection and diagnosis Only a single faults in a set of nets occurs and a unique diagnosis is possible 109

110 Multiple Test Step Tests A test is applied, its response is analyzed and one or more additional tests may have to be applied for a unique sequence When aliasing (but not confounding) test results are obtained A test set can be used for self diagnosis if it is independent 110

111 Adaptive Test Algorithm An full diagnosis of all shorts is possible and no more PTVs are needed than C+Ølog 2 (n+2)ø where C is the highest possible degree of confounding in a set of n nets Step 1: Apply the Ølog 2 (n+2)ø test vectors for all fault detection Step 2: Analyze the test results. If neither aliasing nor confounding results exist, the diagnosis is complete and unique; the test is ready Step 3: If only aliasing results are detected, one more parallel test vector is required for full diagnosis Step 4: The confounding results are resolved Let C be the largest possible degree of confounding test results For C confounding results no more than C-1 tests are required to resolve the confounding causing results Since the detection of these faults can be done in parallel, C-1 tests suffice to completely detect these faults Step 5: After removal of the confounding causing faults, one or more aliasing results are still possible. One more step is needed 111

112 Applying Max-Independence Highly loaded PCB with many nets, i.e. very high C Prior technical knowledge is expected regarding the adjacent nets on the PCB as well as the empirical maximum number of expected shorts occurring in the manufacturing environment The number of parallel test vectors for full diagnosis of the shorts p = Ø E + log 2 (n+2) - log 2 E - 1 ø E is the number of bridged nets n is the number of nets Since 2<=E<=n, Ølog 2 (n+2)ø <= p <= n Suppose that on a PCB of 1000 nets a multiple short of at maximum 20 adjacent nets cover 99% of the total number of all encounter shorts in the factory (E=20) p = Ø 20 + log 2 (1000+2) - log ø =

113 Combined Faults in One Net With multiple faults on one net, usually one or more faults must be solved before full diagnosis is possible A multiple test cycle is required However if the available knowledge about the physical properties of the PCB under test is used, some constraints can be put on the occurrence of faults 113

114 Cluster Testing Circuit containing boundary scan logic and non-boundary scan login A cluster may have its inputs and outputs connected to boundary scan ICs to other circuitry or to board connectors The test stimulus for the cluster is loaded through the TDI-TDO path into the relevant BS output cells and the responses are captured in boundary input cells and shifted out for diagnosis Clusters may be subdivided into various types of cluster Memory array of clusters Single device clusters Random logic clusters Tester must know the PCB topology in order to select the meaningful test data out of the entire background data stream 114

115 Impact on Fault Detection Constraints The conventional cluster is not fully controllable through the boundary scan path The logic within the conventional cluster can possibly not be initialized and hence the cluster will behave unpredictably Test steps of mixed test technology Conventional short test Boundary scan integrity test Interactions test Boundary scan interconnect test 115

116 Conclusion Cheaper products Boundary scan lower capital investments for test equipment Boundary scan shorter test times due to a fault coverage of nearly 100% and strong diagnostics software Time-to-market is shorter Shorter development times because boundary scan implies DFT, encourages concurrent engineering and speeds up prototype debugging Faster production ramp-up because the test programs are ready in advance Improved product quality and reliability The products and the test equipment use the same boundary scan technology, which is in itself technology independent Lower product down time due to improved manufacturing methods Quicker repair at the customer s site due to a very high fault coverage and diagnostic reporting 116