A Low Power 1Mbit MRAM based based on 1T1MTJ Bit Cell Integrated with Copper Interconnects

A Low Power 1Mbit MRAM based based on 1T1MTJ Bit Cell Integrated with Copper Interconnects M. Durlam, P. Naji, A. Omair, M. DeHerrera, J. Calder, J. M. Slaughter, B. Engel, N. Rizzo, G. Grynkewich, B. Butcher, C. Tracy, K. Smith, K. Kyler, J. J. Ren, J. Molla, B. Feil, R. Williams, S. Tehrani Motorola Semiconductor Products Sector and Motorola Labs Tempe, Arizona 85284 This work supported in part by DARPA June 12, 2002 VLSI 2002 c12p4 1

Overview of MRAM Technology Attributes and operation principle 1Mb MRAM process Cu metal interconnect Magnetic Cladding 1Mb circuit Memory organization erence cell Read circuitry Outline Summary June 12, 2002 VLSI 2002 c12p4 2

MRAM Attributes MRAM offers multiple memory capabilities that are currently realized by separate memories. Non-Volatility of Flash with fast programming, no program endurance limitation, and byte programmable Density competitive with DRAM with no refresh refresh Speed competitive with SRAM (except the fastest) at fraction of the cell size Nondestructive read Immunity of bits to soft error June 12, 2002 VLSI 2002 c12p4 3

Memory Cell - 1Transistor 1Magnetic Tunnel Junction (MTJ) i Magnetic Field Flux concentrating cladding layer Inlaid Copper interconnects Digit Line Bit Line i Isolation Transistor MTJ RA (KΩ µm 2 ) 0.6x1.2µm bit at 300mV bias 11 10.5 10 9.5 9 8.5 8 7.5-10 MR=37% -7.5-5 -2.5 0 2.5 5 7.5 10 Bit Line Current (ma) MR = (R max -R min )/R min Digit Line Current 0mA 4mA June 12, 2002 VLSI 2002 c12p4 4

Tunneling Magnetoresistance MTJ Material Structure Spin Dependent Tunneling Storage layer Pinned layer } Top electrode, Bit Line Free AlOx Fixed Ru Pinned AF pinning layer State 0 E F1 Parallel - Low Resistance Pinned Barrier V Free E F2 Base electrode Digit Line State 1 Pinned Free V Isolation Transistor E F1 Antiparallel - High Resistance Barrier E F2 June 12, 2002 VLSI 2002 c12p4 5

Tunneling Magnetoresistance Across wafer uniformity - 200 mm 11.3 11.0 10.5 10.5 10.9 12.3 11.7 10.3 9.74 9.88 9.65 9.80 10.2 11.5 10.3 9.54 10.9 10.6 10.3 9.74 10.5 10.1 9.68 10.4 10.8 10.8 10.7 9.85 10.7 9.80 10.9 10.5 10.8 10.5 9.86 10.2 10.3 9.45 10.1 10.4 10.6 9.87 9.62 10.9 10.2 9.52 9.43 9.56 9.59 10.2 11.2 10.2 10.4 11.0 RA=10.4 kω-µm 2, σ=6% 43.9 44.5 44.6 44.8 44.5 43.1 44.4 45.0 45.2 46.0 45.8 46.0 44.6 43.1 44.1 45.4 42.9 45.6 45.6 45.8 44.5 44.5 46.1 44.3 45.1 45.5 45.8 46.0 45.0 44.5 45.8 43.4 45.4 45.9 45.7 45.9 44.7 44.2 45.3 45.7 45.5 43.9 45.8 45.4 44.0 44.1 45.3 45.9 45.6 45.0 44.7 43.4 44.0 44.8 44.1 MR=45%, σ=2% June 12, 2002 VLSI 2002 c12p4 6

Process Flow 1st MRAM Module Flow 2nd MRAM Module Flow Digit Line Pattern inlaid copper program lines with permeable cladding. Deposit ILD, form via connection to bottom electrode, deposit, and and pattern MTJ stack. 3rd MRAM Module Flow 4th Bit Line Deposit ILD, pattern via for connection to top electrode Pattern inlaid copper program line with permeable cladding. June 12, 2002 VLSI 2002 c12p4 7

Field Enhancement from Magnetic Cladding Magnetic film surrounding conductor doubles field H for a given current I. H tot + + + + M I I Unclad Line I I H unclad 2w H clad I w I Clad Line Cladding concentrates field to top of digit line June 12, 2002 VLSI 2002 c12p4 8

Field enhancement from cladding Calculated field vs. distance above above cladded and uncladded lines 50 30 H (Oe) 20 With cladding 0 0 0.1 0.2 0.3 0.4 Distance above line (µm) cladding 40 15 10 Without cladding (ma) I June 12, 2002 VLSI 2002 c12p4 9 bitline 20 10 Astroid curve from CMOS array 5 0 Uncladded bit line Cladded bit line 0 2 4 6 8 I digit line (ma) Factor of 2 field enhancement calculated and observed

1Mb MRAM Architecture GL0 DL0 Current/Source or Sink Current/Source or Sink Row Pre- Sink Sink 16 Decode 16 Current Switch Current Switch BL 0-511 BL 511-0 0 0 DL0 GL0 Ground Switch Current Sink MRAM Array 512 columns 1024 Rows 16. Columns Digit Line Row Select t MRAM Array 512 columns 1024 Rows 16. Columns Current Sink Ground Switch GL511 DL1023 1023 1023 DL1023 GL511 Column Select Column Select 32 Current Conveyors 16 Comparators 16 Regenerators} 16 Current/Source or Sink Sink 16 dq0 Read Circuit dq15 Current Source A 16 Current/Source or Sink Sink 16 Read Circuit dq15 dq0 June 12, 2002 VLSI 2002 c12p4 10

Array Architecture Left Bank 512K bits Right Bank 512K bits 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k 32k D0 D1 1 D2 D3 3 D4 D5 5 D6 D7 7 D8 D9 9 D10 D12 D14 D11 D13 D15 D15 D13 D11 D9 D14 D12 D10 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 June 12, 2002 VLSI 2002 c12p4 11

MRAM 32Kb Memory Segment with erence Generator ½ Memory block - 1024X16 erence Generator ½ Memory block - 1024X16 BL0 BL1 BL14 BL15 BL16 BL17 BL30 BL31 Current Conveyors and Differential Amp June 12, 2002 VLSI 2002 c12p4 12

MRAM 32Kb Memory Segment with erence Generator ½ Memory block - 1024X16 erence Generator ½ Memory block - 1024X16 BL0 BL1 BL14 BL15 BL16 BL17 BL30 BL31 Current Conveyors and Differential Amp June 12, 2002 VLSI 2002 c12p4 13

Bit Line Rmax Rmin erence Generator Digit Line Common Source Word Line R = ½(R max +R min ) Digit Line Rmax Rmin erence cell-series/parallel combination of MTJ devices generating mid resistance between the two memory states June 12, 2002 VLSI 2002 c12p4 14

erence Performance Cell Resistance KΩ 14 13 12 11 10 9 8 7 6 R high Mid Point R low Operating Region -0.5-0.4-0.3-0.2-0.1 0 0.1 0.2 0.3 0.4 0.5 Cell Bias Voltage V Frequency 200 150 100 50 0 R low 1kb array Mid Point R high 16 18 20 22 24 26 Sense Current (µa) June 12, 2002 VLSI 2002 c12p4 15

1Mb MRAM Read Circuit Vbias Vref + - + - + - + - I data Current Conveyor VO Two Stage Comparator r VP VM Regenerator r q I dataref Current Conveyor VOref Vbias Vref Two Differential Current Conveyor June 12, 2002 VLSI 2002 c12p4 16

Differential Current Conveyor MTJ target MPG XO XO Vbias - A1 + Column n select select - A1 + Vbias Vref - A2 + Current Conveyor + - Vout - A2 + Current Conveyor Vref June 12, 2002 VLSI 2002 c12p4 17

1Mb Measured Access Time 1.00V/div Output Enable e 50ns Data Out 1 <15ns 1 0 0 20ns/div June 12, 2002 VLSI 2002 c12p4 18

Shmoo Plot of Valid Data out vs. Vdd Valid Data Out X <50ns @ 3V Vdd (3V +/-10%) June 12, 2002 VLSI 2002 c12p4 19

1Mb MRAM Clk Gen Prog. Sources Prog. Sources 512K Core Bitline Select Prog. Sources Current Conveyor Comparator I/O Buffer Digit Line Row Select DL Curr Source. Blk 512K Core Bitline Select Prog. Sources Current Conveyor Comparator I/O Buffer June 12, 2002 VLSI 2002 c12p4 20

1M MRAM Specification CMOS Technology 0.6µm Five Metal Double Poly (used as linear resistor) Memory Organization 16K X 16 Cell Size 7.1 µm 2 1M Die Size 4.25mm X 5.89mm Array Efficiency >60% Supply Voltage 2.7V to 3.3V Access Time 50ns Cycle Time 50ns June 12, 2002 VLSI 2002 c12p4 21

Summary Demonstrated 1Mb MRAM with 50ns read and program access time Integrated MRAM with Cu metal interconnect Cladding of metal layers reduced the power power for programming by factor of four New reference generator was demonstrated demonstrated for robust operation Demonstrated MRAM material uniformity on on 200mm substrate June 12, 2002 VLSI 2002 c12p4 22