Information Storage and Spintronics 10

Transcription

1 Information Storage and Spintronics 10 Atsufumi Hirohata Department of Electronic Engineering 09:00 Tuesday, 30/October/2018 (J/Q 004) Quick Review over the Last Lecture Flash memory : NAND-flash writing operation : NOR-type ü 1 byte high-speed read-out Low writing speed Difficult to integrate NAND-type No 1 byte high-speed read-out ü High writing speed ü Ideal for integration Flash erase for a unit block ( 1 ~ 10 kbyte ) only! NAND-flash erasing operation : *

2 10 Dynamic Random Access Memory Memory cell Architecture Data storage Read-out Refresh Further integration Flash Memory vs DRAM Comparisons between flash memory and DRAM : Flash memory Data volatility Writing operation Principles Tunnel barrier Transistor On Condenser Floating gate Transistor Electron charges are stored in the condenser. Electrons are stored at the floating gate. Leakage from the condenser. Electrons cannot tunnel through the On barriers. *

3 Storage and Working Memories Current major memories for storage and work : * Dynamic Random Access Memory (DRAM) In a computer, data is transferred from a HDD to a Dynamic Random Access Memory : Data stored in a capacitor. Electric charge needs to be refreshed. DRAM requires large power consumption. *

4 DRAM Packages DRAM design : DRAM packages : Dual in-line package (DIP) Single in-line pin package (SIPP) Single in-line memory module (SIMM) 30-pin SIMM 72-pin Dual in-line memory module (DIMM) 168-pin Double data rate (DDR) DIMM 184-pin * Memory Cell Development DRAM memory cells : *

5 Memory Storage 1 DRAM cell consists of 1 capacitor + 1 switching FET (1C1T) : 1 -state : 1 V Floating capacitor 0 V OFF 2 V Capacitor 0 -state : 1 V 0 V OFF 0 V * Memory Read-Out Read-out operation of 1C1T : 1 -data : 1 V + ΔV = 2 V Word line (3.6 V) 3.6 V ON 2 V = 1 V + ΔV Data rewrite 0 -data : 1 V ΔV = 0 V 3.6 V ON 0 V = 1 V ΔV * **

6 Memory Refresh Refresh operation of 1C1T : * DRAM Architecture DRAM architecture :: *

7 Data Access Speed Addressing a cell : Raw address strobe (RAS) Column address strobe (CAS) Page mode enables to address different columns in the same raw. Fast page mode Access time 60 ~ 80 ns Cycle time 40 ~ 50 ns Raw 1 Col. 1 Col. 2 Col. 3 Data1 Data2 Data3 Extended data out (EDO) Synchronous DRAM PC-100 : 100 MHz cycles Access time 50 ~ 70 ns Cycle time 20 ~ 30 ns Raw 1 Col. 1 Col. 2 Col. 3 Col. 4 Data1 Data2 Data3 * SDRAM access diagram : Synchronous DRAM (SDRAM) *

8 DRAM Trends DRAM follows Moore s law (160 % / yr.) : * DRAM Design Developments Storage node shapes : *

9 Fin-Type DRAM Designs Various manufacturers developed different designs : * Cells, Pages and Blocks Typical 10Gbit DRAM with high-k materials : *

10 For Higher Recording Density... Conventional DRAM cell : Next-generation DRAM cell : Word line Word line Bit line Bit line Capacitor 1-cell size Capacitor 1-cell size Capacitor Source Insulator for gating Channel Drain Word line Bit line * DRAM Market Market dominated by 3 major manufacturers : *

11 Super Pillar Transistor (SPT) Universal transistor architecture for various memories : * Memory Types Rewritable Volatile Dynamic DRAM Static SRAM Non-volatile Static MRAM FeRAM PRAM Read only Non-volatile Static PROM Mask ROM Read majority (Writable) Non-volatile Static Flash EPROM *

12 Major Memories *