Test and Measurement Challenges for 3D IC Development R. Robertazzi IBM Research
PFA Bill Price. Pete Sorce. John Ott. David Abraham. Pavan Samudrala Digital Test Kevin Stawaisz. TEL P12 Prober Glen Lansman, TEL USA. Probing Jerry Broz Acknowledgements Page 2
Outline Motivation For 3D Integration 3D Technology 3D Test in a Research Environment Instrumentation Supporting Test at Different Stages in The Build Probing Challenges Probe Over Active for KGD Screen Diced Chip Test Conclusions Page 3
Moore s Law 3D 2D 3D Historically, IC performance improvements have depended on scaling planar device structures. 1900 1910 1920 1930 1940 1950 1960 1970 1980 1990 2000 2010 2020 Page 4
Why 3D? Scaling of transistors and other circuit elements is becoming more difficult. Approaching fundamental physical limitations on device size. Interconnect latency is beginning to limit IC performance. Vertical connections allow shorter connections (50 m vs. 10 mm). Expansion of numbers of interconnects through compact vertical connections. Easier to include disparate technologies. Logic, EDRAM, opto electronics, nonsilicon based! Page 5
Challenges For 3D Integrated Circuits Design Timing analysis, clocking. DFT. Process Functionality / yield at single stratum. Characterization of 3D building blocks (TSV, bonding process). Test Definition of test points: Where and what to set, KGD strategy. How to test, probing. Page 6
3D Technology Test Site Stacked Chip Nomenclature S P S N Std Pitch TSV Std. C4 Thin S 0 Face to back stacking scheme. Cu TSV on small pitch, C4 inter strata interconnect. Package pitch Std C4 for package interconnect and final SP layer probing. C4 Small Page 7
Test Site Probing Reticule Area Array Probe Image Design A Design B Design C Design A, pad cage macros, cantilever probes. Design B, C, area array probe set, need to support KGD for base and upper level die, parametric content on both designs. Design B & C images interleaved. Common package used for space transformer. Test set up changed by changing probe head. Page 8
3D Process Characterization TSV Failure Modes -C4 Failure Modes Open TSV Bridge Fault Leaky TSV Resistive -C4 3D process characterization requires measuring resistances from 1m Y 1G (>12 orders of magnitude). True 4 point SMUs will be required to cover the low impedance range. Page 9
Interfacing To The Probe Card Cable to board signal modules Clock / 3 GHz Ports Parametric Agilent 34980A interface for 2&4 point resistance measurements, leakage. Modular Probe Interface High Speed Parametric Std I/O Page 10
Test Points During Build (Probe Options & Risk Assessment ) Build Level VLSI Technology DUT S P (Thick) S P (Thin) S N Assembled, pre-packaged Assembled, packaged Cantilever probes Pointed vertical, probe over active Flat vertical, chip tray No loss of yield observed PFA in progress Assumed OK Page 11
Single Stratum Probing Options Single stratum test required: Design verification. Known good die (KGD) prior to 3D stacking. Current injection over full area of the chip for cache. Major issues for area array probing for single layer: No qualified probe technology for fine pitch uc4 probing. Drives choice to area array probe card, pointed probes contacting Al TD landing pads. Areas of concern: Pad placement, where to probe. Damage introduced through probing process. Option #1 C4 Cluster Probing, Flat Probes Option #2 Power Grid Probe Pad Al Pad Probing, Pointed Probes Page 12
Probing / Damage Experiments: Test Vehicle Top level film stacks similar to 3D test chips. Area array probe card used with 4/9 image. ~ 100 Power/ground contacts measured in parallel for leakage. ~ 40 signal contacts measured individually. ~ 100 sites probed/die. Contactor 5 mil Palinaey 7 probe. Probe tip diameter 10 m Overdrive 0 160 m (0 6.5 mils). Electrical leakage and SEM cross sections evaluated after probing. Probe Image Electrical Set Up PG Set Signal Set Test Vehicle Page 13
Probing / Damage Experiments: Test Vehicle Top Layer Dielectric Investigations Maximum Power / Ground Leakage (A) 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 Dielectric "A" 100 Sites ~10,000 Touchdowns 1 Volt First Fail 1000 Å "A" Cu P/G Pins, Leakage Au Reference Plate S/G Pins, Punch Thru 0 1E-12-80 -60-40 -20 0 20 40 60 80 100 120 140 160 180 Overdrive From 50% Contact Point ( m) 40 35 30 25 20 15 10 5 Maximum Number of Signal Pins Making Contact Maximum Power / Ground Leakage (A) 1E-6 20 1E-7 1E-8 P/G Pins, Leakage 15 1E-9 Au Reference Plate S/G Pins, Punch Thru 10 1E-10 5 1E-11 1E-12 0-80 -60-40 -20 0 20 40 60 80 100 120 140 160 180 Stack A dielectric fails at first probe contact. Stack A + B dielectric fails after 120 m 170 m overdrive. 1 0.1 0.01 1E-3 1E-4 1E-5 Dielectric "A" + "B" 100 Sites ~10,000 Touchdowns 1 Volt 2000 Å "B" 1000 Å "A" Cu Overdrive From 50% Contact Point ( m) First Fail Page 14 40 35 30 25 Maximum Number of Signal Pins Making Contact
Probe Scratch Test Dielectric A Dielectric A + B Dielectric A + B + C Stack A dielectric fails with minimal probe scrub. Stack A + B fails at moderate probe force. Stack A + B + C shows no visual signs of failure, even with application of high probe force. Page 15
Maximum Power Ground Leakage (A) Probing / Damage Experiments: Test Vehicle 1 0.1 0.01 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 Electrical Leakage Dielectric "A"+"B"+"C" 100 Sites ~10,000 Touchdowns 1 Volt 0 1E-12-80 -60-40 -20 0 20 40 60 80 100 120 140 160 180 Full Pad Stack Bare or Al Pad 6500 Å "C" 2000 Å "B" 1000 Å "A" Cu P/G Pins, Leakage Au Reference Plate S/G Pins, Punch Thru All Pass Overdrive From 50% Contact Point ( m) Film Stack Damage Assessment Experiments done with and without Al pad layer. No fails observed for 10,000 probe/pad touchdowns. No observations of cracking from cross sections*. 40 35 30 25 20 15 10 5 Number of Signal Pins Making Contact *N. B. J. Yorita, SWT 2004! Page 16
3D Test Site Probe Pads Al Pad S P, S N Via 130 S P Probing Area 90 Al Cu Dielectric S n : No C4 on probe pad, full pad available for probing. S p :Std. C4 on each probe pad, probing zone offset from contact via / C4 attachment zone. 3 mil probes. S 0 Pad S P Pad Page 17
Top Down SEM on Pads 1. Al Probe Mark 2. Cu Sequential etch of top pad metallization. 1. Al/Cu/Dielectric. 2. Cu/Dielectric. 3. Adhesion Layer/Dielectric. Top down SEM reveals some disturbance of interfacial region. 3. Interface Page 18
AFM On Probe Marks = 31 nm AFM reveals 30 nm depression in top adhesion layer. Page 19
TEM Cross Sections on Probed Pads 3 m Interface Layer Insulator Stack Pad 200 nm No evidence of damage or crack propagation in top insulating layer stack. Page 20
Screen Yield, Design B, Using Probe Over Active S0 wafer SOC3 4 F 3 F 2 F 1 F 0-1 -2 F -3-4 -5 0 5 10 8.9 7.8 6.69 5.6 4.5 3.4 2.3 1.2 0.1-1 IDDQ (A) Wafer screen data shows no increased yield fallout over standard C4 probing using pointed probe over active probing strategy. Page 21
Diced Chip Test In the research environment, we employed a chip to chip bonding strategy for 3D IC assembly. Supporting single die test of complex area array chips has always been problematic: Vision systems in advanced probers not designed to work with single die efficiently. Chip transfer to chuck requires attachment to handler wafer, with adhesive. 3D chip bonding process development greatly benefits from pre packaged test: Does the chip work, is it worth packaging? Does the packaging process affect chip yield? What does the chip look like visually after test? S 0 Double Layer, 3D Chip S p Page 22
Diced Chip Tray TEL custom build chip tray for diced chip designs B & C. Clean, vacuum hold down technology which works with standard Table Load P12 wafer transfer procedure. Two piece design allows easily changing to another chip size, requires only replacing top guide. Alignment marks included for automated load, alignment and wafer scan. Chip Tray Design B Page 23
Chip Tray Thermal Resistance 40 38 Tray Chip Temperature ( o C) 36 34 32 30 28 26 24 R T (Tray) = 2.6 o C/W R T (Chuck) = 0.56 o C/W T Chuck = 25 o C 0 2 4 6 8 10 12 14 16 Chip Power (W) Chuck Thermal resistance (R T ) measurements for chips in tray show resistance R T ~4.6 x higher than measured with full wafer in contact with a Cu chuck. For VLSI designs B & C, no problem encountered in running low speed functional screen tests, or performance tests for brief periods. Page 24
Conclusions 3D introduces a number of new challenges in chip test, probing in particular. A hierarchical test strategy has proven essential in 3D bonding process development learning. Accessibility of test at all points in the build. Access to on board parametrics. Ability to test diced, bonded chips, pre packaged. Fine pitch vertical probe/prober technology required to support current and future 3D fabrication technologies. Page 25