Package level Interconnect Options

Transcription

1 Package level Interconnect Options J.Balachandran,S.Brebels,G.Carchon, W.De Raedt, B.Nauwelaers,E.Beyne imec 2005 SLIP 2005 April 2 3 Sanfrancisco,USA

2 Challenges in Nanometer Era Integration capacity F (GHz) F Integration capacity ~ billion transistors Operating frequencies ~ µwave (GHz) Communication bottleneck Interconnect delay far exceeds scaled transistor delay Latency spanning multiple clock cycles Power consumption 2

3 Computer architecture is all about Interconnect - Prof. William J. Dally, (Stanford HPCA Panel February 4, 2002 imec 2005

4 Breaking the Interconnect bottleneck Clustering GALS/NoC Wired CDMA Dimensions of interconnect solutions Repeaters Differential signaling Equalization Architecture Circuit Design Technology Cu/Low-K X-routing / 3D integration Optical Reverse scaling 4

5 Outline (Interconnect) Challenges in Nanometer Era Review of contemporary solutions Interconnect Scaling & Motivation for Packaging Approach WLP Technology Performance Comparison Applications Conclusion 5

6 Reverse Scaling to Resolve Global Interconnect Challenge Scaling W L Performance channel ++ W channel L Reverse scale -- 6

7 Scaling decreases the repeater-less Communication radius 7

8 Scaling Trend: Interconnect Sizing vs. Repeater insertion Low Performance High 8

9 Metal Interconnect Signal Propagation Characteristics Attenuation, Delay (Norm) Attn. RC regime delay LC regime Fn Delay normalized to near speed of light delay Fn frequency normalized as 6.28 f ( L / R) Speed of light propagation within tolerable attenuation levels 9

10 RC vs. LC Characteristics Attribute RC Lines LC Lines Signal propagation Diffusion slow Near speed of light transmission (Limited only by dielectric constant of the ILD) Dispersion High Low Attenuation High Low Delay with length Repeaters Quadratic Required (depending on distance) Linear Not required Return path Not significant Significant Pulse response Poor Good Type On-chip interconnects Off-chip interconnects 10

11 LC lines offer superior pulse response 90ps L = 5mm Vin LC line (5µ width WLP line) 1 V RC line (130nm global line) 1 Spice simulation from measured S-parameters 11

12 LC regime occurs for XSectional Area > 1um 2 Technology node LC Regime Results from spice simulation 130nm BPTM model for driver 12

13 Wiring sizing outperform Repeater Insertion Diminishing returns with repeaters for increasing wire x-section Below red line wire sizing outperforms repeaters 13

14 Wide Gap in the interconnect Hierarchy Technology node PCB Semi-global Local Global Interconnect gap Adv. PCB On-chip Fat wires on-chip? Cross sectional Area - µm 2 Technologically challenging Signal integrity Cost 14

15 Bridging the Interconnect gap with Wafer Level Packaging Technology node PCB Global Semi-global Local On-chip WLP MCM Adv. PCB Cross sectional Area - µm 2 Fat wires on-chip? Technologically challenging Signal integrity Cost 15

16 WLP Concept 130nm test chip WLP BEOL FEOL WLP wiring layers are post processed on top of active wafer Modular approach to wire stacking Thick low-k ILD with larger metal cross section 16

17 WLP enables higher wiring density than conventional packages Conventional Package wiring WLP wiring WLP uses vias for inter layer connection Package wiring layers form a part of chip 17

18 WLP Technology in our Test chips 2 user routable layers Cu metals and low-k BCB dielectric (ε r = 2.65) Two process configurations Config1 6 masks, IMPS T-lines Config2 8 masks, Ta decoupling capacitors, Microstrip T-lines 18

19 Outline (Interconnect) Challenges in Nanometer Era Review of contemporary solutions Interconnect Scaling & Motivation for Packaging Approach WLP Technology Performance Comparison Applications Conclusion 19

20 Bandwidth (BW) Metrics for Package-BEOL Comparison No. of bits transmitted per second per wire BW density BW across unit routing area Measure of wiring density Latency Delay with respect to clock period Power 20

21 3-7x BW improvement possible with Packaging Approach FF FF T b BW RC = T s01 1 Tp + 2 BW LC η η( T + T ) = 1 s01 p T s01 T s10 η 1 - signal integrity factor T p Line length = 5mm η = 1.3 WLP T-line On-chip global line Package Bandwidth is limited by register setup and hold times 21

22 Package Level Interconnects Enable Single Cycle Communication LT = D * int F clk LT = latency D int = interconnect delay F clk = Clock frequency specified by ITRS Line length = 10mm On-chip global line Package T-line 22

23 Significant Power savings with Package level Interconnects For comparing power, Capacitance ratio is derived as C C chip global pkg T line = 1.75* Zo * C ε C o r + t i onchip R C t Zo = characteristic impedance of transmission line Ci-on chip =On-chip global interconnect capacitance Rt,Ct minimum sized driver output resistance and input capacitance Power saving Per bit Zo = 75Ω 23

24 Bandwidth density is lowered in Package level Interconnects BW BD = = W + S BW P On-chip global line Line length = 5mm WLP T-line 24

25 Outline (Interconnect) Challenges in Nanometer Era Review of contemporary solutions Interconnect Scaling & Motivation for Packaging Approach WLP Technology Performance Comparison Applications Conclusion 25

26 Interconnect Options: Memory buses Off-chip BW is limited strong trend for more on-chip memories Memories occupies significant die area Micrograph of a leading Processor Source: ISSC 2002 WLP interconnects allow low latency memory accesses spread across the die Repeater less communication enables routing over hard macro blocks Can be routed over sensitive analogue blocks Flexible floor planning Low power 26

27 Interconnect Options: Inter Tile Communication Exploit LC Transmission line properties of WLP interconnects NOC or Bus? 27

28 Interconnect Options: Clock distribution First few levels of clock trees can be in WLP Inherent low rise time as compared to on-chip lines Low latency -> relaxed skew tolerance Low power 28

29 Interconnect Options: Power distribution DC Current and Voltage requirements for ITRS Technology nodes At 40nm node, to have 10% IR drop tolerance, Total wire Resistance should be less than 0.2milliohms! Package planes and lines can be used for power distribution 29

30 Conclusion Global interconnect delay and power delivery issues dominate nano- CMOS designs Reverse scaling enabled by WLP Packaging approach is promising : Extends on-chip Wiring hierarchy High low power and latencies Simultaneously address signal and power distribution However limited wiring density Options Memory buses, Intertile Communication, Clock and Power distribution 30

31 Thank you Acknowledgements: Scott List, Maarten Kuijk,Franky Cathoor, Philip Christie,Mandeep Bamal 31