DRC and LVS checks using Cadence Virtuoso Version 3.0

Similar documents
DRC and LVS checks using Cadence Virtuoso Version 2.0

Virtuoso Layout Editor

Virtuoso Schematic Composer

Design rule illustrations for the AMI C5N process can be found at:

Creating Verilog Tutorial Netlist Release Date: 01/13/2005(Version 2)

HOMEWORK 9 CMPEN 411 Due: 4/12/ :30pm

EE115C Digital Electronic Circuits. Tutorial 4: Schematic-driven Layout (Virtuoso XL)

EE434 ASIC & Digital Systems. From Layout to SPICE Simulation (Virtuoso, Calibre, HSpice) Spring 2017 Dae Hyun Kim

Lab 2. Standard Cell layout.

CMOS VLSI Design Lab 4: Full Chip Assembly

Tutorial II: Cadence Virtuoso ECE6133: Physical Design Automation of VLSI Systems Georgia Institute of Technology Prof.

VLSI Lab Tutorial 3. Virtuoso Layout Editing Introduction

The following is a procedure for extracting a layout, doing a layout vs. schematic check, and then simulating the extracted layout with Cadence.

Verifying the Multiplexer Layout

CADENCE SETUP. ECE4430-Analog IC Design

TUTORIAL II ECE 555 / 755 Updated on September 11 th 2006 CADENCE LAYOUT AND PARASITIC EXTRACTION

ANALOG MICROELECTRONICS ( A)

Lab 4 LVS and Post layout Simulation

EE 330 Laboratory 3 Layout, DRC, and LVS Fall 2015

ELEC451 Integrated Circuit Engineering Using Cadence's Virtuoso Layout Editing Tool

VLSI Lab Tutorial 1. Cadence Virtuoso Schematic Composer Introduction

EE 330 Laboratory Experiment Number 11

EDA-BASED DESIGN PRACTICAL LABORATORY SESSION No. 3

More information can be found in the Cadence manuals Virtuoso Layout Editor User Guide and Cadence Hierarchy Editor User Guide.

UNIVERSITY OF WATERLOO

Cadence Schematic Tutorial. EEE5320/EEE4306 Fall 2015 University of Florida ECE

EECE 285 VLSI Design. Cadence Tutorial EECE 285 VLSI. By: Kevin Dick Co-author: Jeff Kauppila Co-author: Dr. Arthur Witulski

Revision Notes: July2004 Generate tutorial for single transistor analysis. Based on existing schematic entry tutorial developed for ECE410

Synopsys Custom Designer Tutorial for a chip integra7on using the University of Utah Standard Cell Libraries In ON Semiconductor 0.

EE 330 Laboratory 3 Layout, DRC, and LVS

Amplifier Simulation Tutorial. Design Kit: Cadence 0.18μm CMOS PDK (gpdk180) (Cadence Version 6.1.5)

HOMEWORK 10 CMPEN 411 Due: 4/28/ :30pm

Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Andrew Mason and the AMSaC lab group.

Cadence Tutorial C: Simulating DC and Timing Characteristics 1

Cadence Tutorial 2: Layout, DRC/LVS and Circuit Simulation with Extracted Parasitics

Cadence IC Design Manual

ESE 570 Cadence Lab Assignment 2: Introduction to Spectre, Manual Layout Drawing and Post Layout Simulation (PLS)

CPE/EE 427, CPE 527, VLSI Design I: Tutorial #2, Schematic Capture, DC Analysis, Transient Analysis (Inverter, NAND2)

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Lab #2: Layout and Simulation

Fall 2008: EE5323 VLSI Design I using Cadence

DOWNLOAD PDF CADENCE WAVEFORM CALCULATOR USER GUIDE

EECS 627, Lab Assignment 3

Place & Route: Using Silicon Ensemble

Abstract Editor (Last updated: Oct. 23, 2008)

Laboratory 6. - Using Encounter for Automatic Place and Route. By Mulong Li, 2013

CS 4120 Hardware Description Languages and Synthesis Homework 6: Introduction to Cadence Silicon Ensemble

Creating LEF File. Abstract Generation: Creating LEF Tutorial File Release Date: 01/13/2004. Export GDS:

Professor Muller Fall 2016 Sameet Ramakrishnan Eric Chang Adapted from prior EE140 and EE141 labs. EE 140/240A Lab 0 Full IC Design Flow

ELEC 301 Lab 2: Cadence Basic

CS755 CAD TOOL TUTORIAL

CPE/EE 427, CPE 527, VLSI Design I: Tutorial #1, Full Custom VLSI (inverter layout)

ASIC Physical Design Top-Level Chip Layout

Cadence Virtuoso Schematic Design and Circuit Simulation Tutorial

Microelectronica. Full-Custom Design with Cadence Tutorial

EEC 116 Fall 2011 Lab #1 Cadence Schematic Capture and Layout Tutorial

Setting up the IBM 65nm libraries in Cadence 6.1

CS/EE 5720/6720 Analog IC Design Tutorial for Schematic Design and Analysis using Spectre

Tutorial for Cadence SOC Encounter Place & Route

Guide to the CSE 577 Lab and Cad tools

EE 330 Laboratory Experiment Number 11 Design and Simulation of Digital Circuits using Hardware Description Languages

EE 330 Spring 2018 Laboratory 2: Basic Boolean Circuits

EE4111 Advanced Analog Electronics Design. Spring 2009 Experiment #4 April 6 ~ April 17

EE5323/5324 VLSI Design I/II using Cadence

Prepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia Institute of Technology

Tutorial 2 Automatic Placement & Routing

Virtuoso Schematic Composer VHDL Interface. VHDL In for Design Framework II:

The original document link is

Cadence Tutorial D: Using Design Variables and Parametric Analysis Document Contents Introduction Using Design Variables Apply Apply

EE 330 Laboratory Experiment Number 11 Design, Simulation and Layout of Digital Circuits using Hardware Description Languages

ECE471/571 Energy Ecient VLSI Design

Simulation with Verilog-XL

CMOS VLSI Design Lab 3: Controller Design and Verification

FACULTY OF ENGINEERING MULTIMEDIA UNIVERSITY LAB SHEET DIGITAL INTEGRATED CIRCUIT

Layout and Layout Verification. of an Inverter Circuit

EE 140/240A - Full IC Design Flow Tutorial

Another view of the standard cells called the abstract view needs to generated

This is a brief tutorial about building a Symbol for a Schematic in Cadence IC design tool environment for hierarchical design of schematics.

Experiment 0: Introduction to Cadence

Tutorial I: Cadence Innovus ECE6133: Physical Design Automation of VLSI Systems Georgia Institute of Technology Prof. Sung Kyu Lim

CMOS VLSI Design Lab 3: Controller Design and Verification

CMOS VLSI Design Lab 3: Controller Design and Verification

Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group.

RC Extraction. of an Inverter Circuit

Cadence SOC Encounter Tutorial for a logic block using the University Of Utah Standard cell Libraries In ON Semiconductor 0.

Orcad Layout Plus Tutorial

EE115C Digital Electronic Circuits. Tutorial 2: Hierarchical Schematic and Simulation

How to Start with Cadence ECE721 Project. Instructor: Prof. Steve Bibyk Prepared by: Golsa Ghiaasi Hafezi Spring 2005 Ohio State University

Analog IC Schematic Capture. Mentor Graphics 2006

Select the technology library: NCSU_TechLib_ami06, then press OK.

Cadence Tutorial. Introduction to Cadence 0.18um, Implementation and Simulation of an inverter. A. Moradi, A. Miled et M. Sawan

Using Cadence Virtuoso, a UNIX based OrCAD PSpice like program, Remotely on a Windows Machine

CMOS Design Lab Manual

Tutorial for Encounter

Laboratory 3. EE 342 (VLSI Circuit Design) - Using Spectre netlist and Calculator for simulation

The Procedure for Laying out the inverter in TSMC s 0.35 micron Technogy using MOSIS SCMOS SCN4M_SUBM design rules.

Instruction on padframe

Introduction to CCV and Cadence Virtuoso for Electronic Circuit Simulation

ECE425: Introduction to VLSI System Design Machine Problem 3 Due: 11:59pm Friday, Dec. 15 th 2017

Procedure for PCBoard Layout

Logic synthesis and Place and Route Tutorial Page 1

Transcription:

DRC and LVS checks using Cadence Virtuoso Version 3.0

Start virtuoso l l Open a virtuoso session in the directory which contains the required cds.lib and lib.def files. Command : virtuoso &

Open the layout corresponding to your design(final_chip) in layout XL by right clicking on the layout and selecting open with. Change the application to layout XL. This will open the schematic as well as the layout. For DRC check go to verify -> DRC. Specify the rules file and uncheck the Rules library. Result will be displayed in the virtuoso command window

Make sure that the total errors are zero. If errors are found fix the errors before proceeding to the next steps. You can use the errors displayed in the command window to debug or also use the following to zoom into the errors locations : verify->markers->find. Select zoom to markers and then cycle through the different errors by hitting Next. Uncheck the warnings to display only the errors during this process.

Extracting the design for LVS check: Go to verify-> extract Specify the rules file and uncheck the rules library. The results will be displayed in the command window. A successful extraction(total errors = 0) will generate a extracted cell view. Verify this using the library manager.

LVS check: LVS will compare the extracted and the schematic views. Go to verify->lvs. Select Form contents and click ok if a Artist LVS form contents Form contents Different window pops up. Specify the schematic and extracted views for your design. Specify the rules file and Hit run.

Make sure that the design passes LVS. The previous slide shows the output generated when the design passes LVS. IF the netlists don't match use the following resources to correct your layout or schematic: -> click on output in the Artist LVS window to get the report that will show the errors in more detail. -> You can also use the info button in the Artist LVS window to get a more detailed view of the errors for schematic or layout separately.

-> You can also use the Error Display button in the artist LVS window to cycle through the different errors in the extracted view and then correct them in the layout view. Make sure to open the extracted view before doing this procedure. The schematic can then be opened to cycle through the errors there too. -> Also the shorts locator can be used to find any net locations causing trouble in the extracted view.

Following are some rules that can help you debug the design using the output from the Artist LVS window: Number of terminals don't match: This is commonly due to missing terminals/pins in the layout or mismatch in terminal names between layout and schematic. Number of nets don't match: If the number of nets given for your layout is higher than that of schematic then layout is missing some connections.

The first scenario for this situation is that your output will say something like?net /net 027 merged with / R. What the above line means is that net 027, which is some internal connection in the circuit, needs to be connected to terminal R. The second scenario for this situation is that your output will say something like terminal gnd! in layout fails to match any terminal in the schematic. In the given case,a transistor that should be connected to gnd! probably is not connected, so you would need to inspect your layout and find where a connection needs to be made. If the number of nets in the layout is less than that of the schematic then there are some connections in the layout that need not be made but are present.

Note : In case the LVS process terminates in the middle giving the following error: The LVS job failed to run to completion click on info button in the artist LVS window and open the log file and check the schematics that need a check and save(towards the bottom of the log file you will see something like xyz has been changed since last extracted). Check the save the required schematics and then re run LVS.

DRC LVS with Cadence Common Problems and Solutions

Metal 2 spacing DRC - you have a Vdd connection that is too close to a row power line and are getting a metal 2 spacing issue. See pic. Just move the power connection down a micron or so.

Metal 3 spacing DRC a quick jog in metal can cause a problem near a via. Just move the via farther away.

2024 © technodocbox.com Privacy Policy | Terms of Service | Feedback