Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs Shyue-Kung Lu and Shih-Chang Huang Department of Electronic Engineering Fu Jen Catholic University Hsinchuang, Taipei, Taiwan 242, R.O.C. Email: sklu@ee.fju.edu.tw Abstract High-density and high capacity embedded memories are important components for successful implementation of a system-on-a-chip. Since embedded memory cores usually occupy a large portion of the chip area, they will dominate the manufacturing yield of the system chips. In this paper, a novel built-in self-test and repair (BISTR) approach is proposed for semiconductor memories with -D redundancy (redundant rows) structures. The memory rows are virtually divided into row blocks and reconfiguration is performed at the row block level instead of the traditional row level. That is, the virtual divided word line (VDWL) concept is used for repairing of memory cores. The hardware overhead is almost negligible. An experimental chip is implemented and shows a low area overhead about 3.06% for a 256 52 SRAM with 4 spare rows. We also compare the repair rate of our approach with previous memory repair algorithms. It also concludes that our approach improves the repair rate significantly.. Introduction With the trend of system-on-a-chip (SoC) technology, high-density and high-capacity embedded memories are required for successful implementation of a system [, 2]. From the viewpoint of complexity, it is very difficult and costly to test embedded memories from an external memory tester as the chip density continues to grow. Moreover, the accessibility of embedded memories is low for external testers. A promising solution to this problem is the built-in self-test (BIST) [3-6]. However, as the density of memory increases, the circuits become more complex and are prone to suffering from defects. Therefore, it is difficult to keep a profitable yield model. In order to improve the fabrication yield, redundancies (redundant rows and/or columns) are often added such that most faulty memory cells can be replaced. When this happens, BIST circuits are required not only to detect the presence of faults but also to specify their locations for repair. The extended techniques of BIST are built-in selfdiagnosis (BISD) and built-in self-repair (BISR) [7-0]. Fault-tolerant designs of memories with redundancies have been widely used in the past. There are two possible solutions to add redundancy into a memory array: ) Spare Row or Spare Column (-D Redundancy) The memory contains spare rows or spare columns. When a fault is detected and must be repaired, the faulty row/column is replaced with one of the spare row/columns. Although it is easier to repair faulty cells, however, this approach is inefficient since a whole spare row/column should be used for repairing a single faulty cell. 2) Spare Row and Column (2-D Redundancy) With this approach, spare rows and spare columns are added in the memory array. Either a spare row or a spare column can be used to replace a faulty cell. This approach is more efficient than the first approach when multiple faulty cells are detected. However, the complexity for finding the optimal spare allocation is NP-complete [2]. Moreover, owing to the high bandwidth of embedded RAMs, more spare columns and rows are
required to achieve sufficient chip yield. This in turn increases the fabrication cost. For convenience, these two repair schemes are categorized as the row-based and/or column-based replacement algorithms. In order to cure these drawbacks described above, novel repair techniques are required for today s SoC era. In this paper, a novel built-in self-test and repair (BISTR) approach is proposed for semiconductor memories with -D redundancy (redundant rows) structures. The memory rows (including the redundant rows) are virtually divided into row blocks and reconfiguration is performed at the row block level instead of the traditional row level. That is, the virtual divided word line (VDWL) concept is used for repairing of memory cores. The fault-tolerant architecture can improve the yield for memory fabrication significantly. Moreover, the hardware overhead is almost negligible. An experimental chip is implemented and shows a low area overhead about 3.06% for a 256 52 SRAM. We also compare the repair rate of our approach with previous memory repair algorithms. It also concludes that our approach improves the repair rate significantly. The rest of this paper is organized as follows. Section 2 introduces the proposed BISTR architecture. The BISTR procedure is described in Section 3. Experimental results are shown in Section 4. Finally, conclusions are given in Section 5. 2. Proposed BISTR Scheme The simplified organization of a 2 m+n bit memory chip is shown in Figure (a). Activating one of the 2 m word lines is performed by the row decoder. The column decoder selects the column whose n-bit address is applied to the decoder input. The definition of address format for our BISTR technique is shown in Figure (b). Compared with the conventional address format as shown in Figure (c), we can see that the 2 n memory columns are divided into L virtual row banks (VRBs), L = 2 l. An example is shown in Figure 2, where m = 2, n = 4, and l = 2. That is, the memory array contains four word lines (W 0 W 3 ), sixteen bit lines, and four virtual row banks (VRB 0 VRB 3 ) are obtained. Each row within a virtual row bank is called a row block (RB). In other words, the Row Address Data in Data out 2 m Row Decoder Read /Write 0 2 m - Memory Array Word line 2 n columns Column Address (a) m bits l bits n-l bits (b) (c) One cell Column Decoder 2 n One column Row Address Bank Column Row Address m bits Column n bits 2 m rows Figure (a) Simplified organization of a memory chip; (b) the proposed address format, and (c) the conventional address format. memory array is divided into sixteen row blocks and there are four row blocks in a VRB. One thing should be noted that in Figure 2, two spare rows (W 4 and W 5 ) are also added (redundant columns are omitted for simplicity). These spare rows are also divided into row blocks. Therefore, we have eight spare row blocks as redundancies. The main scenario of our reconfiguration mechanism is that a faulty row block is replaced by a redundant row block in the same bank if there still exists spare row blocks. In Figure 2, faulty row blocks are dashed. As indicated by the arrows, faulty row blocks are repaired with their corresponding spare row blocks (grayed blocks). As a result, two spare rows (five spare blocks) are sufficient for successful replacement using our virtual_block_repair (VBR) approach. However, four redundant rows are required for traditional row-based replacement approaches. It is evident that our approach will result in better repair efficiency and the cost to achieve the specified yield is minimized.
Figure 2 The simple concept of the row-block repair scheme. 2 m FVRB CAM block Row decoder W 0 W W M- SR r- Virtual Row Bank Address VRB 0 r : No. of spare rows (SR). m : No. of row address bit. n : No. of column address bit. VRB architecture VRB VRB 2 VRB L- c 0 c c N- Column decoder Column Address C 0 within a VRB C n-l C n- VRB Address Figure 3 The BISR architecture of the faulttolerant memories. SR r- Figure 3 shows the general built-in self-repair (BISR) architecture for the fault-tolerant memories. The core memory array has M word lines (W 0 W M- ), N bit lines (c 0 c N- ), M = 2 m and N = 2 n, respectively. The l bits of the column addresses (C n-l C n- ) are used to determine the VRB of the accessed memory cell. Moreover, n-l bits (C 0 C n- l-) of the column addresses are used to select the intended column within the specified VRB. Besides, the memory contains r spare rows ( SR r- ). In this paper, the FVRB (faulty VRB) CAM block stores and compares the row and VRB addresses of the faulty row blocks is added into the memory architecture to achieve fault tolerance. The FVRB CAM block (Figure 4) contains two fields the FW field and the VRB field. The word addresses and VRB addresses of the faulty blocks are stored in the FW field (m bits) and the VRB field (l bits), respectively. The FVRB CAM block is divided into r sub CAM blocks (SUB, SUB 2,, SUB r- ). The word address and VRB address of the ith faulty block in VRB j is stored in the jth address of SUB i (FWVRB i,j ). Therefore, each sub block contains 2 l words. A brief scenario of our BISR approach is described as follows. When a memory cell is accessed in the normal mode, the row address and VRB address is sent to the FVRB CAM block to check whether the memory cell is faulty or not. If a match comes from SUB i, then the match signal is used to activate the spare row SR i and disable the normal word lines. After that, the specified spare row block will replace the faulty row block, i.e., the accessed data could be read or written regularly. If there are faulty row blocks detected in a memory array, our approach assures that faulty row blocks are disabled and spare row blocks are enabled simultaneously. Consequently, the VBR approach can be implemented easily to replace faulty row blocks by spare row blocks. It is important to note that the repair operation is transparent to the user. The memory system never stops its operation during the repair procedure. Since the row addresses are sent to the FVRB CAM block and the original row decoder, they are decoded simultaneously. Moreover, the FVRB CAM block usually has faster decoding speed then the original row decoder. Therefore, address remapping will not suffer from significant performance penalty. In addition, the added components for our approach can be implemented with simple circuits and the hardware overhead is relatively low. FWVRB 0,0 FWVRB r-2,0 FWVRB 0,... FWVRB r-2, Generator FWVRB 0,L- Row and VRB Addresses FWVRB r-2,l- Generator SR r-2 FWVRB r-,0 FWVRB r-, FWVRB r-,l- SUB SUB r-2 SUB r- Figure 4 The FVRB CAM block Generator SR r- The block diagram of the fault-tolerant memories with built-in self-test and repair capability (BISTR) is shown in Figure 5. It consists of the BISTR module and the BISTR wrapper. The BISTR module consists of the BIST
module and the BISR module as shown in Figure 6. The BIST module generates test patterns to detect the faults in the memory array, including the redundant words. The generation of test patterns can be programmed. The default algorithm is the March CW algorithm []. The BISR circuit is basically the FVRB CAM block, which performs redundancy allocation using the proposed scenario as described in the previous paragraph. The wrapper consists of a 2-to- multiplexer and the analyzer. The multiplexer can be used to select the addresses from the BIST module or the original memory ports. Figure 7 shows the BISTR procedure. The BISTR procedure can be activated when turning on the power. Moreover, it can also be started by activating the BISTR mode pin. Upon the BISTR procedure is started, the BIST circuit generates the test patterns specified by the March algorithm to test the spare memory array first during the BIST Spare Array session. In order to avoid using failed spare row blocks to repair failed row blocks in the memory array, it is necessary to test the spare array first. During this session, if some faults are detected (ErrMap = ), the BISR module sets the corresponding spare row blocks unusable. After the BIST Spare Array session is finished, the BIST Memory Array session follows. The row addresses and VRB addresses of faulty blocks must be stored into the BISR circuit (FVRB CAM block). If the spare array does not have enough useable spare blocks to repair the faulty cells, the fail indicator (FAIL) goes to high. This signal indicates that the memory chip can not be repaired. When the whole memory array has been tested (Finish = ) and the repair procedure is successful (FAIL = 0), then the system can operate normally. Figure 5 Block diagram of the proposed BISTR scheme. Figure 7 The BISTR procedure. 4. Experimental Results Figure 6 Block diagram of the BISTR module Therefore, the multiplexer can switch the memories between the BISTR mode and the normal mode. The analyzer compares the data from the BIST circuit (Data_T) with the outputs from the memory (Q). If the compared results do not match, the analyzer sends the signal ErrMap to indicate the faulty status. When the ErrMap signal is activated, this signal can be used to perform the repair procedure to repair the failed memory cells. 3. BISTR Procedure We discuss the repair rate of the proposed VBR scheme. Repair rate is defined as the probability of successful reconfiguration when there are defects in the memory array. We inject random cell faults into the memory array. During the repair rate analysis, the injected faults must be detected by the BIST module first. The number of injected faults may be too large that can t be repaired by the spare array. A 52 256 memory array is used to perform the analysis. The number of virtual row banks is assumed to be 4, 8, and 6, respectively. Figure 8 shows the compared results of repair rates between the Repair_Most (RM) algorithm and our VBR algorithm. We inject about 0.2% random cell faults in the memory array for this analysis. The number of spares x(y*z) means VBR algorithm that has x spare rows and RM algorithm that has y spare rows and z spare columns, i.e., x = y + z.
From this figure we can find that the VBR algorithm has higher repair rates. Moreover, the repair rate of VBR (6 VRBs) is higher than the VBR (8 VRBs). In other words, if there are more virtual row banks in the memory array, i.e., there are more row blocks in a row; more faulty cells can be repaired successfully. VBR (8VRB) RM VBR (4VRB) VBR (6VRB) Figure 8 The repair rate of RM algorithm and VBR algorithm. An experimental 256 52 SRAM chip with the proposed BISTR capability is designed and implemented with Synopsys Design Compiler synthesis tools. According to the experimental results, the hardware overhead is 3.06%. If the capacity of the memory increases, the hardware overhead will decrease further. 5. Conclusions In this paper, a novel virtual_block_repair faulttolerant architecture based on the concept of virtual divided word line is proposed for highcapacity memories. We divide the memory cell arrays into virtual row blocks and redundancies are added at the row block level. Our fault-tolerant architecture can improve the yield for memory fabrication significantly. The reconfiguration mechanism of our architecture requires negligible hardware overhead. According to experimental results, the hardware overhead is 3.06% for a 256 52-bit SRAM chip. We also compare the repair rate of our approach with previous memory repair algorithms. It also concludes that our approach improves the repair rate significantly. [] ERSO (Ed. M.-K. Lin), 997 semiconductor industry annual report, ITRS project report, Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan, June 997. [2] G. E. Moore, Progress in digital integrated electronics, in Proc. IEEE IEDM, pp. -3, 975. [3] J. Dreibelbis, J. Barth, H. Kalter, and R. Kho, Processor-based built-in self-test for embedded DRAM, IEEE Journal of Solid-State Circuits, vol. 33, pp. 73-740, Nov. 998. [4] S. Nakahara, K. Higeta, M. Kohno, T. Kawamura, and K. Kakitani, Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm, International Test Conference, pp. 30-30, 999. [5] C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, T.- Y. Chang, A programmable BIST core for embedded DRAM, IEEE Design & Test of Computers, vol. 6, pp. 59-70, Jan.-Mar. 999. [6] K. Zarrineh, and S. J. Upadhyaya, On programmable memory built-in self test architectures, Design, Automation and Test in Europe Conference and Exhibition, pp. 708-73, Mar. 999. [7] P. Mazumder, and J. S. Yih, A novel built-in selfrepair approach to VLSI memory yield enhancement, International Test Conference, pp. 833-84, Sept. 990. [8] I. Kim, Y. Zorian, G. Komoriya, H. Pham, F. P. Higgins, and J. L. Lewandowski, Built in self repair for embedded high density SRAM, International Test Conference, pp. 2-9, 998. [9] M. Horiguchi, J. Etoh, M. Aoki, K. Itoh, and T. Matsumoto, A flexible redundancy technique for high-density DRAM s, IEEE Journal of Solid-State Circuits, vol. 26, No., Jan. 99. [0] Kanad Chakraborty and Pinaki Mazumder Fault- Tolerance and Reliability Techniques for High- Density Random-Access Memories, Prentice Hall PTR Upper Saddle River, NJ 07458, http://www.phptr.com. [] C. F. Wu, C. T. Huang, and C. W. Wu. RAMSES: a fast memory simulator. Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), PP. 65-73, Albuquerque, Nov. 999. [2] S. Y. Kuo and W. K. Fuchs, Efficient spare allocation in reconfigurable arrays, IEEE Design & Test of Computers, vol. 4, pp. 24-3, 987. References