FFT Circuit Desig
Outlie Applicatios of FFT i Commuicatios Fudametal FFT Algorithms FFT Circuit Desig Architectures Coclusios
DAB Receiver Tuer OFDM Demodulator Chael Decoder Mpeg Audio Decoder 56/5/ 4/48 poit FFT Packet Demux Cotroller Cotrol Pael 3
LA OFDM System TRASMITTER FEC Coder S/P IFFT 64-pt Guard Iterval Isertio D/A LPF Up Coverter MAC Layer 6Mbps ~ 54Mbps RECEIVER FEC Decoder P/S FFT 64-pt Guard Iterval Removal A/D LPF Dow Coverter 4
ADSL (Discrete Multi-tue) System TRASMITTER Data I S/P QAM ecoders IFFT 5-pt add cyclic prefix P/S D/A + trasmit filter RECEIVER chael Data Out P/S QAM decoders FEQ FFT 5-pt S/P remove cyclic prefix TEQ receive filter + A/D 5
Applicatios of FFT i Commuicatios Comm. LA DAB DVB ADSL VDSL System FFT Size 64 56/5/ 4/48 48/ 89 5 5/4/ 48/496 OFDM DMT 6
Outlie Applicatios of FFT i Commuicatios Fudametal FFT Algorithms FFT Circuit Desig Architectures Coclusios 7
Fudametal FFT Algorithms Discrete Fourier Trasfer Pair Radix- FFT ( ν ) Decimatio-i-time (DIT) Decimatio-i-frequecy (DIF) FFT for composite ( ) Cooley-Tukey Algorithms Radix-r FFT 8
Discrete Fourier Trasform Pair Let DFT x[ ] X[ k] deote a DFP pair. e have X [ k ] x[ ] k, k,,...,, x[ ] X [ k ] k,,,...,, here, e j ( π / ). 9
Observatios k is -periodic. k is cojugate symmetric. Both x[] ad X[k] are -periodic. If x[] is real, the X[k] is cojugate symmetric ad vice versa.
Observatios A direct calculatio requires approximately complex multiplicatios ad additios. FFT algorithms reduce the computatio complexity to the order of log. Algorithms developed for FFT also works for IFFT with oly mior modificatios.
Example: Zero-Paddig (LA) Subcarriers LA 5 sub-carriers: use 64-poit FFT. ull # #.. #6 ull ull ull #-6.. #- # 6 7 37 38 6 63 IFFT 6 7 37 38 6 63 Time Domai Outputs
3 Decimatio-i-Time Radix- FFT,, ] [ ] [ ] [ ] [ / / / / + + + k H[k] G[k] r x r x x k X k kr r k kr r k K Assume is a eve umber.
Observatios G[k] is DFT of eve samples of x[]. H[k] is DFT of odd samples of x[]. G[k] ad H[k] are /-periodic. k+/ - k. 4
DIT Radix- FFT X [ r ] G[r] + r H[r], X [ r + / ] G[r] + ( r + / ) H[r], G[r] r < / -. r H[r], G[r] X[r] r H[r] X[r+/] - r 5
Decimatio-i-Time Radix- FFT Butterfly for Radix- DIT FFT (M) th stage r M th stage - r (M) th stage M th stage r I-place Computatio 6
Decimatio-i-Time Radix- FFT x[] x[] x[4] x[6] x[] x[3] x[5] x[7] First layer decimatio /-poit DFT /-poit DFT G[] G[] G[] G[3] H[] H[] H[] H[3] 3 X[] X[] X[] X[3] X[4] X[5] X[6] X[7] 7
Decimatio-i-Time Radix- FFT x[] X[] x[4] X[] x[] X[] x[6] X[3] x[] X[4] x[5] X[5] x[3] X[6] x[7] 3 X[7] 8
Bit Reversal x[ ] x[ ] x[ ] x[ ] x[ ] x[ ] x[ ] x[ ] x[ ] 9
Decimatio-i-frequecy Radix- FFT,, ]) / [ ] [ ( ] [ ]) / [ ] [ ( ] [,,, ] [ ] [ / ) / ( / ) / ( - / r x x r X x x r X k x k X r r k K K + + + + Assume is a eve umber.
Decimatio-i-frequecy Radix- FFT,, where,, ] [ ] [, ] [ ] [ / ) / ( / ) / ( - / r ]) / x[ (x[] h[] ]) / x[ (x[] g[] h r X g r X r r K + + + +
Decimatio-i-frequecy Radix- FFT Butterfly for Radix- DIF FFT (M) th stage M th stage I-place Computatio
Decimatio-i-frequecy Radix- FFT First layer decimatio x[] g[] X[] x[] x[] x[3] g[] g[] g[3] /-poit DFT X[] X[4] X[6] x[4] x[5] x[6] x[7] h[] h[] h[] h[3] 3 /-poit DFT X[] X[3] X[5] X[7] 3
Decimatio-i-frequecy Radix- FFT x[] X[] x[] X[4] x[] X[] x[3] X[6] x[4] X[] x5] X[5] x[6] X3] x7] 3 X7] 4
Butterfly Compariso Butterfly (decimatio-i-frequecy) (M) th stage M th stage Butterfly (decimatio-i-time) (M) th stage M th stage r 5
6 Cooley-Tukey Algorithm ]. k X[ ] [ ], x[ ] [ : t arrageme - re poit D,,,,,, k k X x k k k k + + + +
7 Cooley-Tukey Algorithms, ] [ ] [ k k k x k X + ], [ k G Twiddle factor ], [ ~ k G
Observatios, / -> st stage of the decimatio i frequecy radix- FFT. /, -> st stage of the decimatio i time radix- FFT. I geeral,. If r -> Radix-r. 8
Radix-3 FFT (DIF) Assume is a multiple of 3. X[ k] X[3r ] X[3r + ] X[3r + ] x[ ] ( /3) ( /3) r ( /3) r k ( x[ ] + x[ + /3] + x[ + /3]) ( x[ ] + x[ + /3] e ( x[ ] + x[ + /3] e jπ 3 jπ 3 r /3 + x[ + /3] e + x[ + /3] e jπ 3 jπ 3 ) ) r /3 r /3 9
Radix-3 FFT (DIF) Butterfly for Radix-3 DIF FFT (M) th stage 3 e jπ j π 3 e M th stage j π 3 e 3 e jπ 3
Radix-4 FFT (DIF) Assume is a multiple of 4. X[4 r] X[4 r+ ] X[4 r+ ] X[4 r+ 3] ( /4) ( /4) r ( /4) r ( /4) r ( x[ ] + x[ + /4] + x[ + /4] + x[ + 3 /4]) r /4 ( x[ ] + ( j) x[ + /4] + ( ) x[ + /4] + jx [ + /4]) ( x[ ] + ( ) x[ + /4] + x[ + /4] + ( ) x[ + 3 /4]) 3 r /4 ( x[ ] + jx [ + /4] + ( ) x[ + /4] + ( j) x[ + 3 /4]) r /4 r /4 3
Radix-4 FFT (DIF) Butterfly for Radix-4 DIF FFT (M) th stage M th stage 3
Split Radix FFT Mix Radix- ad Radix-4 architecture. Compute eve trasform coefficiets based o Radix- strategy ad odd coefficiets based o Radix-4 strategy. Ca perform FFT for ν. 33
Simplify Butterfly Represetatios Radix- Radix-4 34
Split-Radix FFT 35
Computatioal Complexity Method # of Complex Multiplicatios # of Complex Additios DFT () Radix- (/) log log Radix-4 (3/8) log (3/) log The above umbers do ot tell the whole story! Architecture is the key issue to trade of amog performace, cost, hardware complexity, etc. 36
Outlie Applicatios of FFT i Commuicatios Fudametal FFT Algorithms FFT Circuit Desig Architectures Coclusios 37
FFT Architecture Desig Cosideratios Trade-off amog accuracy, speed, hardware complexity, ad power cosumptio best fit architecture should be applicatio depedet. Mai architecture differeces i: Degrees of parallelism umber ad complexity of processig elemets, Cotrol schemes - hardware utilizatio ad data flow cotrol. 38
Degree of Parallelism Oe simple processig uit or multiple simple processig uits x[] X[] x[4] X[] x[] x[6] x[] X[] X[3] X[4] x[5] x[3] x[7] 3 X[5] X[6] X[7] 39
Degree of Parallelism Simple processig uits versus complicate processig uits 4
Memory-based FFT architecture Sigle butterfly or processig elemet. Required memory size. A cotrol uit esures the right data flows to compute FFT. Firmware Like. Low complexity. Low speed. 4
Memory-based FFT Block Diagram Data I Iput Buffer Coefficiets ROM or Geerator Butterfly or Processig Elemet RAM Data Out Cotrol Cotrol Uit 4
Pipelie Architectures FFT Sigal Flow Graph Multiple path delay commutator Sigle path delay commutator Sigle path delay feedback 43
Radix- Sigal Flow Graph (DIT) x[] X[] x[4] x[] x[6] x[] x[5] x[3] x[7] 3 X[] X[] X[3] X[4] X[5] X[6] X[7] BF Buffer BF Buffer BF ROM ROM ROM 44
Radix- Sigal Flow Graph (DIF) x[] x[] x[] x[3] x[4] x5] x[6] x7] 3 X[] X[4] X[] X[6] X[] X[5] X3] X7] BF Buffer BF Buffer BF ROM ROM ROM 45
Multi-Path Delay Commutator Delay Commutator (switch) Butterfly Delay Delay Delay 46
Radix- Multi-Path Delay Commutator x[] x[] x[] x[3] x[4] x5] x[6] x7] 7 6 5 4 3 3 switch 4 5 6 7 3 delay 3 4 5 6 7 butterfly 3 4 5 6 7 X[] X[4] X[] X[6] X[] X[5] X3] X7] delay 3 4 5 6 7 switch 5 4 7 6 3 delay 5 4 7 6 3 5 4 7 6 3 butterfly delay 5 4 7 6 3 switch 6 4 7 5 3 delay 6 4 7 5 3 butterfly 6 4 7 5 3 47
Radix- Multi-Path Delay Commutator 8 4 C BF C BF C BF C BF 4 6 48
Radix-4 Multi-Path Delay Commutator 9 48 3 8 C4 BF4 64 6 3 C4 3 6 BF4 4 8 C4 8 4 BF4 C4 BF4 48 3 56 49
Sigle Path Delay Commutator Delay Commutator Butterfly 5
Radix- Sigle Path Delay Commutator DC BF DC BF DC BF DC BF 6 5
Radix-4 Sigle Path Delay Commutator DC4 BF4 DC4 BF4 DC4 BF4 DC4 BF4 56 5
Sigle Path Delay Feedback Delay Butterfly 53
Radix- Sigle Path Delay Feedback 8 4 BF BF BF BF 6 54
Radix-4 Sigle Path Delay Feedback 64x3 6x3 4x3 x3 BF4 BF4 BF4 BF4 56 55
R SDF 8 64 3 6 8 4 BF I BF II BF I BF II BF I BF II BF I BF II 56 56
Hardware Compariso Architecture Multiplier # Adder # Memory Size Cotrol RMDC RSDF R4MDC R4SDF R4SDC R SDF (log 4 ) (log 4 ) 3(log 4 ) log 4 log 4 log 4 4 log 4 4 log 4 8 log 4 8 log 4 3 log 4 4 log 4 3/- 5/-4 - simple simple simple medium complex simple 57
Coclusios Effect FFT computatio is essetial to may commuicatio applicatios utilizig OFDM or DMT techique. A pipelied FFT architecture is applied where a high real-time performace is required. A memory-based FFT architecture ca be adopted whe cost is more cocered tha speed. A best fit FFT architecture depeds o applicatio specific requiremets to trade off amog accuracy, speed, chip size, power cosumptio, etc. 58