IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -4 1 UNIT 4

IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -4 1 UNIT 4 4.1. Serial data communication basics ----------- 1 4.2. UART ------------------------------------------------ 4 4.3. Serial Peripheral Interface (SPI)---------------- 7 4.4. Inter Integrated Circuit ( I2C) ------------------ 13 4.1. SERIAL DATA COMMUNICATION - BASICS Within a micro-computer system, the data transfer is in parallel because it is the fastest method. But transferring the data over long distances, the parallel data transmission requires too many wires and it is complicated and expensive. Therefore, the data to be sent for long distances is converted into serial form so that it can be sent on a single wire. At the destination, the received serial data is converted into parallel form so that it can be easily transferred on the microcomputer buses. Methods of serial data transmission: (i) Simplex : In this mode, the data is transmitted only in one direction over a single communication channel. Ex: CPU to CRT display, Key board to CPU, Radio signal (ii) Half-dupplex : In this mode, the data is transmitted in both directions, but only one direction at a time. i.e., simultaneous data transfer is not possible Ex: Walkie Talkie (iii) Full-dupplex : In this mode, the data transmission takes place in both directions simultaneously. It requires two channels. Ex: Telephone communication

IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -4 2 Synchronous Vs Asynchronous data transfer modes Synchronous data transmission Asynchronous data transmission Transmitter and Receiver are operated with same CLK frequency. SYNC pulses are required A group of characters can be transmitted after sending the SYNC pulses It is used in high speed data transmission Generally used between CPU and other devices on the same PCB, as the same power supply and CLK are used. Ex: SPI, I2C Transmitter and Receiver can operated with different CLK frequency. START and STOP bits are required For each character, the START & STOP bits are required. It is used in low speed data transmission It is used to exchange data with other equipment such as PC. Ex: UART The universal serial communication interface (USCI) module of MSP430 support multiple serial communication modes. The THREE common types of serial communication are Asynchronous serial communication Serial peripheral interface (SPI). Inter-integrated circuit (I²C) bus. The asynchronous systems must conform fully to established standards so that they work reliably and must be protected against electromagnetic interference and other hazards. This requires special interface circuits. On the other hand, simple wires are usually sufficient for SPI and I²C provided that all devices work at the same voltage. SPI and I²C are synchronous, which means that a clock signal is sent along with the data. The device that generates the clock is called the master and other devices are slaves. An extra wire carries the clock.

IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -4 3 In contrast, no clock signal is transmitted in asynchronous communication. Information must therefore be sent in separate frames, each of which is short enough that the separate clocks in the transmitter and receiver remain synchronized. In practice the frames are almost always single bytes. Transmission and reception are essentially separate processes and can take place together, giving full-duplex communication. The major practical difference is that SPI and I²C are typically used between a microcontroller and other devices on the same PCB, while asynchronous communication is used to exchange data with other equipment such as a PC. The major difference between them is that I²C is a true bus, which is designed to accommodate a large number of devices. Transactions follow a protocol that starts with an address to select a particular slave and includes acknowledgment bits to confirm successful delivery. There is only one wire for data, giving a total of two with the clock. Data can travel in either direction but only in one way at a time, which is called half-duplex transmission. In contrast, SPI uses two lines for data so that information can be sent simultaneously in both directions. In fact both processes must occur together because of the concept that underlies SPI. The full version of SPI includes a further line that is used to select a particular slave and gives a total of four wires for the interface. The SPI needs more wires than I²C and offers less sophistication but is simpler and faster. This makes SPI more suitable when large amounts of data have to be transferred. SPI and I²C have similar applications. SPI and I²C are often used to communicate with Port expanders to increase the effective no. of pins for digital input and output. ADCs and DACs. Sensors with digital outputs, such as thermometers. External memory (dataflash, EEPROM). Real-time clocks. Other processors.

IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -4 4 4.2. UART ( Universal Asynchronous Receiver Transmitter) : The universal asynchronous receiver/transmitter (UART) takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes. Each UART contains a shift register, which is the fundamental method of conversion between serial and parallel forms. UART mode features include: 1. 7 or 8-bit data with odd, even, or non-parity 2. Independent transmit and receive shift registers 3. Separate transmit and receive buffer registers 4. LSB-first or MSB-first data transmit and receive 5. Built-in idle-line and address-bit communication protocols for multiprocessor systems 6. Receiver start-edge detection for auto-wake up from LPMx modes 7. Programmable baud rate with modulation for fractional baud rate support 8. Status flags for error detection and suppression 9. Status flags for address detection 10. Independent interrupt capability for receive and transmit

IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -4 5 Format of Data for Asynchronous Transmission Data are sent in short frames, and each frame contains One low start bit (ST). Eight data bits, usually LSB first One or Two high stop bits (SP) The UART character format, shown in below Figure, consists of a start bit, seven or eight data bits, an even/odd/no parity bit, an address bit (address-bit mode), and one or two stop bits. The UCMSB bit controls the direction of the transfer and selects LSB or MSB first. In most applications the least significant data bit (LSB) is transmitted first. The start bit signals the receiver that a new character is coming. The next bits represent the character. If a parity bit is used, it would be placed after all of the data bits. The next one or two bits are always in the mark (logic high, i.e., '1') condition and called the stop bit(s). They signal the receiver that the character is completed. Since the start bit is logic low (0) and the stop bit is logic high (1) there are always at least two guaranteed signal changes between characters. All operations of the UART hardware are controlled by a clock signal which runs at a multiple of the data rate, typically 8 times the bit rate. The receiver tests the state of the incoming signal on each clock pulse, looking for the beginning of the start bit. Setting a Baud Rate The baud rate gives the frequency at which bits are transmitted on the line. It is the inverse of the bit period and the name is used to distinguish it from the rate at which useful data are communicated. If the baud rate is x bits per second, the time slot available for one bit is 1/x seconds. Each 8 bits of data are accompanied by a start and stop bit so the maximum data rate is only 8/10 of the baud rate. No clock is transmitted in asynchronous communication so the transmitter and receiver must run independently at nearly the same baud rates. For a given BRCLK clock source, the baud rate is used determines the required division factor N : N = f BRCLK/Baudrate The division factor N is often a non-integer value, thus, at least one divider and one modulator stage is used to meet the factor as closely as possible.

IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -4 6 Automatic Error Detection The USCI module automatically detects framing errors, parity errors, overrun errors, and break conditions when receiving characters. The bits UCFE, UCPE, UCOE, and UCBRK are set when their respective condition is detected. When the error flags UCFE, UCPE, or UCOE are set, UCRXERR is also set. Error Error flag Description Framing error UCFE Framing error occurs when a low stop bit is detected Parity error Over run error Break condition UCPE UCOE UCBRK Parity error is mismatch between the no.of 1 s in a character and the value of parity bit. Overrun error occurs when a character is loaded into UCARxBUF before the prior character has be read. When not using automatic baud-rate detection, a break is detected when all data, parity and stop bits are LOW. UCAxCTL0 (USCI_Ax Control register0) : UCA0CTL0 This register controls the settings for Parity selection, direction of data transmission (LSB or MSB first),character length, no of stop bits, modes of serial transmission. 7 6 5 4 3 2 1 0 UCPEN UCPAR UCMSB UC7BIT UCSPB UCMODEx UCSYNC=0 Bit 7 UCPEN Parity enable Bit 6 UCPAR Parity select Bit 5 UCMSB MSB first select. Bit 4 UC7BIT Character length 0 Disables Parity 1 Enables Parity 0 Odd parity 1 Even parity 0 LSB first 1 MSB first 0 8-bit data 1 7-bit data Bit 3 UCSPB No. of Stop bits select. 0 1-Stop bit 1 2-Stop bits If UCSYNC = 0 then Bit 2-1 UCMODEx USCI mode. 00 UART mode 01 Idle-line multiprocessor mode 10 Address-bit multiprocessor mode 11 UART mode with automatic baud-rate detection Bit 0 UCSYNC Synchronous mode enable 0 Asynchronous mode 1 Synchronous mode

IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -4 7 4.3. Serial Peripheral Interface (SPI) : The serial peripheral interface (SPI) was introduced by Motorola and is the simplest synchronous full duplex communication protocol. SPI is a single master multi-slave system. SPI requires 4- signal lines for communication. They are : MOSI : Master out slave in signal line carries the data from Master to Slave device It is also called as Slave data in (SDI) / Slave input (SI) /Data in (DI) MISO : Master in slave out signal line carries the data from Slave to Master device It is also called as Slave data out (SDO) /Slave output (SO) / Data out (DO) SCLK : Serial Clock signal line carries the clock signals. SS : Slave Select signal is used for slave device select. Usually it is active LOW signal The concept of SPI is shown in figure : The SPI requires four wires (plus ground, which is essential but never counted) and transmits data simultaneously in both directions (full duplex) between two devices. One device is the master and the other the slave. The master provides the clock for both devices and a signal to select (enable) the slave, but the path followed by the data is identical in each. SPI works on the principle of Shift Registers. The master and slave devices contain a special shift register for the data transmit and receive. During transmission from master to slave, the data in the master s shift register is shifted out to the MOSI pin and it enters the slave s shift register through MOSI pin. At the same time, the shifted out data bit from the slave s shift register enters the master s shift register. In summary, the shift registers of master and slave devices form a circular buffer (loop).

IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -4 8 The concept of SPI is based on two shift registers, one in each device, which are connected to form a loop. The registers usually hold 8 bits. Each device places a new bit on its output from the most significant bit (MSB) of the shift register when the clock has a negative edge and reads its input into the LSB of the shift register on a positive edge of the clock. Thus a bit is transferred in each direction during each clock cycle. After eight cycles the contents of the shift registers have been exchanged and the transfer is complete. Transmission and reception are clearly inseparable: we can t do one without the other, at least in principle. Thus a byte must be transmitted in order to receive a byte. Suppose, if we want to send only a single bit, it requires three steps: 1. Put data on output. 2. Read data from input. 3. Remove data from output. A single cycle of the clock provides stimuli for only two of these so the third is taken from SS. It can either start or end the transmission and this option is specified by the clock phase bit, CPHA in Motorola s notation: If CPHA = 0 : Read on the leading edge of each clock pulse. Written on the trailing edge of each clock pulse. If CPHA = 1: Written on the leading edge of each clock pulse. Read on the trailing edge of each clock pulse Thus CPHA controls whether writing and reading take place on the leading and trailing edges of the clock pulses or vice versa. This is the first of many options that control the configuration of SPI. A related option is the clock polarity, selected with the CPOL bit: CPOL = 0: CPOL = 1: Inactive state is Low ( Positive Clock) Inactive state is High ( Negative Clock) There is no fundamental difference between these two polarities: One is just the complement of the other. Combinations of the two bits CPOL and CPHA give four standard modes for the clock in SPI, which are listed in the following Table.

IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -4 9 The following figures illustrate complete waveforms for a 4-bit transfer in modes 0 and 3. There are two ways of connecting multiple slaves to a single master. In both cases the master provides the clock to all the slaves. Slaves can be addressed individually.

IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -4 10 In the first configuration, all the MOSI pins are connected together, but each slave s SS pin is connected to a separate pin on the master. Slaves must ignore data on MOSI when their SS pin is idle, despite the activity on the clock, and must leave their MISO pins in a high-impedance state. In other words, the MISO pins must have three-state outputs. The alternative is to connect all the devices in a daisy chain, as shown in Figure(b). In this configuration, the MISO pin of a slave is connected to the MOSI pin of the next slave in the chain. The MOSI pin of the final slave is connected to MOSI on the master. Effectively all the shift registers inside each device are connected into a single, long loop. The slaves must allow data to be clocked through them transparently while SS is held active and react to the new data only when SS is released. USCI - SPI Mode In synchronous mode, the USCI connects the MSP430 to an external system via 3 (or) 4 pins: UCxSIMO, UCxSOMI, UCxCLK, and UCxSTE. SPI mode is selected when the UCSYNC bit = 1 and SPI mode (3-pin or 4-pin) is selected with the UCMODEx bits. ( UC control register) SPI mode features include: 1. 7- or 8-bit data length 2. LSB-first or MSB-first data transmit and receive 3. 3-pin and 4-pin SPI operation 4. Master or slave modes 5. Independent transmit and receive shift registers 6. Separate transmit and receive buffer registers 7. Continuous transmit and receive operation 8. Selectable clock polarity and phase control 9. Programmable clock frequency in master mode 10. Independent interrupt capability for receive and transmit 11. Slave operation in LPM4 In SPI mode, serial data is transmitted and received by multiple devices using a shared clock provided by the master. An additional pin, UCxSTE, is provided to enable a device to receive and transmit data and is controlled by the master. 3 (or) 4 signals are used for SPI data exchange:

IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -4 11 Master Mode : The above figure shows the USCI as a master in both 3-pin and 4-pin configurations. The USCI initiates data transfer when data is moved to the transmit data buffer UCxTXBUF. The UCxTXBUF data is moved to the TX shift register when the TX shift register is empty, initiating data transfer on UCxSIMO starting with either the MSB bit or LSB bit depending on the UCMSB setting. Data on UCxSOMI is shifted into the receive shift register on the opposite clock edge. When the character is received, the receive data is moved from the RX shift register to the received data buffer UCxRXBUF and the receive interrupt flag (UCxRXIFG) is set, indicating the RX/TX operation is complete. A set transmit interrupt flag (UCxTXIFG) indicates that data has moved from UCxTXBUF to the TX shift register and UCxTXBUF is ready for new data. It does not indicate RX/TX completion. Slave Mode : The above figure shows the USCI as a slave in both 3-pin and 4-pin configurations. UCxCLK is used as the input for the SPI clock and must be supplied by the external master. The data-transfer rate is determined by this clock and not by the internal bit clock generator.

IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -4 12 Data written to UCxTXBUF and moved to the TX shift register before the start of UCxCLK is transmitted on UCxSOMI. Data on UCxSIMO is shifted into the receive shift register on the opposite edge of UCxCLK and moved to UCxRXBUF when the set number of bits are received. When data is moved from the RX shift register to UCxRXBUF, the UCxRXIFG interrupt flag is set, indicating that data has been received. The overrun error bit, UCOE, is set when the previously received data is not read from UCxRXBUF before new data is moved to UCxRXBUF. UCAxCTL0, USCI_Ax Control Register 0, 7 6 5 4 3 2 1 0 UCCKPH UCCKPL UCMSB UC7BIT UCMST UCMODEx UCSYNC=1 Bit 7 UCCKPH Clock Phase select 0 Read on the leading edge & Written on the trailing edge of each clock pulse. 1 Written on the leading edge & Read on the trailing edge of each clock pulse Bit 6 UCCKPL Clock Polarity select 0 Inactive state is Low ( Positive Clock) 1 Inactive state is High ( Negative Clock) Bit 5 UCMSB MSB first select Bit 4 UC7BIT Character length Bit 3 UCMST Master mode select 0 LSB first 1 MSB first 0 8-bit data 1 7-bit data 0 Slave mode 1 Master mode If UNSYNC = 1 then Bit 2-1 UCMODEx USCI mode. 00 3-pin SPI 01 4-pin SPI with UCSTE active high 10 4-pin SPI with UCSTE active high 11 I2C Bit 0 UCSYNC Synchronous mode enable 0 Asynchronous mode 1 Synchronous mode

IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -4 13 4.4. Inter Integrated Circuit ( I 2 C) Bus : The I²C bus was introduced by Philips (now NXP) Semiconductors. It is a Synchronous Half duplex Serial communication protocol The I²C bus uses only two bidirectional lines - Serial data (SDA) and Serial clock (SCL). Of course there must be a connection for ground as well. It is often called the two-wire interface. Thus I²C provides the full functionality of a bus while using fewer lines than SPI. Transfers on the bus take place between a master and a slave. Each slave has a unique address, which is usually 7 bits long. The master starts the transfer, provides the clock, addresses a particular slave, manages the transfer, and finally terminates it. There may be more than one master on the bus although only one can be in control at a time. Hardware for I²C The electronic interface to the I²C bus is shown in Figure 10.11 for a master and two slaves. A full-featured slave has the same hardware as a master but most are simpler and cannot drive the clock line SCL. On the other hand, slaves must always be able to drive SDA. Digital outputs are normally driven actively for both their binary values, either to V SS for logic 0 or to V CC for logic 1. Pull-up resistors Rp keep the lines at V CC when none of the drivers is active. The devices must therefore have open-drain (or open-collector) outputs. This means that there is only an n-channel MOSFET between the output and ground as in Figure 10.11. The pull-up resistor Rp holds the line at VCC when there is no activity, so both the clock and data idle high. If a single n-mosfet is turned on, its line is pulled down to VSS to give a logical 0.

IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -4 14 USCI - I2C Mode In I2C mode, the USCI module provides an interface between the MSP430 and I2Ccompatible devices connected by way of the two-wire I2C serial bus. External components attached to the I2C bus serially transmit and/or receive serial data to/from the USCI module through the 2-wire I2C interface. The I2C mode features include: 1. 7-bit and 10-bit device addressing modes 2. General call 3. START/RESTART/STOP 4. Multi-master transmitter/receiver mode 5. Slave receiver/transmitter mode 6. Standard mode up to 100 kbps and fast mode up to 400 kbps support 7. Programmable UCxCLK frequency in master mode 8. Designed for low power 9. Slave receiver START detection for auto-wake up from LPMx modes 10. Slave operation in LPM4

IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -4 15 USCI Operation: I2C Mode The I2C mode supports any slave or master I2C-compatible device. Each I2C device is recognized by a unique address and can operate as either a transmitter or a receiver. A device connected to the I2C bus can be considered as the master or the slave when performing data transfers. A master initiates a data transfer and generates the clock signal SCL. Any device addressed by a master is considered a slave. I2C data is communicated using the serial data pin (SDA) and the serial clock pin (SCL). Both SDA and SCL are bidirectional, and must be connected to a positive supply voltage using a pull-up resistor. BRCLK can be taken from ACLK, SMCLK, and UC1CLK chosen with UCSSELx. The frequency is then divided by the value in the UCBRx I2C mode selected using UCMODEx bit in the control register. I²C Protocol A simple example of a transfer on I²C is shown in Figure 10.12, where the master reads a single byte from the slave. Transfers consist of a sequence of 8-bit bytes, which are sent with the MSB first and must be acknowledged to confirm successful reception. The recipient does this by writing a further acknowledgment (A) bit of 0 to SDA. 1. The master sends a start condition (S) by pulling SDA low while SCL is high. 2. The master starts the clock and puts the first bit of the address on SDA after SCL has gone low. 3. The value on SDA is valid after SCL has gone high and is read by all slaves on the bus. 4. The last two steps are repeated until all 7 bits of the address have been sent. 5. The final bit of the first byte specifies the direction for the rest of the transfer. Here it is R/W= 1, which shows that the master wishes to read data from the slave.

IV B.Tech. I Sem (R13) ECE : Embedded Systems : UNIT -4 16 6. The ninth bit is the acknowledgment (A or Ack), which is low and is sent by the slave that recognizes its address. 7. The master must check that a slave acknowledges the address and abort the transfer if the low bit is missing. 8. The next 8 clock cycles are used to transmit 1 byte of data from the slave to the master. The master continues to provide the clock. 9. The 9 th bit would normally be an acknowledgment bit, which signals to the slave that the master has received sufficient data. 10. There is a final cycle of the clock to set up the stop signal (P). The master sends a stop condition (S) by pulling SDA high while SCL is high. Thus transfers Begin with a start condition (S), shown by a falling edge on SDA while SCL is high. End with a stop condition (P), shown by a rising edge on SDA while SCL is high. Both the SCL and SDA lines are high before a start condition and after a stop condition, which is the idle state of the bus UCAxCTL0, USCI_Ax Control Register 0 : 7 6 5 4 3 2 1 0 UCA10 UCSLA10 UCMM -- UCMST UCMODEx = 11 UCSYNC=1 Bit 7 UCA10 Own Address mode select 0 Own address is a 7-bit address 1 Own address is a 10-bit address Bit 6 UCSLA10 Slave addressing mode select 0 Address slave with 7-bit address 1 Address slave with 10-bit address Bit 5 UCMM Multi-master environment select 0 Single master environment. 1 Multi-master environment Bit 4 NOT USED Bit 3 UCMST Master mode select 0 Slave mode 1 Master mode If UNSYNC = 1 then Bit 2-1 UCMODEx USCI mode. 00 3-pin SPI 01 4-pin SPI with UCSTE active high 10 4-pin SPI with UCSTE active high 11 I2C Bit 0 UCSYNC Synchronous mode enable 0 Asynchronous mode 1 Synchronous mode