Hardware Description Languages (HDLs) Verilog Material from Mano & Ciletti book By Kurtulus KULLU Ankara University
What are HDLs? A Hardware Description Language resembles a programming language specifically oriented to describe hardware HDL model can be simulated to check and verify a circuit s functionality Also, automatic tools can optimally synthesize the logic described by an HDL model 2 HDLs (Verilog and VHDL) are approved as standards by IEEE and widely used.
Verilog
Verilog A module is the fundamental descriptive unit in Verilog Name and list of ports
Verilog Internal connections Primitive gate instantiations: Keyword name(output and inputs)
Delays in Verilog
Test Bench
Verilog Simulation Results
Boolean Expressions keyword assign symbols &,, and! for AND, OR, and NOT The previous example circuit could be defined with the statement assign D = (A && B) (!C);
Modeling with Expressions Description below specifies a circuit with the following two Boolean expressions E = A + BC + B D F = B C + BC D
User-defined Primitives and Truth Tables Users can create their own primitives (with keyword primitive) There can only be one output which is written first A truth table can be given between table and endtable
Instantiating User-Defined Primitives
HDL Models Logic of a module can be described in different ways Gate-level modeling Gates and how they are connected together Dataflow modeling Operators that act on binary operands and produce a binary result Behavioral modeling Circuits at a functional and algorithmic level (mostly used for sequential circuits)
Gate-Level Description of a 2-to-4-Line Decoder
Gate-Level Description of a 2-to-4-Line Decoder Defines a vector with 4 bits (0 to 3)
Bottom-up Hierarchical Description of a 4-bit Adder (1/2)
Bottom-up Hierarchical Description of a 4-bit Adder (2/2)
Dataflow Modeling Uses operators that act on binary operands to produce a binary result
Dataflow Model of 4-bit Adder
Behavioral Modeling Represent circuits at an algorithmic level Mostly used to describe sequential circuits Behavioral descriptions use keyword always
Behavioral Modeling Represent circuits at an algorithmic level Mostly used to describe sequential circuits Behavioral descriptions use keyword always Execute the below statements if one of the following values change Could only say if (select)
Writing Test Benchs initial begin D 3 b000; repeat (7) #10 D D 3 b001; end Repeat specifies a looping statement A stimulus module has the following form: module test_module_name; // Declare local reg and wire identifiers. // Instantiate the design module under test. // Specify a stopwatch, using $finish to terminate the simulation. // Generate stimulus, using initial and always statements. // Display the output response (text or graphics (or both)). endmodule
Writing Test Benchs System tasks are system functions that begin with the symbol $ Some of the system tasks that are useful for display are $display display a one-time value of variables or strings with an end-of-line return, $write same as $display, but without going to next line, $monitor display variables whenever a value changes during a simulation run, $time display the simulation time, $finish terminate the simulation.
Behavioral Modeling of Sequential Circuits Two possible ways to produce clock signal initial begin clock = 1'b0; repeat (30) #10 clock = ~clock; end initial begin clock = 1'b0; end initial 300 $ finish; always #10 clock = ~clock;
Behavioral Modeling of Sequential Circuits
Summary We only looked at a summary of HDLs There are many other capabilities State diagram-based models Structural description of sequential circuits Registers Counters The primary aim is to make circuit design and testing (simulating) easy and automatic synthesis possible