Performing Multi-Phased Radar Processing with a Very Deep FPGA Pipeline

Transcription

1 Performing Multi-Phased Radar Processing with a Very Deep FPGA Pipeline Jeffrey T. Muehring and John K. Antonio School of Computer Science University of Oklahoma antonio@ou.edu 2000 MAPLD Conference The 3 rd Annual Military and Aerospace Applications of Programmable Devices and Technologies International Conference September 26-28, 2000

2 Outline Review of multiprocessor-based solution for Synthetic Aperture Radar (SAR) Proposed FPGA-based deep-pipeline solution for SAR An initial comparison of multiprocessor-based and FPGA-based solutions for SAR A framework for minimizing power consumption of deep pipelines based on signal activity transformations Summary

3 Typical Scenario for SAR Predator

4 Footprint of Aerial Side-Looking SAR Velocity Footprint Range Azimuth Targets

5 Offset Overlapping Beams Real Azimuth Resolution v R s

6 Synthetic Beams Azimuth v R Compressed Resolution R s

7 Overview of SAR Processing Two Main Phases of Computation for a SAR Processing Phase Range Processing Phase 2 Azimuth Processing Outputs Input Data Stream Typical Timing Diagram for Executing SAR on a Multiprocessor System Processor Sets S 2 S Time

8 Typical Communication Requirements for SAR on a Multiprocessor System Phase Range Processing (shown distributed across 3 processors) Phase 2 Azimuth Processing (shown distributed across 4 processors) azimuth processor 4 range processor 3 azimuth processor 3 range processor 2 distributed corner turn pulses range samples range processor azimuth processor 2 azimuth processor range samples pulses Reference:T. Einstein, Realtime Synthetic Aperture Radar Processing on the RACE Multicomputer, App. Note 203.0, Mercury Computing Sys, 996.

9 Typical Processing Flow for SAR on a Multiprocessor System Input Data (Pulse Returns) m n n Range Processing (r-tap FIR)* n m n Output Image Distributed Corner Turn Azimuth Processing (a-tap FIR)* *Typically performed using FFT-based fast convolution technique m

10 Outline Review of multiprocessor-based solution for Synthetic Aperture Radar (SAR) Proposed FPGA-based deep-pipeline solution for SAR An initial comparison of multiprocessor-based and FPGA-based solutions for SAR A framework for minimizing power consumption of deep pipelines based on signal activity transformations Summary

11 Tracing of Computational Dependencies for a Single Input Range Bin Input Data (Pulse Returns) (assume r = 3) m n n (m/2)-th pulse return Range Processing (r-tap FIR) n m (assume a = 5) n Output Image Distributed Corner Turn Azimuth Processing (a-tap FIR) m

12 Computation of Output Values Associated with Single Input Range Bin using Proposed Deep-Pipe Input Data (Pulse Returns) (assume r = 3, a = 5, n = 0) n Deep Pipeline (a r)-tap FIR interspersed with a (n - r) delay elements (m/2)-th pulse return Note: each output value is the sum of a r weighted input values Computation of Output Image Samples: after c cycles after c + cycles after c + n cycles after c + (a n) cycles n n n n m m m m

13 Structure of the Deep-Pipeline Example: no. range bins = n = 4 range kernel size = r = 2 azimuth kernel size = a = 3 R 0 > R > R 2 > R 3 > R 4 > R 5 > R 6 > R 7 > R 8 > R 9 > input stream a 2 r a 2 r 0 a r a r 0 a 0 r a 0 r no. registers = (a n) (n r) no. KCMs = (a r) + + output stream

14 Outline Review of multiprocessor-based solution for Synthetic Aperture Radar (SAR) Proposed FPGA-based deep-pipeline solution for SAR An initial comparison of multiprocessor-based and FPGA-based solutions for SAR A framework for minimizing power consumption of deep pipelines based on signal activity transformations Summary

15 Example SAR Scenarios The following sets of application parameters define three SAR scenarios Application Parameters Simple Medium Difficult δ 2.5 (resolution, m) v (velocity, m/s) The following radar parameters are assumed for all scenarios Radar Parameters R (range, m) R s (range swath, m) λ (wavelength, m) Parameter Values 00,000 20,000.03

16 Computational Parameters for Three Scenarios Computational Parameters Simple Medium Difficult n 0,000 20,000 40,000 (no. range bins) r,024 2,048 4,096 (range ker. size) a 375,500 6,000 (azim. ker. size) Q (M samples/sec)

17 Comparison of Multiprocessor-based and FPGA-based Approaches for Three Scenarios Computational Approach Simple Medium Difficult Multiprocessor DSPs: = 4 Mem: = 35 MB DSPs: 3 + = 24 Mem: 4 +,080 =. GB DSPs: = 5 Mem: ,640 = 8.7 GB FPGA Taps: M Taps: 3.M Taps: 24 M Regs: 3.75 M Regs: 30 M Regs: 240 M The multiprocessor approach requires complex interconnection network plus significant RAM The FPGA approach only needs simple systolic connections among FPGAs Based on SHARC 2060 DSPs and assumes fast (FFT-based) convolutions

18 Outline Review of multiprocessor-based solution for Synthetic Aperture Radar (SAR) Proposed FPGA-based deep-pipeline solution for SAR An initial comparison of multiprocessor-based and FPGA-based solutions for SAR A framework for minimizing power consumption of deep pipelines based on signal activity transformations Summary

19 Power Consumption Model input stream W Deep Pipeline W output stream a 0 c 0 input signal activities a a 2 c c 2 P avg = P leak + V 2 2 f W i= 0 a i c i M

20 Measured and Predicted Power Consumption for FIR Filter on Xilinx 4036 Power (W) 4.2 S S2 S3 4.0 S4 S5 S6 3.8 S7 S8 S9 3.6 S0 S S2 3.4 S3 S4 P 3.2 P2 P3 P4 3.0 P5 P6 P7 2.8 P8 P9 P0 2.6 P P2 P3 2.4 P4 all measured Data Sets T. Osmulski, et al, A Probabilistic Power Prediction Tool for the Xilinx 4000-Series FPGA, Proceedings of The 5 th International Workshop on Embedded/Distributed HPC Systems and Applications (EHPC 2000), in Lecture Notes in Computer Science, May 2000, pp

21 Using Activity Transformations to Minimize Power Consumption Some input lines are hot (high capacitance) other input lines are cold (low capacitance) May be possible to apply linear transformation to input data to appropriately match input line activity vector to capacitance vector input stream a a T Deep Pipeline Assume Power Model P(a ) T - output stream Assuming activity vector a is known or estimated, determine transformation T to minimize power consumption of deep pipeline: Min {P(T(a))} T

22 Summary An FPGA-based approach was proposed as an alternative to the traditional multiprocessor approach for SAR processing The proposed FPGA-based approach looks promising in terms of inherent hardware complexity, but is probably not practical for implementation with currently available FPGA parts The proposed FPGA-based approach is applicable to other multi-phased embedded radar applications (e.g., STAP Space Time Adaptive Processing) A framework was proposed for minimizing power consumption for a class of FPGA designs based on input signal activity transformations