AN ENTROPY BASED GENETIC ALGORITHM TO SIMULTANEOUSLY MINIMIZE AREA AND WIRELENGTH FOR VLSI FLOORPLANNING PROBLEM

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1 International Journal of Advanced Research in Engineering and Technology (IJARET) Volume 9, Issue 6, November-December 2018, pp , Article ID: IJARET_09_06_004 Available online at ISSN Print: and ISSN Online: IAEME Publication AN ENTROPY BASED GENETIC ALGORITHM TO SIMULTANEOUSLY MINIMIZE AREA AND WIRELENGTH FOR VLSI FLOORPLANNING PROBLEM Leena Jain Associate Professor Global Institute of Management and Emerging Technologies, Amritsar, India Amarbir Singh Research Scholar, I. K. Gujral Punjab Technical University, Jalandhar, India ABSTRACT Due to the exponential increase in number of components on a VLSI (Very Large Scale Integration) chip over the years, there is a need to develop automated algorithms to decide the relative positions of circuits on a chip. In order to improve the performance of a chip, it is essential to deal with multiple objectives including area and wire length during the floor planning phase. Genetic Algorithms can be effectively used for multi objective optimization to generate optimal floor plans. In this paper, to solve the floor planning problem entropy based genetic algorithm is proposed to minimize area and wire length simultaneously using a heuristic placement strategy. The heuristic placement strategy helps in deciding the positions of rectangular modules on a chip. Microelectronics Centre of North Carolina (MCNC) benchmarks circuits are used to test the performance of our algorithm. Experimental results show that our algorithm can generate competitive solutions in comparison with various techniques proposed in literature for outline-free floor plans. Keyword Head: Floor planning, Entropy, Genetic algorithm, Wire length. Cite this Article: Leena Jain and Amarbir Singh, An Entropy Based Genetic Algorithm to Simultaneously Minimize and Wire length for VLSI Floor planning Problem International Journal of Advanced Research in Engineering and Technology, 9(6), 2018, pp INTRODUCTION A floor plan is a rectangular dissection which describes the relative placement of electronic modules on the chip. In the design of VLSI circuits, floor planning helps to determine the topology of layout and this problem is known to be NP-hard (Non-Deterministic Polynomialtime Hard). The solution space of this problem increases exponentially with the increase in number of modules in a circuit. Due to this it becomes very difficult to find the optimal solution by exploring the global solution space [1]. This problem has received much attention 30 editor@iaeme.com

2 Leena Jain and Amarbir Singh of researchers in recent years due to its usefulness and complexity. As the number modules are increasing day by day due to the improvement in integration technology, floor planning becomes a critical step in the process of VLSI physical design process. Floor planning consists of finding the optimal order of placement of modules so that dead space and wire length can be minimized and there are no module overlaps [2]. In this paper Entropy Based Genetic Algorithm is proposed to solve the VLSI floor planning problem for non-slicing floor plans and hard modules. In the proposed algorithm, concept of entropy is used in genetic algorithm to measure the diversity of population. The concept of entropy was given by one of the electrical engineer Claude Shannon and a recent research in this field reveals that it can be used in different areas like physics, biology, economics, computer science and engineering etc. The entropy represents a measure of uncertainty in random variable or random function. In other words, entropy represents a function which endeavors to illustrate its unpredictability. Entropy is maximum, when the distribution of random variable is equal and it becomes minimum, when each random variable has unequal probability. Entropy of random variable Z with a probability distribution P(Z) is maximum, when all the probabilities are same, it can be represented mathematically as below [3]. = (1) Where, K is a positive constant. Recently, various stochastic optimization algorithms, such as Simulated Annealing (SA), Genetic Algorithm (GA), Artificial Neural Networks (ANN) and tabu search have been used to solve complex problems. In the past, numbers of heuristic and met heuristic algorithms have been used to solve this problem. Genetic algorithm (GA) is a commonly used global search technique based on the survival of the fittest strategy. GA has been used effectively in the past to solve non-slicing VLSI Floor planning problem [4]. It has been proved that GA is an effective method for solving NP-hard optimization problems, so due to this reason GA has been applied on VLSI floor planning problem in our research. We have also used the concept of information entropy as a measure of diversity of each population into the process of GA to solve the problem of falling into a local optimal solution. To resolve the problem of local optimal solution Renyi s entropy is used in this paper. It ensures that crossover and mutation operators of genetic algorithm generate a generation with different population. Mathematically Renyi s entropy over a probability distribution P = P1, P2, P3,Pn is defined as = (2) Where α > 0 and α 1. So with the help of Renyi s entropy a new entropy based algorithm is proposed to find an optimal solution to the VLSI floor planning problem using the outline free constraints with the objective of minimizing the dead space and wire length. In our work we have purposed an algorithm based on heuristic placement strategy and Genetic Algorithm (GA) to solve the VLSI floor planning problem with the objective of minimizing area (dead-space) and wire length for non-slicing floor plans with hard modules. The proposed algorithm is tested for outline-free floor planning. Rest of the paper is organized as follows. Preliminaries to VLSI floor planning problem are discussed in section 2. In section 3, related work done by different researchers in past is given. Heuristic placement strategy and entropy based genetic algorithm is discussed in detail in section 4. Experimental results for outline free floor planning benchmark circuits are presented in section 5. Finally, some concluding remarks are given in section editor@iaeme.com

3 An Entropy Based Genetic Algorithm to Simultaneously Minimize and Wire length for VLSI Floor planning Problem 2. PRILIMINARIES 2.1. Floor plan Representation There are basically two floor plan layout structures slicing and nonliving. Any floor plan is sliceable if its rectangular dissection can be obtained by recursively dividing rectangles into smaller rectangles until each non-overlapping rectangle is invisible. So such floor plans which are not sliceable are called non-sliceable floor plans. The slicing floor plan is less useful than non-slicing floor plan, as it can be used to solve the floor planning problems with rather limited scope [5]. Different representations of non-slicing floor plan have been proposed in recent years: Corner Block List (CBL) representation [6], Sequence Pair (SP) representation [7], Bounded Slicing Grid (BSG) representation [8], O-tree representation [9], Transitive Closure Graph (TCG) representation [10], B* tree representation [11] [12] etc. Further details of the above mentioned representations can be found in literature [13]. Literature [14] introduces integer coding representation, which is simple, effective and quite suitable for floor planning problem, due to these advantages the integer coding representation has been adopted in this research work. According to this representation modules can be represented in the format of < V1, V2,,Vi,, Vn>, where 1 Vi n. Now Vi = j implies that the i-th module is to be placed at j-th position. After that a heuristic approach is used to adjust the modules while taking both their shapes and directions into consideration. In this paper, an integer coding representation is used but it only contains the order of modules. Information about shape, position and direction of the modules is not included in the representation Problem Statement Given a rectangular region with width W and height H, a set of modules M = { r1, r2, r3,..., rm}, in which module riis a rectangular block with fixed width wiand height hi (hard module) and given a net list N specifying interconnections between the modules in M, the problem is to find a packing of all the modules into the rectangular region P, such that they meet the following conditions: 1) No module can be aligned in a diagonal position; it must be placed parallel to the coordinate axis. 2) All modules must lie inside the rectangular region and overlapping of one module with any other module is not allowed. 3) A module may be rotated by 90 before its placement Given M and N, goal of the floor planning problem is to find a floor plan F such that a cost function is minimized [15]. The cost of a floor plan F, cost (F), consists of two parts, one is the area, area (F), which is measured by the smallest rectangle that encloses the floor plan and the other is wire length (F), which is the wire length of all the nets specified by N or the interconnection cost between various modules. The wire length of a net is calculated by the half perimeter of the minimal rectangle in the floor plan, which encloses the centers of the modules connected by the net. Now the cost function can be defined as follows: =!_ +1 %&'()!_% Where w is a weight assigned for primary objective related to area, w [0, 1]. As we have to simultaneously minimize area and wire length, value of w is taken as 0.5. The norm_area and norm_wire are the minimal area and the minimal wire length cost of the problem respectively. This kind of cost function has been adopted from [16]. Since we do not know norm_area and norm_wirein practice, estimated values are used. (3) 32 editor@iaeme.com

4 Leena Jain and Amarbir Singh 3. RELATED WORK In the context of circuit design, floor planning is the process of placing circuit modules of arbitrary sizes and dimensions on a given layout area with an objective of minimizing area and wire length between the modules and this problem has been tackled by using various approaches in literature. Iterative approaches are most popular for optimizing VLSI floor plans, commonly used iterative approaches are Simulated Annealing (SA), Genetic algorithm (GA) and Particle Swarm Optimization (PSO). A brief literature review of these popular approaches that have been used to address VLSI floor planning problem is given here. Chen et al. (2006) [17] studied two types of modern floor planning problems: 1) fixedoutline floor planning and 2) bus-driven floor planning (BDF). This floor planner used B*- tree floor plan representation based on fast three-stage Simulated Annealing (SA) scheme called Fast-SA in order to solve multi objective VLSI Floor planning problem. Maolin Tang et al. (2007) [18] proposed a Mimetic Algorithm (MA) for a non-slicing and hard-module VLSI floor planning problem. This MA is a hybrid genetic algorithm that uses an effective genetic search method to explore the search space and an efficient local search method to exploit information in the search region. Further the work on optimization using genetic algorithm was carried out by Pradeep Fernando et al. (2008) [19] they proposed a multi-objective genetic algorithm for floor planning that simultaneously minimizes area and total wire length. The proposed genetic floor planner is the first to use non-domination concepts to rank solutions and Jianli Chen et al. (2010) [20] described that hybrid genetic algorithm (HGA) uses an effective genetic search method to explore the search space and an efficient local search method to exploit information in the search region. Particle Swarm Optimization (PSO) [1] has been used apart from Genetic Algorithm and Simulated Annealing for optimization of VLSI Floor planning problem. 4. WORKING OF PROPOSED ALGORITHM 4.1. Heuristic Placement Strategy The module sequences for placement will be generated during the creation of population for genetic algorithm, and some rules are needed to convert modules sequence to two dimensional floor plan. Each module sequence will be converted into a floor plan according to the rules listed below: 1. Place the corresponding module of first element in the sequence to the left bottom corner. Pivot points are identified on the introduction of every module. 2. For each valid pivot point, the next module in sequence is placed on the chip in both length and Width wise orientation and area of the resulting rectangular casing is noted. The pivot point, which gives the smallest enclosing rectangle, is selected. As shown in Fig 1 (A, B, C, D) module 2 is placed in both Width and length wise orientation for all the pivot points and the resulting wastage is highlighted in the figure. 3. The algorithm needs to check that the newly placed module does not overlap with the boundary of the rectangular chip or with the modules placed earlier before the floorplan is accepted as valid. 4. The latter step is repeated for all the remaining modules in the sequence editor@iaeme.com

5 An Entropy Based Genetic Algorithm to Simultaneously Minimize and Wire length for VLSI Floor planning Problem Figure 1 (A) Placement of module 2 width wise at pivot point 1 (B) Placement of module 2 lengthwise at pivot point 1 (C) Placement of module 2 width wise at pivot point 2 (D) Placement of module 2 lengthwise at pivot point Entropy Based Genetic Algorithm Genetic algorithm does not guarantee to find an optimal solution, but the past experience shows that genetic evolution based approach is very useful in solving VLSI problems in an efficient manner [21].A genetic algorithm (GA) is a stochastic optimization search approach proposed by Holland in It is based on the natural selection and evolutionary genetic mechanisms. A genetic algorithm traverses the entire solution space utilizing a population consisting of a set of chromosomes through the survival of the fittest principle, which implies merging of a structured yet randomized information exchange. Different steps in genetic algorithm are Selection, Crossover and Mutation. Crossover is applied on two parent chromosomes that are selected to produce an offspring. The newly generated child chromosomes inherit some characteristics from its parents. The overall working of this operator is quite similar to the process of natural evolution. In the proposed entropy based genetic algorithm, Modified One Point Ordered Crossover Operator (MOOC) has been used. This crossover operator is influenced from one point crossover operator and ordered crossover operator [16]. The fitness of a floor plan (Individual) F is defined as follows. +,-.= (4) / 0( Where cost (F) is the cost of floor plan F defined in (3). One of the major problems with genetic algorithm is that it may fall into a local optimal solution during the evolution process. Sometimes the count of similar chromosomes starts to rise rapidly in a population and in such a situation mutation operator fails to maintain the 34 editor@iaeme.com

6 Leena Jain and Amarbir Singh diversity of the population. In this paper an Entropy Based Genetic Algorithm is used to escape from the trap of above said problem. In our approach, Entropy Based Intelligent Genetic Algorithm (EBIGA) proposed in literature [16] has been used to measure the diversity of the chromosome population in every generation and the low diversity population is improved with the help of Renyi s entropy. 5. EXPERIMENTAL RESULTS In this part, an experiment is carried out one for outline-free floor planning using hard modules and MCNC benchmark circuits have been used to test and compare the results of experiment. Characteristics of MCNC benchmark circuits are shown in Table 1. MATLAB R2015a is used to implement and run the programs on a machine with an intel CPU running at 1.70 GHz and 4 GB RAM. In our experiment, the objective is to minimize the wastage area (dead-space) and wire length simultaneously. Algorithm is run for 50 times in order to obtain best possible values for area and wire length. The fitness function is described in Eq. (3) and the parameters of the EBIGA are set as follows: The value of w in Eq. (3) is set to 0.5, population size for genetic algorithm varies for different benchmark circuits, crossover probability (Cp) are set as 0.8 and mutation probability (Mp) is 0.1. In the implementation of EBIGA, in order to calculate renyi entropy the value of α is taken as 7 and ln(α) i.e. ln(7) =1.946 is used as the threshold value. The value of control parameter (cp) is different for every benchmark circuit, as the number of modules is different in each benchmark circuit. Higher value of cp means higher probability of doing improvement. Table 1 The Chracteristics of MCNC benchmark circuits Benchmark Circuit #Cells #Nets Cell area (mm 2 ) MCNC Apte Xerox Hp ami ami Table 2 contains the best values produced by our algorithm during simultaneous minimization of area and wire length for MCNC benchmark circuits. In order to show the efficiency of the algorithm for outline-free floor planning with the objective of minimizing area and wire length, we have compared the results with Transitive Closure Graph (TCG) [22], O-tree [23], Enhanced O-tree [24],Corner Sequence (CS) [25], Genetic Algorithm [26], Evolutionary Search GA [27], Fast SA [17], Discrete-PSO [1] in Table 3. Results of these floor planning algorithms are taken from their published reports in literature. EBIGA produces better results than almost sixty percent of other algorithms proposed in literature by different researchers. It has been observed that proposed algorithm performs better for problems with large number of modules in comparison with other approaches. Comparison of dead-space percentage is given in Table editor@iaeme.com

7 An Entropy Based Genetic Algorithm to Simultaneously Minimize and Wire length for VLSI Floor planning Problem Table 2 Results of EBIGA with the objective of minimizing area and wire length simultaneously (w=0.5) MCNC Benchmark (mm2) Wire length(mm) DS(%) apte xerox Hp ami ami Table 3 Performance Comparison for outline-free floor planning with the objective of minimizing area and wire length simultaneously on MCNC benchmark circuits (w=0.5) Circuit apte xerox hp ami33 ami49 Algorithm (mm 2 ) WL (mm) (mm 2 ) WL (mm) (mm 2 ) WL (mm) (mm 2 ) WL (mm) (mm 2 ) WL (mm) EBIGA TCG O-tree Enhanced O-tree CS Genetic Algorithm Evolutionary Search GAGA Fast SA Discrete-PSO Table 4 Dead Space Comparison for Classical (outline-free) floor planning with the objective of minimizing area and wire length simultaneously on MCNC benchmark circuits (w=0.5) Algorithm Dead Space Percentage for Various Benchmark Circuits Apte xerox hp ami33 ami49 EBIGA TCG O-tree Enhanced O-tree CS Genetic Algorithm Evolutionary Search GA Fast SA Discrete-PSO Average CPU time comparison of EBIGA with evolutionary search GA is given in figure 2. It show that the proposed technique takes less time for problems with small number of 36 editor@iaeme.com

8 Leena Jain and Amarbir Singh modules and takes more time for problems having large number of modules than its counterpart Evolutionary Search GA EBIGA 0 apte xerox hp ami33 ami49 Figure 2 Average CPU time (sec) comparison on MCNC benchmark circuits Figure 3 shows the simulation result for ami33 benchmark circuit produced by our algorithm, it is the best result produced during the execution of entropy based genetic algorithm 50 times. Figure 4 shows the convergence graph for the ami33 benchmark circuit and it describes the minimization of area values during the execution of 50 generations of EBIGA. Figure 3 Simulation result on MCNC ami33 Convergence Graph - ami Iterations EBIGA Figure 4 Convergence graph for MCNC ami editor@iaeme.com

9 An Entropy Based Genetic Algorithm to Simultaneously Minimize and Wire length for VLSI Floor planning Problem 6. CONCLUSION In this paper, an entropy based genetic algorithm is presented for minimizing area and wire length simultaneously for VLSI floor planning problem. The proposed algorithm made use of heuristic placement strategy and entropy based genetic algorithm to explore global search space in an efficient way. Different experiments show that our method achieves substantially improved success rate than most of other algorithms for outline-free floor planning. Results for EBIGA show that various benchmark circuits can be processed in a reasonable time. It has been observed that more attention should be given to carry out optimization at other stages of physical design process of integrated circuits, such as Partitioning and Placement, so that more efficient and compact chips can be produced. ACKNOWLEDGEMENT Authors are thankful to the I.K. Gujral Punjab Technical University, Kapurthala for the support and motivation for research. REFERENCES [1] Guolong Chen, WenzhongGuo, Yuzhong Chen: A PSO-based Intelligent Decision Algorithm for VLSI Floor planning, Soft Computing Methodologies and Appl. 14(12), pp (2009). [2] Jianli Chen, Wenxing Zhu, and M. M. Ali, A Hybrid Simulated Annealing Algorithm for Nonslicing VLSI Floor planning, IEEE transactions on systems, man and cybernetics part c: applications and reviews, VOL. 41, NO. 4, 2011, [3] Rongxi Zhou, RuCai, Guanqun Tong: Applications of Entropy in Finance: A Review. Entropy, pp (2013). [4] Amarbir Singh, Leena Jain, Optimization of VLSI Floor planning Problem using a Novel Genetic Algorithm, International Journal of Computer Science and Information Security, Volume 14, No. 10, October 2016, pp [5] Wang, T.C.,Wong, D.F.: An Optimal Algorithm for Floorplan Optimization. In: DAC 90: Proceedings of the 27th ACM/IEEE Design Automation Conference, pp ACM, New York (1990). [6] X. L. Hong, G. Huang, Y.C. Cai, J. C. Gu, S. Q.Dong, C. K. Cheng, and J. Gu: Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floor plan. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp ACM/IEEE (2000). [7] H. Murata, K. Fujiyoshi, S. Nakatake, and Y.Kajitani: VLSI Module Placement Based on Rectangle-Packing by the Sequence-Pair. IEEE Transactions CAD, 15(12), pp ieee (1996). [8] S. Nakatake, K. Fujiyoshi, H. Murata, and Y.Kajitani: Module Packing Based on the BSG-Structure and IC Layout Applications. IEEE Transactions on CAD, 17(6), pp IEEE (1998). [9] P. N. Guo, C. K. Cheng, and T. Yoshimura: An O-tree Representation of non-slicing Floor plan and its Applications. In: Proceedings of the 36th ACM/IEEE conference on De-sign Automation, pp New Orleans, Louisiana, United States (1999). [10] J. M. Lin, and Y. W. Chang: TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floor plans. In: Proceedings of the 38th Design Automation Conference, pp Las Vegas, USA (2001) editor@iaeme.com

10 Leena Jain and Amarbir Singh [11] Chang YC, Chang YW, Wu GM: B*-tree: A New Representation for non-slicing Floor-plans. In: Proceedings of the37th conference on design automation, pp ACM, Los Angeles, California (2000). [12] Tung-Chieh Chen, and Yao-Wen Chang: Modern Floor planning Based on B*-Tree and Fast Simulated Annealing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 4, pp (2006). [13] Leena Jain, Amarbir Singh, Non Slicing Floorplan Representations in VLSI Floor planning: A Summary, International Journal of Computer Applications ( ) Volume 71 No.15, June 2013, [14] B. H. Gwee, and M. H. Lim: A GA with Heuristic Based Decoder for IC Floor planning. INTEGRATION: The VLSI Journal, 28(2), pp (1999). [15] Jianli Chen, Wenxing Zhu, and M. M. Ali: Hybrid Simulated Annealing Algorithm for Nonslicing VLSI Floor planning. IEEE transactions on systems, man and cybernetics part c: applications and reviews, VOL. 41, NO. 4, pp (2011). [16] Amarbir Singh, Leena Jain, (2018), VLSI Floor planning Using Entropy Based Intelligent Genetic Algorithm, Springer Nature, CCIS 805, pp [17] Chen, T.C., Chang, Modern floorplanning based on B*-tree and fast simulated annealing, IEEE Trans. CAD 25(4), 2006, pp [18] Maolin Tang and Xin Yao, A Memetic Algorithm for VLSI Floor planning IEEE transactions on systems, man, and cybernetics part b: cybernetics, VOL. 37, NO. 1, 2007, pp [19] P. Fernando and S. Katkoori, An elitist non-dominated sorting based genetic algorithm for simultaneous area and wire length minimization in vlsi floo planning, IEEE Intl. Conf. on VLSI Design, 2008, pp [20] Jianli Chen, Wenxing Zhu, A Hybrid Genetic Algorithm for VLSI Floor planning, International Conference on Intelligent Computing and Intelligent Systems (ICIS), IEEE, 2010, pp [21] De-Sheng Chen, Chang-Tzu Lin, Yi-Wen Wang, Ching-Hwa Cheng: Fixed-outline floorplanning using robust evolutionary search. Engineering Applications of Artificial Intelligence, pp Elsevier Ltd (2007). [22] J. M. Lin, and Y. W. Chang: TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Flooplans. In: Proceedings of the 38th Design Automation Conference, pp Las Vegas, USA (2001). [23] Guo, P.N., Cheng, C.K., Yoshimura, T.: An O-tree representation of non-slicing floor plan and its applications. In: DAC 99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference, pp ACM, New York (1999). [24] Y. Pang, C. K. Cheng, and T. Yoshimura: An Enhanced Perturbing Algorithm for Floor plan Design using the O-tree Representation. In: Proceedings ISPD, pp (2000). [25] Lin, J.M., Chang, Y.W., Lin, S.P.: Corner sequence-a P-admissible floor plan representation with a worst case linear-time packing scheme. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 11(4), (2003). [26] Tang, M., Sebastian, A.: A genetic algorithm for VLSI floor planning using O-tree representation. In: Applications on Evolutionary Computing. Lecture Notes in Computer Science, vol. 3449, pp Springer, Berlin/Heidelberg (2005). [27] e-sheng Chen, Chang-Tzu Lin, Yi-Wen Wang, Ching-Hwa Cheng: Fixed-outline floorplanning using robust evolutionary search. Engineering Applications of Artificial Intelligence, pp Elsevier Ltd (2007) editor@iaeme.com