Abstraction and Optimization of Consistent Floorplanning with Pillar Block Constraints

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1 Abstraction and Optimization of Consistent Floorplanning with Pillar Block Constraints Ning FU, Shigetoshi NAKATAKE, Yasuhiro TAKASHIMA, Yoji KAJITANI School of Environmental Engineering, University of Kitakyushu 1-1 Hibikino, Wakamatsu-ku, Kitakyushu-city, Fukuoka , Japan {funing, nakatake, takasima, kajitanienv.kitakyu-u.ac.jp Abstract We aim at developing floorplan method, a key in topdown design of system LSIs, and provide floorplan abstraction available in high level design. We introduce pillar blocks to represent a frame of a chip layout and propose how to evaluate the chip before the floorplanning with physical dimension. The frame by the pillar blocks is employed as constraints in optimizing block placement. The experiments to MCNC benchmarks showed that the abstraction is faithful to the physically optimized block placement with respect to the chip area and the wire-length. I. INTRODUCTION Intensive growth of market of system LSIs is requesting the rapid and robust designs such as topdown design style of good efficiency, based on usage of soft and hard macro IPs. While the high level design must steadily take physical information of the chip into consideration, since the wire delay is being dominant in the signal delay as silicon technology progressing into deep sub-micron. The physical information, that is, the chip layout is obtained by floorplanning at the early stage. The floorplanning should have a variety according to usage in each design stage, and the variety should be appropriate to abstractive objects of a circuit. This paper carries two issues: one is to abstract a floorplan so as to be available in high level design. In stage of HW/SW co-design, for example, a designer hopes to seek an optimal chip architecture from a lot of candidates. This means the floorplanning in the stage should be rapid enough to take a role as a function incorporated into architecture optimization. A trend of recent works of floorplanning [1, 2, 3, 4, 5, 6] is based on optimization by stochastic searches (e.g. simulated annealing), which usually take much time. In this point, the existing floorplannings have a fatal drawback. The other issue is to, in the physical design stage, optimize the layout consistently with the abstractive floorplan in the high level design. The lack of the consistency causes the design feedback, which results in a long term design. This paper is presenting one solution for these issues, focusing partitioning and block placement in topdown design style. An input circuit may consist of objects of variously abstractive states, but the partitions are naturally determined by the functions. Otherwise we apply a min-cut based partitioning to the circuit. Thus, partitioning information is available at whichever design stage. At first, we abstract a floorplan by using the information. The key is to introduce pillar blocks which form a frame of a chip. Pillar blocks have the following three features. (i)they exist along the cut-line of partition. (ii) They are dominant in determining the width and the height of the chip. (iii) They bring the partitioning information into the following block placement. This paper provides a heuristics (called pillar clustering) to extract pillar blocks from a circuit by looking into connections, partitions and influence on the width and the height of the chip. We also give an abstraction of floorplan induced by pillar blocks. Next, we present a way to convey the abstractive feature of floorplan to block placement. Nakatake et. al.[7] propose consistent floorplanning, which gives the concept and a way to do block placement consistently with the preceding partitioning. They are introducing super hierarchical constraints induced by the feature of the partitioning. According to the concept, the feature of pillar blocks is transferred into constraints (called pillar constraints). The constraints are represented by the ABLR-relations ( above, below, left-of, right-of ) of the pillar blocks and the other blocks. The ABLR-relations are formulated on a sequence-pair known as a rectangle packing method [2]. We implemented a prototype that is composed of pillar clustering and block placement under pillar constraints, and applied it to MCNC benchmarks. We showed the promising results: the floorplan abstraction induced by pillar blocks was almost faithful to the block placement after optimization with respect to the chip area and the wire-length. The rest of the paper is organized as follows. Section 2 is for describing the concept of consistent floorplanning presented in [7]. Section 3 is devoted to sketch the feature of pillar blocks and the floorplan abstraction. Section 4 is for describing pillar constraints and optimization under the constraints. Section 5 is devoted to the experiments to compare the abstraction with the block placement. Section 6 is for conclusions and future works. II. CONSISTENT FLOORPLANNING [7] introduces the concept consistent floorplanning on the Sequence-Pair [2] that takes the feature of the partition. The main frame is based on the understanding that circuit partitioning is always connectivity-oriented bi-partition and hierarchical, while the Sequence-Pair is a non-hierarchical datastructure of general floorplans. The idea is to convey the feature of partition into the floorplanning as a constraint. A. Sequence-Pair Based Representation Given a placement of n blocks, gridding[2] is a procedure to determine a pair of sequences (α, β), called the Sequence-Pair (SP). An equivalent description of SP is as follows. α and β are defined as the sequences satisfying the property that all blocks can be removed one after another along α (β) in the above-left (below-left) direction without touching the remaining blocks. Consider that the circuit is partitioned into four clusters, say, A, B, C, and D under the condition that each is assigned to

2 )? = > * special peripherals to touch. Then the possible cluster placements are depicted in five configurations as shown in Fig. 1 (a), (b), (c), (d) and (e). In the SP representation, each pair of clusters is given just one ABLR-relation. However, in each figure, we may observe two ABLR-relations for a pair of clusters. For example, in the figure (a), B is above C, and B is right-of C. It leads alternative SP s. The corresponding SP s are (a) (b) (c) (d) (e) α = (ABCD) or (ACBD), β = (CDAB), α = (ABCD), β = (CDAB) or (CADB), α = (ABCD) or (ACBD), β = (CDAB) or (CADB), α = (ACBD), β = (CDAB) or (CADB), α = (ABCD) or (ACBD), β = (CADB). (1) = >? Another example is: a(b cd) means (abcd), (acbd) and (acdb). To list all the constraints represented by this single formula, they are α 1 (a) < α 1 (b), α 1 (a) < α 1 (c), α 1 (a) < α 1 (d), and α 1 (c) < α 1 (d). With this notation, Eq. (1) is mapped to a formula; α = A(B C)D, β = C(D A)B. (2) This formula is called super hierarchical constraint. SP BLK satisfying the constraint is said to be feasible. Obviously, in block placement, The constraint of blocks in the same cluster X is x 1 x 2 x i. For example, given clusters as A = {a 1, a 2, B = {b 1, b 2, C = {c 1, c 2 and D = {d 1, d 2, SP BLK = (a 1 a 2 b 1 b 2 c 1 c 2 d 1 d 2, c 2 c 1 d 2 a 2 a 1 d 1 b 1 b 2 ) is feasible under (A(B C)D, C(D A)B), that is, ((a 1 a 2 )(b 1 b 2 c 1 c 2 )(d 1 d 2 ), (c 1 c 2 )(d 1 d 2 a 1 a 2 )(b 1 b 2 )). Note that the shape of cluster D is not a rectangle as shown in Fig. 2.? = > Fig. 2. An example of block placement under α = (A(B C)D), β = (C(A B)D). Fig. 1. Possible placements corresponding to four clusters A B. Super Hierarchical Constraints In a hierarchical placement system, each cluster is a mass of blocks. Given an SP of cluster placement, consider a translation from the SP to that of a block placement. Let blocks in A, B, C, and D be {a i, {b i, {c i, and {d i, respectively. SP CLT and SP BLK denote SP s of cluster and block placement, respectively. In a simple translation, the orders of blocks in SP BLK are inherited from those of clusters in SP CLT. For example, SP CLT (ABCD, CDAB) implies the SP BLK ; α = (... a i... b i... c i... d i...), β = (... c i... d i... a i... b i...). However, there is a variation of SP CLT s as shown in Eq. (1) which is induced by the circuit partitioning. Furthermore, the above translation limits shape of each cluster to be rectangle. To take such a variation of SP CLT s into consideration as well as to release shape of clusters from a rectangle, [7] introduces the super hierarchical constraint. In [7], a logical expression is introduced. The fact that a sequence is possible to be (abcd) or (acbd) is represented by the formula a(bc)d. Here, addition xy denotes a commutative relation that orders (xy) and (yx) are both feasible, while product xy non-commutative relation, that order (xy) is unique. Let us explain about the formula more in detail. Consider a sequence α. α 1 (x) is the inverse function, which returns an order of a block x in α. β 1 (x) is analogously defined. By definition, xy means α 1 (x) < α 1 (y), while x y does α 1 (x) < α 1 (y) or α 1 (x) > α 1 (y). The placement system is a heuristic search that generates feasible sequence-pairs, constructs the corresponding floorplans, evaluates them, and transforms one to another guided by simulated annealing. Then it outputs the best so far. III. PILLAR BLOCKS AND FLOORPLAN ABSTRACTION This section describes the feature of pillar blocks and the abstraction of floorplan with pillar blocks. In this paper, width and height of all blocks are fixed. A. The Feature of Pillar Blocks Given a set of blocks, four clusters A, B, C, and D are obtained by some bi-partitioning in the way such as [7]. We note that the resultant clusters and the shape of each block suggest some information of the frame of the chip layout. At first, we focus such blocks that are dominant in determining the shape of the chip. For example, a placement of 18 blocks is shown in Fig. 3. Let A = {1, 2, 3, 4, B = {5, 6, 7, a, b, C = {8, 9, c, d, D = {e, f, g, h, i. The width of this chip is determined by the length of path 3 4 a b g and the height is determined by 2 5 a c e. Next, let us consider the position of the block a which is a member of B. It is connected to 9, c, and f which belong to A, C, and D, respectively. Thus, a is expected to be located near to the cluster A, C, and D. From the observation, we focus the blocks of some features to induce the chip layout. Those blocks are called pillar blocks. Let us describe the above features in more details. Let I(x, P), called incident value, be the number of the nets such that each net connects x with a block in cluster P. In Fig. 3, I(a, A) = 0, I(a, B) = 1, I(a, C) = 2, I(a, D) = 1. A pillar block has the following three features: F1 It has higher incident value.

3 &? A # D > B % $ E C F2 It is placed around the boundaries between two clusters. F3 It exists on the semi-longest path of horizontal constraint graph or vertical constraint graph, which is used to calculate width or height of a chip, respectively. In Fig. 3, pillar blocks are 2, 3, 4, 5, a, b, c, e, and g.! " ' = Fig. 3. An example of the feature of pillar blocks in block placement Feature F1 and F2 ensure that the positions of pillar blocks induce a placement with less net length. Feature F3 ensures that the behavior of the pillar blocks dominates the size of chip. B. Extraction of Pillar Blocks In this section, it is described how to extract pillar blocks from given clusters. Assume that four clusters are given. The extension in more than four clusters may be possible, but it is omitted here for the space. First, four clusters A, B, C, and D are obtained in the similar way as [7].!!!!!! Fig. 4. Relative positions of nine clusters Next, re-configure the above four clusters into nine clusters C 11, C 21, C 31, C 12, C 22, C 32, C 13, C 23, and C 33, where the relative position of each cluster is shown in Fig. 4. Rules of the configuration are described in the following. C 22 A B C D, C 21 A B, C 23 C D, C 12 A C, C 32 B D, C 11 = A/(C 12 C 22 C 21 ), C 31 = B/(C 21 C 22 C 32 ), C 13 = C/(C 12 C 22 C 23 ), C 33 = D/(C 23 C 22 C 32 ). (3) Each cluster C i j should be configured in order to minimize the cut size. When the configuration finishes, C 12, C 21, C 22, C 23, and C 32 consist of only pillar blocks. The others do not have any pillar block. The clusters with pillar blocks are called pillar clusters. In the abstractive floorplan, the shape of each cluster is considered as a rectangle. For cluster C i j, let the width, height, area and the number of blocks be W(C i j ), H(C i j ), A(C i j ), and N(C i j ), respectively. The blocks in C 12 C 32 only have the horizontal relation to each other. And the blocks in C 21 C 23 only have the vertical relation to each other. So, the width and height of these clusters are defined as Eq.(4) H(x) W(C i2 ) = W(x) and H(C i2 ) = (i = 1, 3), N(C x C i2 x C i2 ) i2 W(x) H(C 2 j ) = H(x) and W(C 2 j ) = ( j = 1, 3). N(C x C 2 j x C 2 j ) 2 j (4) Then, it assumes that the shape of the other blocks C 22,C 11,C 13,C 31, and C 33 are square as follows W(C i j ) = H(C i j ) = A(C i j ), (5) where A(C i j ) = A(x). x C i j The width and height of each cluster must satisfy the following conditions. where max(w 1, W 2, W 3 ) min(w 1, W 2, W 3 ) δ W, max(h 1, H 2, H 3 ) min(h 1, H 2, H 3 ) δ H, W j = H i = 3 W(C i j ) ( j = 1, 2, 3), i=1 3 H(C i j ) (i = 1, 2, 3). j=1 From the observation of the above conditions, the size of each cluster can be controlled by δ W, δ H, and N(C 22 ). In this paper, those values are given as input parameters. They might be determined empirically. Next, we describe an algorithm, for the reconfiguration, called pillar clustering. procedure Pillar Clustering input : A, B, C, D, N(C 22 ), δ W, δ H output : C i j (1 i 3, 1 j 3) 1. Set C 11 = A, C 31 = B, C 13 = C, C 33 = D. 2. Sort all blocks in non-increasing order according to the sum of the incident values formulated as: I(x, Q), i f x P. Q Q P Choose N(C 22 ) blocks with the largest sum of the incident values and move these blocks to C Prepare eight lists of blocks L AB, L AC, L BA, L BD, L CA, L CD, L DB, and L DC, such that blocks of list L PQ are sorted in non-increasing order according to I(x, Q), x P. We define the operation of MOVE BLOCK from L AB (6) (7) (8)

4 to C 21 as moving the head block of L AB to C 21 and removing the block from the L AC too. Other MOVE BLOCK operations can be defined analogously. 4. Choose blocks one by one from the lists and move them to a cluster C 12, C 21, C 23 or C 32 as follows: Set the threshold K H and K W. Repeat a sub-procedure EXPAND H2W2 until max(h 1, H 2, H 3 ) min(h 1, H 2, H 3 ) δ H and max(w 1, W 2, W 3 ) min(w 1, W 2, W 3 ) δ W. If the times of repeat of expanding H2 is more than K H, then δ H = 2 δ H, so does δ W. EXPAND H2W2: if(h 2 < W 2 ){ /* increase H 2 */ if(h 1 < H 3 ){ /* decrease H 3 */ if(a(c 33 ) < A(C 31 )){ /* decrease C 31 */ MOVE BLOCK from L BA to C 21. else { /* decrease C 33 */ MOVE BLOCK from L DC to C 23. else { /* decrease H 1 */ if(a(c 13 ) < A(C 11 ){ /* decrease C 11 */ MOVE BLOCK from L AB to C 21. else { /* decrease C 13 */ MOVE BLOCK from L CD to C 23. else { /* increase W 2 */ if(w 1 < W 3 ){ /* decrease W 3 */ if(a(c 33 ) < A(C 13 )){ /* decrease C 13 */ MOVE BLOCK from L CA to C 12. else { /* decrease C 33 */ MOVE BLOCK from L DB to C 32. else { /* decrease W 1 */ if(a(c 31 < C 11 )){ /* decrease C 11 */ MOVE BLOCK from L AC to C 12. else { /* decrease C 31 */ MOVE BLOCK from L BD to C 32. Let the number of all blocks and the number of all terminals be n and p, respectively. In algorithm pillar clustering, the complexity of each step is as follows: Step 1 needs that all blocks move into one of four clusters, thus O(n). In step 2, calculation of I(x, A), I(x, B), I(x, C), and I(x, D) takes the complexity O(np). Next, sorting all blocks is done in O(n log n). Thus, in this step, the complexity is O(npn log n). In step 3, for each list of blocks L PQ, sorting the blocks in non-increasing order according to I(x, Q), x P, takes O(n log n). In step 4, the complexity of selecting the block and moving it into the appropriate cluster is O(1), and these operations are iterated at most n times. Thus, the complexity is O(n). Therefore, the total complexity is O(np n log n). C. Floorplan Abstraction The width and height of the abstractive floorplan are max(w 1, W 2, W 3 ) and max(h 1, H 2, H 3 ), respectively. Let the coordinates of the left-bottom point of the cluster P be (X(P), Y(P)). The coordinates of each cluster are as follows: X(C i1 ) = X(C i2 ) = X(C i3 ) (i = 1, 2, 3); X(C 1 j ) ( j = 1, 2, 3) = x-coordinate of the left-most of the chip. Y(C 1 j ) = Y(C 2 j ) = Y(C 3 j ) ( j = 1, 2, 3); Y(C i3 ) (i = 1, 2, 3) = y-coordinate of the bottom-most of the chip. Each block exists at the center of the belonging cluster. IV. CONSISTENT OPTIMIZATION UNDER PILLAR CONSTRAINTS A. Pillar Constraints The feature of pillar blocks described in the previous section should be conveyed into block placement. Therefore, we configure certain constraints, for block placement, which are induced by the feature and the definition of pillar blocks. We call the constraints pillar constraints, and they are represented as a set of topologies between blocks. Pillar constraints consist of the following three constraints (super hierarchical, internal boundary, and path constraint). We expect the resultant placement as shown in Fig. 5, which includes the jagged boundaries between clusters.!!!!!! Fig. 5. An expected placement with jagged shape clusters 1. Super hierarchical constraint To avoid forming clusters like in Fig. 6, super hierarchical constraint is necessary. It is defined as follows:!!!!!! Fig. 6. An unexpected placement with S -shaped clusters without super hierarchical constraint (a) α = C 11 (C 13 C 22 C 31 )C 33 (C 12 C 21 )(C 23 C 32 ) (b) β = C 13 (C 11 C 22 C 33 )C 31 (C 12 C 23 )(C 21 C 32 ) 2. Internal boundary constraint

5 (a) x is not right-of y, for x C i j, y C i1 j (i = 1, 2, j = 1, 2, 3) (b) x is not below y, for x C i j, y C i j1 (i = 1, 2, 3, j = 1, 2) 3. Path constraint (a) x is above or below y, for x, y C 21 or x, y C 23 (b) x is left-of or right-of y, for x, y C 12 or x, y C 32 The above topological constraints can be replaced with constraints in terms of sequence-pair. M α and M β introduced in [7] are available on the constraint 1 since all constraints can be seen on α and β, independently. The entry of M α, called consistency index, is defined as m α (x, y) = 1, if only order (xy) is allowed in α. m α (x, y) = 1, if only order (yx) is allowed in α. m α (x, y) = 0, otherwise. The entry of M β is analogously defined. The constrain 2 and 3 can not be checked independently. They must be checked by α and β at the same time directly. B. Implementation with Simulated Annealing As well as recent works[3, 4, 5, 6] of block placement, we adopt a simulated annealing as a stochastic search. A design of a simulated annealing is, simply to say, to provide generation of an initial solution which meets pillar constraints, and to define a move to generate one solution after another as not violating the constraints (said to be feasible). An initial solution is constructed as shown in Fig. 4, that is, the sequence-pair is: α = C 11 C 12 C 21 C 22 C 13 C 31 C 23 C 32 C 33, β = C 13 C 12 C 23 C 22 C 11 C 33 C 21 C 32 C 31. Note that blocks in C 12, C 21, C 23 and C 32 must satisfy path constraints. Then, calculate the matrix M α and M β. Make two lists (list α and list β) of block pairs whose corresponding consistency index is 0. After that, our simulated annealing uses the following three moves which are the extension of moves provided in [2]: full-exchange: Choose a pair of blocks, which exists in both list α and list β, and exchange them in both α and β; half-exchange: Choose a pair of blocks from list α or list β, and exchange them in corresponding sequence; rotation: Choose a block, which is not in pillar cluster C 12, C 21, C 23 nor C 32, and rotate it by 90 degree. For each move, all three constraints must be checked. The time complexity of this checking is O(n), where n is the number of blocks. The results with respect to the chip area and the total net length are also shown in Table I and Table II, respectively. In Table I, A abst and A place correspond to chip area evaluated by the abstractive floorplan and that by the block placement, respectively. A pair of values within each parenthesis corresponds to the width and the height of the chip. TABLE II COMPARISON W.R.T TOTAL OF NET LENGTH: N abst AND N place ARE TOTAL NET-LENGTH OF FLOORPLAN ABSTRACTION AND BLOCK PLACEMENT, RESPECTIVELY. data N abst N place (N place N abst )/N place ami33 69,234 75, ami49 771, , In the almost cases, the differences between the abstractive floorplan and the block placement are about 2%. The differences are small enough to make use of the evaluation in high level design. Fig. 7 and 9 show the abstractive chip layout of ami33 and ami49, respectively. Fig. 8 and 10 show the resultant block placements. In these figures, the shade rectangles represent pillar clusters or pillar blocks. We are convinced that our abstraction of floorplan is faithful to the block placement. Furthermore, we observed the results from a point of view of the total net-length. In the abstraction, each block is located at the center of the cluster. The total net-length is the sum of a half-perimeters of bounding boxes of nets. The results are shown in Table II. N abst and N place are corresponding to the total net-length of the abstraction and the block placement, respectively. The differences are small enough, as well as those to chip area. The results encourage us to develop our concept further. VI. CONCLUDING REMARKS We provided floorplan abstraction to evaluate a chip in high level design. In the abstraction, we introduced pillar blocks to represent a frame of a chip layout and proposed how to extract the pillar blocks. Furthermore, we defined pillar constraints induced by the pillar blocks to impose on block placement. The experiments applying the algorithm to MCNC benchmarks showed the promising results, where the abstraction is faithful to the block placement. As future works, we will develop the algorithm with pillar blocks defined more generally, apply it to larger instances, and enhance it to be able to handle instances with soft blocks. ACKNOWLEDGMENT This work was supported in parts by funds from the Japanese Ministry of ECSST via Kitakyushu and Fukuoka knowledgebased cluster projects. V. EXPERIMENTS We implemented a prototype that consists of pillar clustering and block placement under pillar constraints. We experimented to demonstrate the comparison of the floorplan abstraction and the block placement. The input circuits and parameters of pillar clustering are shown in Table I. N(C 22 ) is set to be about 6% of the number of blocks. δ W and δ H are set to be the minimal width and height of all blocks, respectively. REFERENCES [1] D. F. Wong and C. L. Liu, A New Algorithm for Floorplan Design, Proc. 23rd Design Automation Conference pp , [2] H.Murata, K.Fujiyoshi, S.Nakatake and Y.Kajitani, VLSI Module Placement Based on Rectangle-Packing by the Sequence-Pair, IEEE Trans. on Computer-Aided Design of IC s and Systems, Vol.15 No.12 pp , 1996.

6 TABLE I COMPARISON W.R.T CHIP AREA: A abst AND A place ARE CHIP AREA BY FLOORPLAN ABSTRACTION AND BY BLOCK PLACEMENT, RESPECTIVELY. data N(C 22 ) δ W δ H A abst A place (A place A abst )/A place ami ,293,112 (1,202x1,076) 1,318,149 (1,281x1,029) ami ,126,435 (7,237x5,821) 42,223,104 (7,392x5,712) Fig. 7. Abstractive floorplan of ami33 Fig. 9. Abstractive floorplan of ami49 BLK[7] BLK[18] BLK[15] BLK[24] BLK[5] BLK[14] BLK[13] BLK[17] BLK[25] BLK[20] BLK[26] BLK[21] BLK[9] BLK[0] BLK[29] BLK[23] BLK[22] BLK[12] BLK[10] BLK[32] BLK[11] BLK[8] BLK[19] BLK[3] BLK[27] BLK[16] BLK[4] BLK[2] BLK[30] BLK[1] BLK[28] BLK[31] BLK[6] BLK[46] BLK[47] BLK[4] BLK[36] BLK[3] BLK[5] BLK[45] BLK[12] BLK[10] BLK[48] BLK[35] BLK[8] BLK[6] BLK[22] BLK[21] BLK[1] BLK[2] BLK[37] BLK[39] BLK[7] BLK[40] BLK[20] BLK[38] BLK[29] BLK[11] BLK[34] BLK[19] BLK[41] BLK[13] BLK[23] BLK[33] BLK[28] BLK[42] BLK[24] BLK[18] BLK[9] BLK[0] BLK[15] Fig. 8. Block placement of ami33 BLK[32] BLK[31] BLK[26] BLK[27] BLK[17] BLK[30] BLK[25] BLK[44] BLK[16] BLK[14] BLK[43] [3] S.Nakatake, H.Murata, K.Fujiyoshi, Y.Kajitani, Module Packing Based on the BSG-Structure and IC Layout Applications, IEEE Trans. on Computer Aided Design of IC s and Systems, Vol.17, No 6, pp , [4] P.Guo, C.Cheng and T.Yoshimura, An O-Tree Representation of Non-Slicing Floorplan and Its Applications, Proc. 36th Design Automation Conference, pp , [5] K. Sakanushi and Y. Kajitani, The Quarter-State Sequence (Q-Sequence) to Represent the Floorplan and Applications to Layout Optimization, Proc. of IEEE Asia Pacific Conference on Circuits and Systems 2000, pp , Fig. 10. Block placement of ami49 Corner Block List, Proc. of Asia South Pacific Design Automation Conference [7] S. Nakatake, Y. Kubo and Y. Kajitani, Consistent Floorplanning with Superhierarchical Constraints Trans. on Computer-Aided Design of IC s and Systems, Vol.21, No.1, pp.42-49, [6] Y.Ma, S.Dong, X.Hong, Y.Cai, C.K.Cheng and J.Gu, VLSI Floorplanning with Boundary Constraints Based on