AN ACCELERATOR FOR FPGA PLACEMENT

Transcription

1 AN ACCELERATOR FOR FPGA PLACEMENT Pritha Banerjee and Susmita Sur-Kolay * Abstract In this paper, we propose a constructive heuristic for initial placement of a given netlist of CLBs on a FPGA, in order to accelerate the iterative phase of the placement in the context of re-configurable computing. The experimental results of our method show significant improvement in cost compared to the initial placement of the popular tool VPR. We observe that simulated annealing converges much faster given the proposed initial placement configuration. Keywords: FPGA, Placement 1. Introduction Placement in an FPGA is the process by which a netlist of circuit blocks (which are either I/O or Configurable Logic Blocks (CLBs)) is mapped onto physical locations which is essentially a two dimensional array. Placement algorithms are broadly classified as constructive methods and iterative improvement techniques. Constructive methods build up a solution step by step starting with a single unit. Iterative improvement algorithms start with a valid initial placement and repeatedly modify the configuration with the objective of reducing a certain cost such as delay, wire-length, area, etc. Iterative algorithms produce good placements but require enormous computation time which may depend on the initial configuration of the placement. Typically, many trials are performed with various initial solutions. The iterative phase may however be accelerated by starting with a good initial configuration. In the context of reconfigurable co-processors, it is essential to reduce the time complexity of mapping, place-and-route stages without sacrificing the quality of solution. From earlier works, we find that most of the FPGA placement algorithms are iterative. With this motivation, we propose in this paper a fast constructive placement algorithm for a given technology-mapped netlist of CLBs on an island-style FPGA, realizing a given digital circuit. 2. Earlier Works on FPGA Placement FPGA placement techniques can be categorized as force directed methods, Tabu search, successive bi-partitioning or quad-partitioning and clustering based algorithms. There are many works on bi-partitioning and quad-partitioning techniques for placement [Takahashi (1995), Krupnova (1997)]. Work related to clustering based techniques is extensive in the literature [Lou (1998), Senouci (1998), Fang (1997), Tsay (1995)]. Quinn and Breuer proposed a force directed constructive method by formulating a set of force equations [Quinn (1998)]. Eisenmann et al used additional force * Advanced Computing and Microelectronics Unit, Indian Statistical Institute, 203 B. T. Road, Kolkata , India. {pritha_r, ssk}@isical.ac.in This work was funded by Indo-French Centre for the Promotion of Advanced Research.

2 equations to reduce cell overlaps [Eisenmann (1998)]. The algorithm by Raman et al takes into account circuit performance as well [Raman (199)]. Betz et. al. have developed a tool VPR, that starts with a random placement and optimizes the placement by using a linear congestion cost function in the framework of simulated annealing [Betz (1997)]. There are several genetic algorithm based techniques for FPGA placement [Cohoon (1986), Saab (1991), King (1989)]. Emmert and Bhatia developed a Tabu search approach towards speeding up the placement and floorplanning steps of FPGA [Emmert (1999)] Mathur and Liu have developed a timing driven iterative algorithm that has alternate compression and relaxation phases for placement on regular architectures [Mathur (1997)]. In summary, most of the effective placement algorithms for FPGAs are based on stochastic iterative methods which however do not pay heed to the quality of the initial solution and its impact on the convergence time. 3. Problem Formulation The FPGA placement problem can be formally defined as follows. Given a set of modules M = {m 1, m 2,, m n } and a set of signals S = {s 1, s 2,, s q }, we associate each module m i M with a set of signals S, where S S. Similarly with each signal s i S we associate a set of modules M M s i = {m j s i S m j }. m i s i m i, where M s i is said to be signal net. We are also given a set L = {l 1, l 2,, l p }, where p M. The placement problem is to assign each module m i M to a unique location l j L such that the chosen objective function is optimized. For the case of mapping m i M to a regular two dimensional array, each l j L is represented by a unique (x j, y j ) location on the surface of the two dimensional array where x j and y j are integers [Emmert (1999)].. Proposed Initial Placement Method Our proposed approach is to place the netlists of CLBs on the FPGA using a novel constructive method and then we use a Simulated annealing framework to improve the configuration. This paper presents our fast yet cost effective constructive heuristic to place the CLB netlists. It also guides the iterative phase to improve the placement configuration in lesser number of iterations..1. Overview We place only the primary outputs randomly in the boundary of the square array, instead of randomly placing the entire CLB netlist on a minimum dimensional square array to place all CLBs and primary I/Os. For the given circuit specified as a netlist, let us define a directed graph D = <V, E>, where V = {v v is either a CLB, or a primary input (PI) or a primary output (PO)} and A = {<v i, v j > v i fanin(v j ) and v j fanout(v i )}. We define a cone for each of the primary outputs present in netlist as follows. A cone of a primary output O i, denoted by f i, is the set consisting of O i and all its predecessors [Mathur (1997)]. In other words, f i = cone(o i ) = { u a simple directed path from u to O i in D}. The root of the cone is the primary output

3 itself. Let C l be a CLB at level l (breadth-first order) in the cone of D. The predecessors of a CLB at level l, C l, within the cone are either CLBs or primary inputs which are in the fan-in of the CLB C l. These blocks form the next level of the cone f i. We continue tracing the input list at every block in breadth-first manner, till we find no new CLBs and primary inputs for the cone f i. Breadthfirst traversal of the cone results in a tree structure. At the leaves of the cone, we find all CLBs and primary inputs that have already been visited at one of the previous levels. Having defined output cone as above, we place the CLBs and primary inputs on the two dimensional minimum square matrix by processing any output cone at a time. Starting from the root of the output cone f i, we select all the blocks b i B l, where B l is the set of blocks at level l for placement. This process is continued till the base of the cone is reached. The CLB or primary input, b i, which is selected for placement, is placed at the optimal position with respect to the current configuration. In order to determine the optimal position we define a bounding box for the block b i as a rectangular region containing all b j fanout(b i ) fanin(b i ), i.e, the fan-out CLBs of b i as well as the CLBs and primary inputs in the input list of b i that are placed at that instant. We assign b i to a slot within the bounding box that results in minimum wire-length of the nets in the bounding box. If there are no empty slots left within the bounding box, we extend the bounding box by a row or a column, and place the block b i in the extended bounding box. This process continues for each of the CLBs and primary inputs present in the cone f i. By placing the blocks of the output cone f i, according to level order, the total estimated wirelength is therefore maintained as close to minimum as possible. Thus we process all the output cones of the given netlist one by one. This gives the initial placement configuration for the technology-mapped netlist specified, as input to an iterative procedure for further improvement in the placement configuration. The cost of our initial placement is measured as sum of semi-perimeter wirelengths over all nets in the given netlist as shown below. nets Total wirelength = ( bbspan x ( neti ) + bbspan y ( neti )) i= 1 where bbspan x (net i ) and bbspan y (net i ) are the horizontal and vertical span of bounding box of net i, respectively. We have compared our result with the bounding box cost of VPR [Betz (1997)].2. Initial Placement Algorithm Structure Used: netlist { primary input list, primary output list, clb list, number of primary inputs, number of primary outputs, number of CLBs } Initial Placement(technology-mapped~netlist): begin netlist read the netlist file clbmatrix generate a two dimensional array such that all CLBs and primary I/O can be placed in the square array configuration place primary outputs randomly on the boundary of clbmatrix

4 for all O i primary output do Q 1 φ Q 2 φ b i fanin(o i) configuration Place Block(configuration, b i) b i fanin(b i) enqueue(q 1,b i) repeat b i Trace Cone() configuration Place Block(configuration, b i) until Q 1 is empty end for end Trace Cone (): Begin b i dequeue(q 1) enqueue(q 2, b j) such that b j fanin(b i) and b j not placed if (Q 1 is empty) then} Q 1 Q 2 /* Start tracing next level in the cone */ Q 2 φ end if return b i end Place Block(configuration, b i): begin bbfanin(b i) A square region in clbmatrix containing fanin(b i) that are placed bbfanout(b i) A square region in clbmatrix containing fanout(b i) that are placed bb(b i) A square region in clbmatrix defined by bbfanin(b i) bbfanout(b i) while b i is not placed do p i bb(b i) such that p i is an empty slot in the bounding box and wlength(fanin(b i)) + wlength(fanout(b i)) is minimum amongst all slots in bb(b i) where, wlength(fanin(b i)) b fanin( b ) b j i j manhattan distan ce between p i and p j placed at p wlength(fanout(b i)) semi-perimeter length of bb(b k) such that b k fanout(b i) if no empty slot p i found then bb(b i) expanded bounding box by one row and one column on all sides else configuration b i placed in clbmatrix at p i end if end while return configuration end.3. A Running Example Let us consider an example netlist with 10 CLBs, primary inputs and 3 primary outputs, given in Table 1. The cone f i for primary output o_1() is shown in Figure 1. A strikethrough index in the output cone of indicates that the tree need not be grown any further. For example, all the children of 16 in the cone, i.e., 9, 1, 3 and 2 are already placed in the previous levels. Indices that are primary inputs are not expanded at any level. Tracing of the algorithm is shown in Figure 2. The random placement of all primary outputs as in VPR is shown in Figure 2a. By tracing the cone of primary output we find 7 in the tree, whose bounding box and placement is shown in 2b. Next we find 2 in the tree and so on. Figures 2c show the placement of all other blocks in the cone of. Figure 2d shows the initial placement configuration after all the output cones of the given netlist is placed. j

5 Table 1 : An Example Netlist Primary Input Name Index Fanout Name Index Fanout i_9 0 12, 15, 8, 13, 10 i_7 2 12, 9, 15, 16, 7 i_ , 11, 1 i_8 3 9, 16, 10 Primary Output Name Index Input Name Index Input o_1 7 o_ o_ CLB Name Index Input Fanout Nam Index Input Fanout e o_1_ 7 2, 8, 9 n3 8 11, 16, 0 12, 15, 1, 7 n6 9 15, 3, 2 16, 1, 7 o_2_ 10 3, 11, 12, 0 5 n2 11 1, 1 12, 8, 10 n , 2, 0, 8 10 o_0_ 13 0, 1, 15 6 n1 1 1, 9, 16, 8 11, 13 n5 15 8, 0, 2 9, 13 n 16 9, 1, 3, 2 8, Figure 1: Tracing the cone for a primary output o_1 5. Experimental Results We have compared the experimental results of our initial placement algorithm with that of VPR which places the CLBs and I/Os randomly on the minimum size square array of slots. We have placed the output pins randomly as is done in VPR, and then we followed the procedure described in the previous subsection to place the remaining CLBs and primary inputs. We tested the initial placement algorithm on the same MCNC Benchmark circuits used by VPR and the results obtained are shown in Table 2. The results show that for all the benchmark circuits, our initial placement method gives better result with respect to the bounding box cost as defined in Section.1 at the initial placement stage.

6 a) After the random placement of all the primary outputs c) After placing 2 (BB:0, to 1,) 8 (BB:1,3 to 1, or 1, to 2, ) 9 (BB:0, to 2,) 11 (BB:2 to 1,3 or 1,3 to 2,3) 16 (BB:0,3 to 2,), 0 (BB:0,3 to 1,3) 15 (BB:0,2 to 2,), 3 (BB:2,3 to 2,5) 1 (BB:2,1 to 1,), 1 (BB:1,0 to 2,0) b) After placing 7 (BB:1, to 1,5) d) After placing all output cones, i.e., 5 and 6 Slots reserved for primary I/Os Figure 2: Steps of our algorithm Table 2: Experimental Results of Initial Placement Our Initial Placement Initial Placement of VPR * MCNC Matrix Total BB Cost Benchmark Dimension Wire-length (VPR) Initial BB Cost alu.net apex2.net apex.net Ex1010.net ex5p.net pdc.net seq.net spla.net * Calculation of Total Wire-length for Initial Placement of VPR can be obtained easily

7 Table 3: Experimental Results of Final Placement MCNC Benchmark Our Initial Placement + VPR Final BB Cost # of Iterations Cpu Time (min:sec) Final BB Cost Placement of VPR # of Iterations Cpu Time (min:sec) Alu.net : :19 apex2.net : :21 apex.net 181 1: :35 ex1010.net : :20 ex5p.net : :00 pdc.net : :27 seq.net : :35 spla.net : :15 Table 3 shows the comparison of results of final placement, CPU time and number of iterations in the iterative phase. For all the circuits we achieve a speedup in the number of iterations and CPU time with bounding box cost very close to optimal. 6. Conclusion and Future Directions We present a constructive initial placement algorithm for placement of netlist on FPGA to accelerate the final placement phase. The netlist is placed by tracing the output cones present in the netlist. At every step, blocks are assigned to an optimal position with respect to the current configuration. Our results show improvements in the initial placement stage when compared to the initial placement of VPR. We also observed that VPR converges faster, given our initial placement configuration. We will consider the effect of ordering output cones for critical paths in our future work. We also expect further acceleration by taking into account the overlap of cones. Another area of improvement is elimination of re-calculation of the best position by reuse of information. Last but not the least, an appropriate iterative technique focusing on moves based on neighbourhood parameters so that it converges very quickly to an optimal solution, is being developed. References Emmert, J. M., Blanacha, S., And Bhatia D. K. (1999), Physical Layout Techniques for Field Programmable Gate Arrays, invited paper, IEEE, ACM, SIGDA Design and Test Workshop. Quinn, Jr., N. R., And Breuer, M. A. (1979), A Force Directed Component Placement Procedure for Printed Circuit Boards, IEEE Trans. on Circuits and Systems, Vol. CAS-26, No.6, June, pp. Eisenmann, H., And Johannes, F. M. (1998), Generic Global Placement and Floorplanning, In Proceedings of the 35th Design Automation Conference. Raman, S., Liu, C. L., And Jones, L. G. (199), Timing-Constrained FPGA Placement: A Force-Directed Formulation & Its Performance Evaluation, VLSI

8 Design: An International Journal of Custom Chip Design, Simulation, and Testing. Betz, V., And Rose, J. (1997), VPR: A New Packing, Placement and Routing Tool for FPGA Research, In 7th International Workshop on Field- Programmable Logic and Applications, pp Cohoon, J. P., And Parris, W. D. (199), Genetic Placement, In Proceedings of the International Conference on Computer-Aided Design, pp Saab Y. G., And Rao V. B. (1991), Combinatorial Optimization by Stochastic Evolution, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol 10, April, pp King, R. M., And Banerjee, P. (1989), ESP: Placement by Simulated Evolution, IEEE Trans. on Computer-Aided Design,Vol. 8, March, pp Emmert, J. M., And Bhatia, D. K. (1999), Fast Timing Driven Placement Using Tabu Search, In IEEE International Symposium on Circuits and Systems, May. Takahashi, K., Nakajima, K., Terai, M., And Sato, K. (1995), Min-Cut Placement with Global Objective Functions for Large Scale Sea-of Gates Arrays, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 1, April, pp Krupnova, H., Rabedaoro, R., And Saucier, G. (1997), Synthesis and Floorplanning for Large Hierarchical FPGAs, In ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. Lou, J., Salek, A. H., And Pedram, M. (1998), An Integrated Flow for Technology Remapping and Placement of Subhalf-micron Circuits, In Asia- South Pacific Design Automation Conference Proceedings. Senouci, S. A., Amoura, A., Krupnova, H., And Saucier, G. (1995), Timing Driven Floorpanning on Programmable Hierarchical Targets, International Symposium on Field Programmable Gate Arrays. Fang, W. J, And Wu, A. C-H. (1997), Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy, In Proceedings of the 3th Design Automation Conference. Tsay, Y., And Lin, Y. (1995), A Row-Based Cell Placement Method that Utilizes Circuit Structural Properties, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 1, March, pp Mathur A., And Liu, C. L. (1997), Compression-Relaxation: A New Approach to Timing-Driven Placement for Regular Architectures, IEEE Trans. on CAD of Integrated Circuits and Systems, Vol 16, No 6, June, pp