Research Paper ANALYSIS AND DESIGN OF VLSI FLOORPLANNING ALGORITHMS FOR NANO-CIRCUITS Gracia Nirmala Rani. D 1, Rajaram.S 2 Address for Correspondence

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1 Research Paper ANALYSIS AND DESIGN OF VLSI FLOORPLANNING ALGORITHMS FOR NANO-CIRCUITS Gracia Nirmala Rani. D 1, Rajaram.S 2 Address for Correspondence 1,2 Department of ECE, Thiagarajar College of Engineering, Madurai, Tamilnadu , India. ABSTRACT The semiconductor industry has advanced tremendously over the last ten years with features sizes being downscaled from micrometer to nanometer regime. As the VLSI technology marches towards nanotechnology, the physical design complexity is increasingly with millions of layout objects on a monolithic chip. In the physical design process, floorplanning is an important step, as it establishes the groundwork for a good layout. The existing challenges and limited solutions to the different issues under VLSI floorplanning problem include placing a set of circuit modules on a chip to minimize the total area and interconnect cost. And adding constraints such as alignment and performance blocks will make the floorplanning problem more critical. Also, more packing density of the modules inside the floorplanning will lead to increase the temperature and interconnection problem. All these issues must be addressed fully for the successful deployment of the intelligent VLSI floorplan representation. In this paper an attempt is made to address these issues by proposing robust algorithms and validating them with the MCNC benchmark circuits. Index Terms Design Automation, Very Large Scale Integration, Evolutionary Computation, Thermal Noise. I. INTRODUCTION VLSI circuit has a high design complexity that allows the implementation of a large number of transistors on a single chip. The non-ideal phenomenon for nanometer regime will become much more serious in runtime. Based on this consideration, the chip design became increasingly complex. Thus, CAD tool helps in automating the process of VLSI design by using sophisticated and efficient algorithms. It plays a major role in floorplanning problems due to its high computational complexity. This paper proposes the optimization algorithms for the different VLSI floorplanning problem. Floorplanning is used to plan the location of all circuit modules on a chip without overlapping each other and also the circuit performance is to be optimized. Hence, it is important to choose a good representation and a searching methodology to perturb the infinite solution space for a near optimal floorplan in less time. Also, the designers want to provide extra options to place the modules in the final packing for various reasons. If there are many interconnections between the modules or align vertically in the middle of the chip for busbased routing, the VLSI circuit designers is to limit the separation between two modules. So, it is desirable to find a useful way to handle the floorplanning problem with the placement constraints.in addition, aggressive scaling of DSM technologies allows the increased level of integration within a single die enforces rigid constraints on the power consumption budget and hence the temperature of the chip is increased. Hence, temperature based VLSI floorplanning designs has gained importance and popularity in recent years. II. LITERATURE SURVEY Many circuit designers search the good optimization tools for floorplanning problems. Generally, all the floorplan structure will be non sliceable. [2] proposed B*-tree based Annealing(SA) scheme for floorplan design runs faster, consumes less memory, and results in the smaller silicon area. To improve area utilization, [4] embedded SA into tabu search algorithm. This method doesn t exploit the information in the search space which is the major drawback. Then, [5] developed Hybrid Evolutionary Algorithm (HEA) which combines the efficiency of Fast SA and evolutionary algorithm. It is obvious that this method achieves a high-quality solution using hybrid scheme; especially the area objective has a marked improvement. But it takes larger computation time to produce the optimal solution space. Next, [6] explained that as the feature size is reduced, it increases exponentially with the increase in temperature. Hence, reducing the temperature of the chip will result in less leakage and most of the poweraware design does not reduce power density in hotspots, having little impact on operating temperature. Then [7] developed temperature-aware floorplanning via geometric programming techniques.next, [8] showed that thermal aware floorplanning can be done using B* tree representation and SA. Here top 20% modules are chosen and their module area is expanded to reduce the power density and the module temperature is reduced. The lack of proposals which is capable of dealing with a large number of functional units in a short time motivates this work. Many common challenges have been focused on the salvation of numerous floorplanning problems by using various techniques proposed in the literature survey. This work is considered as the area, wire length and thermal constraints for fixed frame floorplanning based on B*tree representation using our proposed Evolutionary (DE) algorithm in order to focus on a computation time complexity and solution space. III. B*TREE REPRESENTATION A floorplan is usually represented by a rectangular dissection. VLSI Floorplanning representations mainly classified into two types namely i) slicing representation and ii) non-slicing representation. The nonslicing category is a more general representation for all types of packing. Not all floorplans are sliceable. All these nice properties make the B*-trees an efficient and flexible representation for nonslicing floorplans. Hence, B*-tree based VLSI Floorplan representation has been considered in our proposed work. Given a placement P, to construct a unique B*-tree in linear time by using a recursive procedure similar to the Depth First Search (DFS) algorithm. Starting from the root, first construct the left sub tree and then the right sub tree recursively.

2 TABLE 1: COMPARISON BETWEEN VARIOUS PACKING FLOORPLAN REPRESENTATIONS Solution Flexibilit Space Size y Representati on Time Complexit y Encodin g friendly Space complexit y NPE[10] O(n!2 3n /n 1. O(n) General Low O(n) BSG [11] O(n!C(n 2, O(n 2 ) General Medium O(nlgn) n)) SP [12] (n!) 2 O(n 2 )* General Medium 2nlgn CBL [13] O(n!2 3n /n 1. O(n) Mosaic High nlgn + 3n B*-tree[14] O(n!2 2n /n 1. O tree [15] O(n!2 2n /n 1. Amortized O(n) Amortized O(n) compacte d compacte d High nlgn + 2n Medium nlgn + 2n CS [16] (n!) 2 O(n) compacte Low -- d TCG [17] (n!) 2 O(n 2 ) General Medium O(n 2 ) Figure.1 (a) Admissible Placement (b) The Corresponding B*-tree Fig.1 (a) & (b) shows a placement and its corresponding B*-tree respectively. The root n 0 of the B*-tree denotes that M 0 is the module on the bottomleft corner of the placement. For node n 3 in the B*- tree, n 3 has a left child n 4 which means that module M 4 is the lowest adjacent module on the right-hand side of the module M 3 (i.e. n 4 = n 3 + n 3 ). n 7 is the right child of n 3 since module M 7 is the visible module over module M 3 and the two modules have the same x coordinate (n 7 = n 3 ). IV. DIFFERENTIAL EVOLUTIONARY ALGORITHM FOR VLSIFLOORPLANNING Researchers [10] proposed a new floating point encoded evolutionary algorithm for global optimization and named it Evolution (DE) algorithm. It has a special kind of differential operator, which they invoked to create new offspring from parent chromosomes instead of classical crossover or mutation. If the new parameter vector is accepted, automatically it reduces the objective function value. This method is usually named the greedy search. The convergence speed will be fast in the greedy local search method, but it can be trapped by local minima. This problem can be eliminated by running several vectors simultaneously. This is the main idea of DE algorithm. Even though many evolutionary algorithms like genetic algorithm versions have been developed, still it has a computational problem. In order to overcome this problem, the evolution strategy called DE algorithm has been proposed. It has been applied to our VLSI floorplanning problem to optimize the area and wirelength of the floorplan modules 4.1 Problem Description Let M = {M 0, M 1..., M n }be a set of n rectangular modules, and w i, h i and a i be the width, height and area of b i, 1 i n, respectively. The aspect ratio of b i is given by w i /h i. A placement is an assignment of the rectangular modules b i s with the coordinates of their bottom-left corners being allocated to (x i, y i ) s so that no two modules overlap. 4.2 Fitness Function Each individual in the population is an admissible floorplan represented by a B*-tree. The floorplanning objective is to minimize the area and the estimated wirelength. The floorplan objective function will be defined [20] as follows: area wirelength cos t( F ) 1 * 2 * area wirelength (2) In the above equation, area is the smallest rectangle including all the modules. wirelength which represents the interconnection costs is calculated by the semiperimeter method. Area * and wirelength * represents the minimal area and the interconnection costs, respectively. As the values in practice are not known, estimated values such as ω 1 and ω 2 are the weights assigned to the area minimization and the wirelength minimization objectives respectively, where 0 ω 1, ω 2 1, and The fitness of an individual (Floorplan) is defined as follows 1 Fitness( F) cos t( F) (3) Where F is the corresponding floorplan and the cost (F) is defined in Equation (2). 4.3 Initial Population An individual in the initial population is a B*-tree, it represents an admissible VLSI floorplan. An admissible B*-tree is constructed by a constructive algorithm. It is based on a deterministic algorithm. 4.4 Mutation The role of the mutation operation is to discover a new assuring search region by mutating the structure of an individual. The two mutation operators are used with the DE to discover new search regions that have different fitness distances from the mutating individual. Given an admissible floorplan represented as a B*-tree, the first mutation operator identifies the left branch and the right branch of the B*-tree, then swaps the two branches of the B*-tree (Fig.2). Observe that the mutated floorplan may not be admissible. Therefore, by moving the modules to the left-hand side and the bottom, the mutation operator makes it admissible. Figure.2 (a) Mutation Operator Op1 (b) Mutation Operator Op2 4.5 Crossover The target vector and the mutated vector are mixed. Given any two individuals as parents, both of which are admissible floorplans represented by B*-tree, the crossover operator transmits the important structural information from two parents to a child. First, a partial set of nodes from first parent is transferred to the offspring through this process. Hence, the child can inherit some properties from its parent. Second, the remaining nodes are arbitrarily selected from second parent. To generate a child C 1 from two parents P 1 and P 2, the crossovers selects the left branch from P1, copy them, and puts them in C1 (Fig.3). Then, the crossover operator makes a copy of P 2 and takes out those nodes that have been present already in C 1 and then the remaining structural components is

3 added to C 1. In this way, the generated child carries the significant structural information from the parents. Fig.3 illustrates the basic idea behind the crossover operator Figure.3 (a) Crossover - P1 Parent(b) Crossover - P2 Parent (c) Crossover - C1 Child 4.6 Selection The greedy selection scheme is used. If and only if the trial vector gives a good cost function value compared to the parameter vector, it is accepted as a new parent vector for the following new generation (G+1). Otherwise, the target vector is kept to serve as a parent vector for generating G+1 once again. V. DIFFERENTIAL EVOLUTIONARY ALGORITHM WITH CONSTRAINTS Based on the various constraints, circuit blocks/ip blocks will be placed on a chip in VLSI floorplanning process. Additional constraints are imposed on a subset of blocks that have to be located inside the chip in the real world floorplanning problem. Therefore it is need to allow users for specifying placement constraints during the floorplanning process. 5.1 Fitness Function The VLSI floorplanning objective is to minimize the area and the wire length. area wirelength cos t( F) ar 1 * 2 * (6) area wirelength ar is the aspect ratio to control the floorplan operations. The constraints function will be included in the objective function of this algorithm. The fitness of an individual (Floorplan) is defined as follows. 1 Fitness( F) constraintfunction (7) cos t( F) Where F is the corresponding floorplan and the cost (F) is defined in Equation (6). 5.2 VLSI Floorplanning with Constraints During the optimization algorithm, perturbation operation can be done in the B*tree. The following operations are required to perturb a B*-tree. Op1: Rotate a block. Op2: Flip a block. Op3: Move a block to another place. Op4: Swap two blocks. Op5: Move a set of alignment blocks to another place. The first four operations are very similar to the previous work and the last one is designed for alignment constraints. In Operation 5, a set of alignment blocks is moved to another place. The positions of the first pair of a dummy node and an alignment node change in the alignment shape. Then, other pairs of dummy node and alignment nodes have attached to the correct positions to maintain their shape. VI. THERMAL AWARE VLSI FLOORPLANNING In nanometer technology, the large number of transistors will be integrated in a single chip leads to high power dissipation. Another important factor that involves the temperature distribution of a chip is the lateral spreading of heat in silicon. This depends on the functional unit adjacency determined by the floorplan of the system blocks. Therefore, temperature based VLSI floorplanning designs have has enlarged importance and popularity in recent years. In this work, a new floorplanning method is presented to reduce the temperature of the chip. Temperature aware floorplanning is able to greatly improve the temperature distribution of the chip during block placement. The Hotspot thermal model [11] is used for temperature driven floorplanning. The HotSpot software tool calculates the temperature distribution among different blocks in a chip. The main objective of this work is to arrange the blocks in a floorplan such that the maximum temperature of the floorplan is reduced. The highpower density blocks are the cause of generating high temperature. Also, if two or higher power density blocks come besides each other, they might create a hotspot and would result in high temperature. In order to reduce the maximum temperature of the floorplan, the blocks with high-power density blocks should be placed away from each other as far as possible, so that high power density blocks would dissipate heat to the low-power density blocks. As a result, the maximum temperature is reduced. Thermal aware floorplanning makes use of the Hybrid Annealing (HSA) Algorithm and is used to reach a globally optimal solution. 6.1 Problem Description Let B = {b 1, b 2 b m } be a set of m rectangular modules with block b i of width w i, height h i, area a i, and an original power density P i, 1 <i<m. Each module is free to rotate. The goal of the thermal aware floorplanning algorithm is to optimize chip area, wirelength and peak/average temperatures across the chip. The hotspot in a modern chip have a temperature of more than 100 C while the intra chip temperature differentials is larger than 10~20 C. Temperature can have a staged impact on circuit performance, power, and reliability. Therefore, it is very important to eliminate hotspots and have a thermal balanced design in VLSI circuits. This proposed work uses a B*-tree for representing floorplan structure to distribute the temperature evenly across a module (Fig.4). Figure.4 B*-tree Representation for Cooling Modules 6.2 Fitness Function Thermal aware floorplanning is a Multi-objective optimization problem. The parameters are area, wire length and temperature. The cost function is given in

4 the following equation. area wirelength Temp Cost (F) ar 1area* 2 wirelength* 3 Temp* (8) Where area, wirelength and Temp are the total area, wirelength and the maximum temperature respectively. Let Area *, Wire * and Temp * are the average value of the area, wire length and temperature based on the randomly generated 1000 kinds of floorplan calculation. Parameter ar is used to control the floorplan aspect ratio. 6.3 Hybrid Annealing Algorithm First, initial B*-tree is generated using new constructive method in the HSA. Then, the local search method is used in the HSA to exploit local information in the search region. Afterward, a new operation on the B*-tree can be done by swapping two sub trees in the B*-tree to generate a new configuration. Finally, a novel bias search approach is used to determine if the new configuration could be accepted for balancing the global exploration and local exploitation. VII. EXPERIMENTAL RESULTS The experimental setup is as follows. The DE floorplanning algorithm is implemented in C++ programming language on an Intel Core i5 with 2.10 GHz.The DE algorithm is run to regenerate the outputs and compared the results with the previous evolutionary algorithms. For the DE, the population size (NP) is set to 100, the probability of crossover (CR) is 0.9, and a scaling factor (F) is 0.5. In this experiment, the weight to the area and the interconnection minimization objective was set to 1. The circuit characteristics of Microelectronics Center of North Carolina (MCNC) are presented in Table 2.1 respectively. TABLE 2: THE STANDARD MCNC BENCHMARK CIRCUITS Circuit # of #of # of i/o # of Area modules nets pads pins Apte xerox Hp ami ami TABLE3: AREA COMPARISONS BETWEEN VARIOUS OPTIMIZATION ALGORITHMS MCNC benchmarks Circuits Modules# annealing area Non slicing(b*-tree) Previous algorithms Evolutionary simulated annealing Hybrid simulated annealing Hybrid genetic algorithm Proposed Method evolution area apte xerox hp ami ami TABLE4: WIRE LENGTH COMPARISON BETWEEN VARIOUS OPTIMIZATION ALGORITHMS MCNC Benchmarks Circuits Modules# Annealing Fast SA Non Slicing (B*-tree) Previous algorithms Hybrid annealing Evolutionary Annealing ProposedMethod Evolution apte xerox hp ami ami TABLE5: RUNTIME COMPARISONS BETWEEN VARIOUS OPTIMIZATION ALGORITHMS MCNC Benchmarks Circuits Modules# Annealing (sec) Fast SA (sec) Non Slicing (B*-tree) Previous research Hybrid Annealing (sec) SA embedded in Tabu search (sec) apte xerox hp ami ami Proposed method Evolution (sec)

5 Table 3 & 4shows the area and wirelength comparison between various evolutionary algorithms with proposed DE algorithm. It gives the better area optimization result (2.27%) compared to the other optimization algorithms. When compared the wire length metric, it provides the best optimization (87.71%) related to the SA algorithm only. Table 5 exhibit the runtime comparison between the optimization algorithms. It clearly shows that the DE algorithm has a less computation time with other algorithms. Because the DE algorithm has a few control parameters to find an optimal function. The proposed DE algorithm with alignment and performance constraints have compared with SA framework as shown in Table 6 & 7. The proposed approach adopts a DE algorithm without resorting to floorplan representations, and the placement constraints of the buses are satisfied during the block-packing process. The following notations will be used in the benchmark circuits: xerox-1 and hp-1 contains four alignment blocks only. Xerox-2 and hp-2 contains four alignment blocks and two performance blocks. ami33-1 and ami49-1 consists of four and five alignment blocks ami33-2 and ami49-2 contains four alignments and three performance blocks. Table 6 and 7 compares area (2.05%) and runtime (43.99%) between SA and DE with alignment and performance constraints. Table 8 represents the wire length estimation of the algorithm. When the performance blocks are used, it reduces the critical net delay and it leads to decrease in the total wire length of the module. TABLE 6: AREA ESTIMATION WITH ALIGNMENT AND PERFORMANCE CONSTRAINTS Circuit Blocks Constrained blocks Proposed Annealing Evolution Area Area Align Perf apte xerox xerox hp hp ami ami ami ami ami TABLE7: RUNTIME ESTIMATION WITH ALIGNMENT AND PERFORMANCE CONSTRAINTS Circuit Blocks Constrained blocks Align Perf Proposed Annealing Evolution Run Time(sec) Run Time(sec) Apte xerox xerox hp hp ami ami ami ami ami TABLE8: WIRELENGTH ESTIMATION WITH ALIGNMENT AND PERFORMANCE CONSTRAINTS Ours; Constrained blocks Circuit Blocks Evolution Align Perf Wire length Apte xerox xerox hp hp ami ami ami ami ami Figure.5The Result packing of ami33-2. And ami49-3 (a) (b) Figure.6 Floorplan and Distribution of the (a) apte (b) Xerox (c) (c) hp Benchmark Circuit HotSpot tool calculates the maximum temperature of the floorplan and uses this maximum temperature as one of the objectives in HSA algorithm in the floorplanning process. Maximum temperature of a floorplan with hot blocks placed besides cooler blocks is relatively lesser than the maximum temperature of a floorplan with hot blocks placed besides each other. Since this maximum temperature is used to optimize the objective function of the algorithm, the floorplanner tries to push away the hot blocks as far as possible from each other. Fig.7 shown below gives the optimum floorplan that is temperature-aware using HSA algorithm. The maximum temperature of the chip reduces considerably when thermal aware floor planning is used, in comparison to normal floorplanning or floor planning without temperature factor. Fig.8 (a) & (b) shows the normalized reduction of maximum chip temperature in various benchmarks.

6 (a) (b) figure.7 temperature aware floorplan for (a) apte (b) xerox (c) (c) hp Benchmark Circuit (a) (b) Figure.8(a) Comparison of the Peak Temperature of the MCNC Benchmark Circuit (b) VIII. CONCLUSION In the first step, a novel DE algorithm based on B*-tree representation has been proposed for non-sliceable floorplanning problem. From the comparison results of different algorithms with our proposed algorithm using MCNC benchmarks, it is clear that the DE algorithm shows the better optimized results in the area and computational time. Then, our proposed DE algorithm guarantees a feasible placement solution with alignment constraints and generates a good placement with performance constraints during each operation. The advantage of using DE is the reduction of computation time by proposing a trial solution (with all constraints) which does not need evaluating the objective function every time. Furthermore, a novel thermal aware floorplanning method using a HSA algorithm has been implemented.the optimized floorplan is obtained and separates available two hot modules to decrease the overall die temperature. The next research direction is that how to make 3-D floorplanning both temperature-aware and leakage-aware is a good topic. REFERENCES [1]. Skadron, K, Stan, M, Velusamy, S &Sankaranarayanan, K 2005, A case for thermal-aware Floorplanning at the microarchitectural level, Journal of Instruction-Level Parallelism, pp.8-1. [2]. Chang, YC, Chang, YW, Wu, GM & Wu, SW 2000, B*-tree: A New representations for non slicing floorplans, Proceedings of ACM/IEEE Design Automation Conference, LosAngles, pp [3]. Tung- Chieh Chen & Yao-Wen Chang 2006, Modern Floorplanning based on B* tree and Fast Annealing, IEEE Transactions on Computer Aided Design of Integrated circuits and systems, vol. 25, no. 4, pp [4]. Maolin Tang & Xin Yao 2007, A memetic algorithm for VLSI Floorplanning, IEEE Transactions on Systems, Man, and Cybernetics, Part B, vol. 37, no. 1, pp [5]. Jiarui Chen &Jianli Chen 2010, A Hybrid Evolution Algorithm for VLSI Floor planning, Proceeding of IEEE Design Automation Conference in Computational Intelligence and Software Engineering, pp [6]. Liu, Y, Dick, RP, Shang, L & Yang, H 2007, Accurate temperature-dependent integrated circuit leakage power estimation is easy, Proceedings of the conference on Design, Automation and Test in Europe, pp [7]. Ying-Chieh Chen &Yiming Li 2010, Temperature-aware floorplanning via geometric programming, Mathematical and Computer Modelling, vol. 51, no.7-8, pp [8]. Lixia Qi, Yinshui Xia &Lunyao Wang 2011, Annealing Based Thermal-Aware Floorplanning Proceedings of International Conference on Electronics, Communications and Control (ICECC), pp [9]. Po-Hsun Wu & Tsung-Yi Ho 2012, Bus-driven Floorplanning with bus pin assignment and deviation minimization, Integration the VLSI Journal, vol.45, no.4, pp [10]. Price, KV 1999, An Introduction to Evolution. In: Corne, D., Dorigo, M. and Glover, F. (Eds.). New Ideas in Optimization, McGraw-Hill, London. ISBN , pp [11]. Skadron, K, Stan, M, Velusamy, S &Sankaranarayanan, K 2005, A case for thermal-aware Floorplanning at the microarchitectural level, Journal of Instruction-Level Parallelism, pp.8-1. [12]. Young, FY & Wong, DF 1997, How Good are Slicing floorplans, Integration the VLSI Journal, vol.23, pp [13]. Young, FY & Wong, DF 1998, Slicing floor plans with preplaced modules, Proceedings of ICCAD, pp [14]. Young, FY & Wong, DF 1999, Slicing floorplans with boundary constraint, Proceedings of Asia and South Pacific Design Automation Conference, pp [15]. Young, FY, Wong DF & Yang, H 2001, On extending slicing floorplan to handlel/t-shaped modules and abutment constraints, Proceedings of IEEE TCAD, vol. 20, no.6, pp [16]. Rong Luo & Peng Sun 2007, A Novel Ant Colony Optimization Based Temperature-Aware Floorplanning Algorithm, Proceedings of Third International Conference on Natural Computation,vol.4, pp [17]. Hu, TC &Kuh, ES 1985, VLSI circuit layout: Theory and design, IEEE Press, New York, USA. [18]. Wan-Ping Lee, Hung-Yi Liu& Yao-Wen Chang 2009, Voltage-Island Partitioning and Floorplanning under Timing Constraints, IEEE Transactions on CAD of Integrated Circuits and Systems,vol.28, no. 5, pp [19]. Jackey ZY & Chris Chu 2010, DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanning Algorithm, IEEE Transactions on computer-aided design of integrated circuits and systems, vol. 29, no. 3, pp [20]. Rawat, CD, Anmol Shahani, NitishNatu, Abbas Badami, &RonakHingorani 2012, A Genetic Algorithm For VLSI Floorplanning, International Journal Of Engineering Science & Advanced Technology, vol. 2, no.3, pp