Implementation of a Low Power Decimation Filter Using 1/3-Band IIR Filter

Transcription

1 Implementation of a Low Power Decimation Filter Using /3-Band IIR Filter Khalid H. Abed Department of Electrical Engineering Wright State University Dayton Ohio, Abstract-This paper presents a unique design and implementation of a low power decimation filter. The designed decimation filter architecture shows how the /3- band IIR filter and a poly-phase half-band FIR filter are used effectively for multirate multistage signal processing. The /3-band IIR filter is realized using six first order all-pass filters. Each filter stage is simulated using Matlab and, the complete architecture of the decimation filter is captured using Simulink and a DSP Blockset. The hardware realization of the decimation filter is obtained using FPGA Xilinx technology. The designed decimation filter reduces the hardware by 59% and the power dissipation by 34% compared to conventional decimation filters. I. INTRODUCTION Decimation filters are used for telecommunication applications such as asymmetric digital subscriber line (ADSL), broadband, and video applications. There have been continuous efforts to reduce the computational complexity of decimation filters. Hence, efficient structures of decimation filters have been designed. Babic et al. [] has described an efficient flexible implementation of a cascaded integrator comb (CIC) filter for multirate multistage signal processing. Aboushady [2] presents some results that are useful in determining the proper choice of the first stage decimation factor for the decimation filter. The poly-phase decomposition used in the realization of decimator is described in Mitra [3]. The poly-phase decomposition is incorporated to obtain computationally efficient decimators. Kaiser et al. [4] shows the multirate multistage implementation approach to reduce the computational requirements in sampling rate conversion by factoring the rate conversion ratio into small integers. Johansson [5] mentions that using a cascade of low order all-pass infinite impulse response (IIR) filters can reduce hardware and power consumption. The design of /3-band IIR filter is described by Lutovac et al. [6]. The poly-phase form of half-band filters, described by Barrett [7], is hardware efficient and consumes low power. In this paper, we propose to design and implement a novel and a hardware efficient architecture for a decimation filter. The proposed decimation filter is designed using the economical /3-band IIR filter and the computationally efficient poly-phase implementation of half-band filter. The paper is organized as follows. The Shailesh B. Nerurkar Department of Electrical Engineering Wright State University Dayton Ohio, second section consists of the design and implementation of digital decimation filter. Section III describes multirate multistage signal processing and some advantages of using poly-phase network for decimators. In section IV, the design and implementation of /3-band IIR filter is explained. The fifth section includes the poly-phase halfband filter and its part in increasing the efficiency of the decimation filter. In section VI, we present results and a comparison table that shows the reduction in computational complexity of the decimation filter compared to other decimation filter architectures for telecommunication applications. Finally, we provide conclusions based on the designed decimation filter. II. DIGITAL DECIMATION FILTER Generally, digital decimation filters are implemented using finite impulse response (FIR) filters and comb filters. A cascade of either comb-fir chain or FIR-comb chain is commonly used. Multipliers represent most of the hardware used to implement a filter; as a result, multipliers contribute to most of the power dissipated in a filter. Thus, the designed multiplier-less CIC filter is suitable for low hardware implementation and low power consumption. CIC filters consist of two basic building blocks, an integrator and a comb filter. An integrator is a single pole IIR filter. The transfer function of an integrator is given by (). Figure shows the implementation of an integrator. H z ) = z ( Figure. An integrator. A comb filter is an odd symmetric FIR filter decimated by a factor M. The transfer function of a comb filter is given by (2). H ( z ) = z () ( 2 ) /03/$7.00 (C) 2003 IEEE 460

2 Figure 2. A comb filter. Figure 2 shows the implementation of a comb filter. An N- stage CIC filter consists of a cascade of N integrator sections together with N comb sections. Since the comb filter operates at a low sampling rate of f s /M, we have considerably increased the efficiency by reducing the hardware and the power consumption. This technique reduces the delay elements in the comb sections and it allows the integrator and comb filter to be independent of the change in the sampling rate. A single stage CIC filter has a drawback of poor stop band attenuation; therefore, we have used a fourth order CIC filter. The fourth order CIC filter consists of four cascaded integrator stages, operating at a sampling rate of f s, followed by 6: decimator, followed by four cascaded comb stages operating at a sampling rate of f s /6 as shown in Figure 3. For a 4-bit binary word, Aboushady presents a graph for hardware requirements and power consumption, which indicates that a decimation factor of 6 is a proper choice for the first decimation stage. As a result, we have used a decimation factor of 6 in the first stage for the CIC filter. The input frequency of the CIC filter is 600 MHz, and after the decimation by a factor of 6, the output frequency of the CIC filter is 37.5 MHz. The /3-band IIR filter is used at a higher sampling rate to reduce the computational complexity and achieve an economical and efficient decimation filter. The /3-band IIR filter is followed by a half-band FIR filter, which considerably reduces hardware and power consumption. The proposed decimation filter architecture for low power and minimal hardware is shown in Figure 5. Figure 5. The proposed digital decimation filter. III. MULTIRATE MULTISTAGE SIGNAL PROCESSING Figure 3. The implementation of a fourth order CIC filter. The fourth order CIC filter used in the decimation filter provides the required stop band attenuation of 55 db as shown in Figure 4. Multirate multistage signal processing is important in modern telecommunication applications. The over sampling performed on sigma-delta decimator filter results in high order filters and very high power consumption. The order of the filter is directly proportional to the pass-band ripples and stop-band ripples and inversely proportional to the ratio of the width of transition band and the sampling frequency. The power consumption is directly proportional to the number of taps, the word length and the sampling frequency. To overcome this problem, we have considered a multirate multistage approach described by Kaiser to design and implement the proposed decimation filter. In this approach, every stage filters to a certain extent; then, a down-sampler is used for further reduction of the sampling frequency. This approach reduces the hardware and power dissipation in the decimation filter. The poly-phase decimators used along with multirate multistage signal processing provide efficient decimation filter structures. The M-stage conventional decimator followed by a lowpass filter H(z) is shown in Figure 6. Figure 4. The stop-band attenuation of a fourth order CIC filter. Figure 6. An M-stage conventional decimator. 46

3 In the conventional decimator structure, shown in figure (6), all the computations are required to be completed in one sampling period, and for the following (M-) sampling periods the arithmetic units remain idle. Thus, the computational requirements for an N th -order FIR filter are N multiplication and N addition to compute one output sample. Now consider an M-stage poly-phase decimator followed by a low-pass filter H(z) as shown in Figure 7. increases the sampling frequency and allows the IIR filters to operate at a high sampling frequency. The computationally efficient /3-band IIR filter is obtained by reducing the frequency band to one-third of the original band. The /3-band IIR filter is designed by using the Ellip built-in Matlab function, (3) and (4) as described in [6]. f P = tan π 3 tan( πf S ) (3) f S = F S (4) Where f P = pass-band edge f S, F S = stop-band edge. The frequency response of a /3-band IIR filter is shown in Figure 8. Figure 7. An M-stage poly-phase decimator. In poly-phase decimators, the arithmetic units operate at all instants of the output-sampling period, which is M times that of the input sampling period. Thus, the computational requirements of the overall structure for an N th -order FIR filter are N multiplication and N addition. Thus, multirate multistage techniques employed along with poly-phase decimators result in computationally efficient realizations. IV. /3-BAND IIR FILTER Due to its computational simplicity, IIR filters have less hardware and consume less power than FIR filters. The direct form, transpose form, parallel form and cascade form are some of the realizations used to implement /3- band IIR filter. The direct form and the transpose form of realization consume more hardware and power than the last two forms. The IIR filters have high coefficient sensitivity if they are composed of two all-pass filters in parallel as described in [5]. They also set bounds on the maximal sampling frequency at which a filter can be implemented. Hence, we cascade first order all-pass filters to implement the /3-band IIR filter. The interconnection of low order filters reduces the sensitivity of coefficients and the latency in the critical loops, which eventually Figure 8. Frequency response of a /3-band IIR filter. Several structures can be used for cascade lattice realization of all-pass IIR filters, but most of the structures except the one-multiplier realization result in 2N multipliers for an N th -order filter. The one-multiplier realization approach results in N multipliers for an N th - order filter. This results in low power consumption and minimal hardware for the decimation filter structure. The first order all-pass filter with one-multiplier realization is shown in Figure 9. Figure 9. First order all-pass filter with one multiplier cascaded lattice realization. 462

4 The transfer function of the first order all-pass filter is given by (5). d + z A ( z ) = + d z ( 5 ) These identical first order all-pass filters are cascaded to form a high order low-pass /3-band IIR filter. For high order filters, the parameter d is adjusted to get the desired response of the /3-band filter. Figure 0 shows a /3-band IIR filter implementation. Figure. The poly-phase implementation of half-band FIR filters. VI. RESULTS Figure 0. A /3-band IIR filter implementation. The parameter d of the /3-band IIR filter is calculated using (6) presented in [3]. d sin( w ) = cos( w ) Where w represents the 3-dB cut-off frequency. V. POLY-PHASE IMPLEMENTATION OF HALF- BAND FILTER (6 ) In half-band filters, the number of taps is reduced by 50% since the odd coefficients are zeros. This considerably reduces the hardware and the power consumption. As a result, we use half-band FIR filters instead of direct conventional FIR filters. The half-band FIR filter is designed using the Remez algorithm, which gives the filter coefficients. The poly-phase implementation exploits the symmetry of coefficients of the FIR filters. This reduces the computational complexity since only half the number of coefficients is used to implement the decimation filter. This poly-phase implementation reduces the power consumption by approximately one-half because the filter operates at the decimated rate instead of the input rate. The poly-phase implementation of half-band FIR filter is shown in Figure. A sigma-delta modulator generates an output sampling frequency of 600 MHz, which is used as the input to the decimation filter stages. The decimation filter has a flat pass band of 2.25 MHz and a cut-off frequency of 4.5 MHz, which is suitable for telecommunication applications like ADSL. Consider (7) for calculating the power metric: Power α (taps adders/tap frequency word length) (7) Equation (7) can be represented as follows: Power α (T A F/ F i L) (8) Where T = Taps of the Filters used in the architecture A = Adders used in each tap F = Input sampling frequency of the filter F i = Input sampling frequency of the final FIR filter L = Output word length. The coefficients for all the filters included in decimation filter architectures in Table are obtained from Matlab simulations. We are using 4 integrators operating at 48 F i and 4 differentiators operating at 3 F i, where F i is 2.5 MHz. Since the number of input bits is 4 and the final output word length is 8 bits, the power metric for the integrators and comb filters are 536 and 96 units, respectively. As a result, we obtain a total power metric of 632 units for the CIC filter stage. We calculate the power metric of the /3-band IIR filter and the half-band filter by using (8). 463

5 Similar to Barrett, we use three adders for each tap instead of a multiplier. The effective numbers of taps for the /3-band IIR filter and half-band filter are 6 and 8, respectively. The power metric for the /3-band IIR filter is 540 units since it is operating at 3 F i and has a word length of 0. Similarly, the power metric for the half-band filter, which has a word length of 2 bits, is 288 units. The total power metric for the decimation filter is 2460 units. Decimation filter Power Consumption Number of taps Comb-FIR-FIR Comb-FIR-IIR Comb-IIR-FIR Comb-IIR-FIR Comb-/3-band IIR-FIR Table. Comparison of decimation filters. Table presents five architectures used to design decimation filters. By using Matlab simulations, the number of taps for the first IIR filter and the second FIR filter of the conventional decimation filter is 6 and 8, respectively. The conventional decimation filter designed with a direct form IIR filter and an FIR filter requires 34 taps to satisfy the specifications of the proposed decimation filter. The effective numbers of taps for the /3-band IIR filter and the half-band FIR filter of the proposed decimation filter are 6 and 8, respectively. Thus, the total number of taps of the decimation filters is 4, which is 59% reduction in hardware compared to the conventional decimation filter. By using (7) and (8), we find that the power dissipated by the proposed decimation filter is 34% less than the conventional filter. The proposed decimation filter has the least hardware and consumes the least power compared to other conventional decimation filters, which can be used for telecommunication applications. The first stage /3-band IIR filter has a wide transition bandwidth of 4.5 MHz to satisfy the stop-band requirement of 60 db and pass-band requirement of 0.00 db since it is operating at a sampling rate of 37.5 MHz as shown in Figure 2. The second stage half-band FIR filter operates at a sampling rate of 2.5 MHz and has a passband of 2.25 MHz with a transition bandwidth of 2.25 MHz. The final and desired response is generated by the second stage half-band FIR filter, which provides the required stop-band attenuation of 86 db and the pass-band attenuation of db as shown in Figure 3. Figure 2. The output of the first stage /3-band IIR filter. Figure 3. The output of the last stage half-band FIR filter. VII. CONCLUSION To obtain such a highly efficient decimation filter, we have considered different design techniques, such as polyphase implementation of multirate multistage half-band FIR filter, poly-phase realization of decimators and first order all-pass cascaded lattice one multiplier realization of /3-band IIR filter. The selection of the proposed decimation filter architecture results in a computationally efficient design compared to the conventional decimation filters, which were used for telecommunication applications. The designed multirate multistage /3-band IIR filter and the half-band FIR filter have achieved considerable reduction in hardware and power. The 464

6 decimation filter is designed and simulated using Simulink and DSP Blockset and implemented in FPGA Xilinx technology. The resulting decimation filter has 59% less hardware and consumes 34% less power compared to the conventional decimation filters. REFERENCES [] Djordje Babic, Jussi Vesma and Markku Renfors, Decimation by Non-integer Factor using CIC filter and Linear Interpolation, Proceedings of the 200Finnish Signal Processing Symposium. [2] H. Aboushady, Y. Dumonteix, M. Louerat and H. Mehrez, Efficient Poly-phase Decomposition of Comb Decimation Filters in Sigma-delta Analog to Digital Converters, IEEE Transaction on Circuits and Systems-II, vol. 48, No. 0, October 200. [3] Sanjit K. Mitra. Digital Signal Processing. A Computer Based Approach, McGraw Hill, New York. [4] James F. Kaiser, Sanjit K. Mitra. Handbook for Digital Signal Processing, John Wiley and Sons 993. [5] H. Johansson, On High Speed Recursive Digital Filters, EUSIPCO [6] M.D. Lutovac. Filter Design for Signal Processing, Prentice Hall, Upper Saddle River, New Jersey [7] Carol. J. Barrett, Low power Decimation Filter Design for Multi- Standard Transceiver Applications, M.S Thesis, University of California, Berkeley. 465