A High Performance Unified BCD and Binary Adder/Subtractor

Transcription

1 29 IEEE Computer Society Annual Symposium on VLSI A High Performance Unified and Binary Adder/Subtractor Anshul Singh,Aman Gupta,Sreehari Veeramachaneni, MB Srinivas* Centre for VLSI and Embedded System Technologies(CVEST), International Institute of Information Technology (IIIT),Gachibowli, Hyderabad, 532, India * Department Electronics and Communication Engg, Birla Institute of Technology and Science (BITS), Hyderabad Campus, Hyderabad, India {anshul_ singh, aman }@studentsiiitacin, srihari@researchiiitacin,srinivas@iiitacin Abstract Decimal data processing applications have grown exponentially in recent years thereby increasing the need to have hardware support for decimal arithmetic In this paper, an improved architecture for efficient Binary Coded Decimal () addition/subtraction is presented that performs binary addition/subtraction without any extra hardware The architecture works for both signed and unsigned numbers The design is runtime reconfigurable and maximum utilization of the hardware is a feature of the architecture Simulation results show that the proposed architecture is at least 32% better in terms of powerdelay product than the existing designs I INTRODUCTION Fast decimal data processing needs hardware that supports decimal arithmetic Recently, specifications for decimal floating point arithmetic have been added to the draft revision of the IEEEP75 standard for floating point arithmetic [2] Extensive work has been done on arithmetic especially on adders/subtractors Some of the initial contributions came from Schmooklar et al [] and Adiletta et al [3] Later, designs of combined and Binary adders were presented by Levine et al and Anderson The first signmagnitude adder/subtractor was designed by Grupe [] An area efficient signmagnitude adder was later developed by Hwang[8] as shown in Fig Area occupied by this design was least amongst all the previous designs Flora [5] followed the principle of carry select adders and came up with a design which concurrently calculated two results, one assuming the presence of an input carry and the other in its absence Fischer et al [] (Fig 2) later came up with a compact design that employed only one adder but the latency was a problem as it had to use an additional correction block N Invert the operand when a sign is detected A is added when both and N are positive F Input Stage F2 X Y Binary Adder Output Stage Figure 2 Fischer s proposal [] Subtract a when necessary During the last decade various adder/subtractor circuits have been developed for the IBM microprocessors based on the design presented by Haller et al [] This architecture is shown in Fig 3 Recently, Haller et al optimized the carry chain in the same architecture which slightly reduced the delay but with an increased area of the unit S C Operand AGS F3 N (Addend Input) Augend Input Digitwise Nine s Complimenter Operand N Dec Add Dec Sub Carry Input Bi B Ai A Y Binary ALU Ci Y Yi Y Ci C Y Decimal Cd Unit Y Ri R Binary Carry Out Decimal Carry Out N N N Digitwise N CY N N N Digitwise N CY Digital Carry Network Multiplexer Partial Sum Partial Sum Figure Hwang s proposal [8] Carry Out Figure3 Haller s Proposal [,7] /9 $25 29 IEEE DOI 9/ISVLSI29 2

2 The design of the Universal Adder (Fig ) proposed by DRHumberto et al [2] uses affective addition/subtraction operations on unsigned/signmagnitude, and various complement representations This design overcomes the limitations of previously reported approaches that produce some of the results in complement representation when operating on signmagnitude numbers The design has high latency Add N' ' EAdd XOR Decimal SUB N Add Bin N * N DC Logic Co Logic in Fig), which is used for group propagate and generate The CM block is basically the Black cell used in the proposed design It can be easily observed that the delay for generating the carry out from the CM is same as that for the second ripple carry adder thereby making the CM block redundant Further, replacement of CM3 block by the grey cell (GC) will reduce the hardware without affecting the functionality of the circuit A B A3 B3 A2 B2 A B Binary ADD/SUB Decimal Add Digitwise Coder Decimal Time CM2 CM DS (3/2) Counter Array CM3 Co Carry Adder Ci Add XOR Figure Humberto s Proposal [2] Sreehari et al [9] recently came up with the prefix logic based adders and proposed a novel unified binary addersubtractor [] which is considered as the fastest unified adder in the literature so far The architecture is divided into three major parts, the precomputation stage, the prefix network and the postcomputation stage This architecture is illustrated in Fig5 The precomputation block consists of logic to compute propagate and generate signals for both and Binary addition/subtraction Bn An Bn B3 A3 An B2 A2 B A Figure The Existing Block [9] Wide varieties of prefix networks are available depending on the requirements of the designer Sklansky network is chosen by the authors for reduction in delay The postcomputation block proposed by Sreehari et al [] (Fig 7) uses a bit CLA to add the two numbers to calculate the sum/difference and the carry out bits for each stage But these bits are already calculated in the precomputation block and the prefix network thereby making more than half of the post computation block redundant Removing these redundancies from the design can increase the performance of the architecture considerably for each stage A s B s B B2 B3 B PREFIX NETWORK A A2 A3 A 's Complement Cin Cin OpSelect / / / / / OpSelect bit CLA Full Adder Sum/Difference Figure5 Architecture of the existing Unified and Binary Adder/Subtractor [] The precomputation stage of the architecture is not clearly presented by the authors in the paper [] and it is assumed that they have used the same block presented in [9] The block uses a Carry Merge block, CM (as shown B k Corrector for Subtractor Cout Corrector for Adder / DIFFERENCE Figure7 Post Computation Block [] 22

3 This paper presents a modified version of this unified adder and is shown to perform better by at least 32% in powerdelay product The rest of the paper is organized as follows: Section 2 gives description of the algorithm for the unified adder while section 3 describes the proposed architecture Simulation results for the proposed and existing circuits are given in section and comparisons are carried out II Algorithm for Unified /Binary Adder/Subtractor The main objective of the algorithm is to perform efficient addition/subtraction But in the proposed design the binary addition/subtraction is automatically taken care of without any extra hardware As digits are bits in length, all the operations, be it addition/subtraction or binary addition/subtraction, are done on bit numbers The algorithm divides the proposed design into three major parts, the Block, the Prefix Block and the Block as shown in the Fig 8 The block generates signals named propagate (P) and generate (G) for every bits These signals are used by the prefix network for generating the carry out for each stage The P and G for a stage denote whether the stage propagates or generates the carry/borrow respectively Along with generating these signals, the sum/difference of the bit numbers is obtained that is directly used by the correction logic unlike the previous design [] The block itself uses prefix logic to generate the P and G signals for bit numbers A B = 9 A B > Figure9 Examples of addition illustrating the concept of bit propagate and generate For Binary addition/subtraction and subtraction, P* = if C D = 5 (C and D are bit numbers) G* = if C D > 5 For the case of subtraction, D is the 2 s complement of the original subtrahend For subtraction P* and G* remain the same as in binary addition/subtraction because subtraction is treated as Binary subtraction for the first two stages These control signals are then sent to the prefix network which calculates the group propagate and generate using the formula G i:j = G i:k P i:k G k:j P i:j = P i:k P k:j where i k > j BN(N3) AN(N3) B85 A85 B A Block K Block 2 Block SN(N3) S85 S K 2 C D = Prefix Network C D > CK SN(N3) C2 S85 C S Block K Block 2 Block Figure Example of Binary addition/subtraction illustrating the concept of bit propagate and generate for subtraction / Binary addition/subtraction ON(N3) O85 Figure8 Architecture of Unified /Binary Adder/Subtractor O The concept of propagate and generate for different cases are illustrated below with equations and examples For addition, P = if A B = 9 (A and B are bit numbers) G = if A B > 9 The group P k: and G k: bits denote whether the first k stages propagate or generate the carry/borrow G k: denotes the carry out of the k th stage ie C k = G k: where C k is the carry out of the k th stage After all the carry/borrow bits are obtained, these are fed to the correction stage which along with the sum/difference bits from the block gives out the final result The first operation in the correction block is to add the incoming carry/borrow from the previous stage to the sum/difference bits This is implemented using carry select adder to reduce 23

4 S S p:3,g:3 g2: S S the delay After this stage the correct binary outputs are obtained but for addition/subtraction further corrections are to be made to obtain the correct result For addition () 2 or () is added to the binary sum if it exceeds () 2 or (9) to get the correct sum subtraction in the first block is treated as binary subtraction and the difference is obtained by the 2 s complement technique The only thing which has to be taken care of is that the magnitude of subtrahend should always be smaller than that of the minuend If a digit of the minuend is greater than that of subtrahend the binary output for that digit is the correct output and there is no need for any correction But if a digit of the subtrahend is greater than the minuend then () 2 or () has to be added to the binary output for that digit to get the correct difference To detect the relative magnitude of the minuend and the subtrahend of a block, the carry out of that stage is checked The following example illustrates the above algorithm Let A (minuend) = 5 5 B (subtrahend) = In format: A = B = Treating these numbers as binary, 2 s complement of B, say C is taken C = Next the subtrahend is added to the minuend and the correction is done if needed Carry out, no correction needed is when the effective operation is subtraction and when the effective operation is addition III Proposed Architecture of the Unified /Binary Adder/Subtractor The architecture, as discussed before, consists of three major blocks ie the block, the Prefix block and the block (Fig8) The architecture of the block is shown in the Fig 2 Each block takes in 8 bits, bits of each number and generates the propagate and generate signals for addition (P and G) and for subtraction/binary addition/subtraction (P* and G*) and also the sum or difference bits (S to S in the below case) The logic diagram of the full adder, BC (black cell) and GC (grey cell) are given in Fig 3 For the case of /Binary subtraction, 2 s complement of the subtrahend is calculated by inverting the bits of the subtrahend and adding to the adder generating the least significant bit in the first block (least significant) as shown in Fig 2 The rest of the P G blocks only take complements of the subtrahend and do not add To choose between the two kinds of propagate and generate a multiplexer is used at the end of each block A B SUB/ADD SUB/ADD SUB/ADD B3 B2 A3 A2 A B SUB/ADD Bs As OpSelect p,g S p3,g3 S No carry out, correction needed BC A C P* G* GC g:/cout G P Correct Binary output ADD/ELSE Output to Prefix Network Correct output Figure Illustrating the proposed algorithm for subtraction Figure2 The block Hence the final result = (37) A B The signed numbers are taken care by the control logic at the beginning which takes the two sign bits and OpSelect (Operation Select) as inputs to compute the control signal (SUB/ADD) which specifies the effective operation to be performed by the hardware The effective operation to be performed is calculated by the below equation SUB/ADD = As Bs OpSelect where OpSelect is when the operation is subtraction and when the operation is addition and As and Bs are the sign bits of the numbers under operation The control signal SUB/ADD XORXNOR Cin Sum Cout Figure3 (a) Full adder 2

5 Gk:j Pi:k Gi:k S S S Gk:j Pi:k Gi:k Pk:j C Gi:j Gi:j Pi:j O O3 O2 O Figure5 Gate level diagram of correction unit for Addition (b) (c) Figure3 (b) Grey Cell (c) Black Cell The propagate and the generate signals produced by the block are then sent to the prefix network The selection of the prefix network can be made according to the requirements of area, power and delay from the wide range available in literature For simulation purposes Sklansky network is chosen for the design [3] The prefix network generates the group generate for each stage which is the carry out of that stage Carry out of nth stage is denoted by C n After all the carry/borrow bits are obtained, these are fed to the correction stage which along with the sum/difference bits from the block gives out the final result which is shown in Fig The first operation in the correction block is to add the incoming carry/borrow from the previous stage to the sum/difference bits This is implemented using carry select adder to reduce the delay After this stage the correct binary outputs are obtained but for addition/subtraction, corrections need to be made to obtain the correct result For the addition the correction is done by adding () 2 and for subtraction the correction is done by adding () 2 to the correct binary output whenever needed The logic diagram of the two correction units is shown in Fig 5 and Fig C S S Carry select adder Logic for Addition D Logic for Subtraction Cin (C) S S(C) (C) (C) Figure Gate level diagram of correction unit for Subtraction For the binary addition/subtraction the output of the carry select adder in the correction block gives the final result IV Simulations and Results The analysis of all the architectures tabulated below has been carried out by performing simulation runs on HSPICE using 5nm CMOS technology Simulations are performed for 32 bit adders/subtractors All the circuits are simulated at 2V at a frequency of 5 MHz The simulation results are shown in Table TABLE I Average Delay, Power, PowerDelay Product and Area of various architectures Architecture Delay ( sec) Power ( watt) Power Delay Product ( ) S Area (no of mosfets) Humberto[2] Haller [7] Sreehari [] Proposed D B /Binary O Figure Block ADD/SUB It is clear from the above Table that the proposed design has an improvement of 75% in terms of delay and is 8% better in terms of power giving it a 32% improvement in powerdelay product over the most efficient architecture in the literature 25

6 V Conclusion This paper presented a modified architecture for fast addition/subtraction that performs binary addition/subtraction without any extra hardware The design is runtime reconfigurable and maximum utilization of the hardware is a feature of the architecture All the blocks have been designed to work with least delay The proposed architecture shows, on an average, an improvement of 32% in powerdelay product over the most efficient architecture in the literature REFERENCES [] MSSchmookler and A Weinderger Decimal Adder for Directly Implementing Addition Utilizing Logic Circuitry, International Business Machines Corporation, US patent 32955, pages 9, Dec 97 [2] IEEE standard for floatingpoint arithmetic IEEE SC, Oct 2 at [3] M J Adiletta and V C Lamere Adder Circuit Digital Equipment Corporation, US patent 853, pages 8, Jul 989 [] H Fischer andw Rohsaint Circuit Arrangement for Adding or Subtracting Operands Coded in Code or BinaryCode, Siemens Aktiengesellschaft, US patent 523, pages 9, Sep 992 [5] Flora, Laurence P, Fast /Binary Adder, US Patent 57 [] W Haller, U Krauch, and H Wetter Combined Binary/Decimal Adder Unit International Business Machines Corporation, US patent , pages 9, Jul 999 [7] W Haller, W H Li, M R Kelly, and H Wetter Highly Parallel Structure for Fast Cycle Binary and Decimal Adder Unit International Business Machines Corporation, US patent 2/3289, pages 8, Feb 2 [8] S Hwang HighSpeed Binary and Decimal Arithmetic Logic Unit, American Telephone and Telegraph Company, AT&T Bell Laboratories, US patent 85, pages, Sep 989 [9] Sreehari Veeramachaneni, M Keerthi Krishna, L Avinesh, P Sreekanth Reddy, MB Srinivas, Novel HighSpeed Digit Adders Conforming to IEEE 75r Format, IEEE Computer Society Annual Symposium on VLSI (ISVLSI 7), pages 3335, Mar 27 [] Sreehari Veeramachaneni, M, Kirthi Krishna; V, Prateek G, S Subroto, S, Bharat, MBSrinivas, A Novel CarryLook Ahead Approach to a Unified and Binary Adder/Subtractor, 2st International Conference on VLSI Design 28, pages 57552, Jan 28 [] U Grupe Decimal Adder, Vereinigte Flugtechnische WerkeFokker gmbh, US patent , pages, Jan 97 [2] DRHumberto Calderón, G N Gaydadjiev, S Vassiliadis, Reconfigurable Universal Adder, Proceedings of the IEEE International Conference on ApplicationSpecific Systems, Architectures, and Processors (ASAP 7), pages 89, July 27 [3] J Sklansky, Conditionalsum addition logic, IRE Trans Electronic Computers, vol EC9, pages 2223, June 9 2