Design of FPGA Based Radix 4 FFT Processor using CORDIC
|
|
- Andrew Nash
- 5 years ago
- Views:
Transcription
1 Design of FPGA Based Radix 4 FFT Processor using CORDIC Chetan Korde 1, Dr. P. Malathi 2, Sudhir N. Shelke 3, Dr. Manish Sharma 4 1,2,4 Department of Electronics and Telecommunication Engineering, DYPCOE, Akurdi, Pune, India 3 Research Division, JDM Design Technology, Nagpur, India chetan.cik@gmail.com 1, malathijesudason@ymail.com 2, sudhirshelke1976@gmail.com 3, manishsharma.mitm@gmail.com 4 Abstract - The Fast Fourier Transform (FFT) is an efficient algorithm for computing the Discrete Fourier Transform and requires less number of computations than that of direct evaluation of Discrete Fourier Transform (DFT). It has several applications in signal processing. But, because of the complexity of the processing algorithm of FFT, recently various radix-r FFT algorithms have been proposed to meet real-time processing requirements and reduce hardware complexity. The FFT processor is a critical block in all multi-carrier systems used primarily in the mobile environment. The main requirement of these systems is low power FFT architectures. This work proposes design of FFT processor using Coordinate Rotation Digital Computer (CORDIC) algorithm to reduce complexity of hardware and improve performance of processing, which will be synthesized on Field Programmable Gate Array. The purpose of this work is to obtain an area efficient description of FFT processor. Keywords - FFT, Radix 4, Radix 2, CORDIC, VHDL, FPGA. 1. INTRODUCTION The Digital signal processing has been dominated by microprocessors, because of some design feature enhancements in microprocessor like Special addressing modes and single cycle multiply-accumulate instructions. Though microprocessors are more flexible with low cost, but they are not fast enough for Digital Signal Processing (DSP) tasks. The arrival of reconfigurable logic computers offers hardware solutions for higher speed at cost which are less than traditional software approach. Unfortunately, algorithms used for these microprocessor based systems cannot be mapped into hardware. In such hardware efficient algorithms, there is a class of solutions for trigonometric functions that uses shifts and additions in its operation. The trigonometric functions are calculated by using vector rotations, while other functions like square root are realized by using an incremental expression. So, implementation of all these function in the hardware is difficult. In digital signal processing and communication systems, Discrete Fourier Transform (DFT) is one of the core operations. Many fundamental algorithms can be realized by DFT, such as spectrum estimation, correlation and convolution etc. Furthermore, DFT is widely used in standard embedded system applications such as wireless communication protocols requiring Orthogonal Frequency Division Multiplexing, Radar image processing using Synthetic Aperture Radar and Software Defined Radio etc. But, because of computational complexity of DFT it is difficult to implement. In practice, Fast Fourier transform (FFT) is used for reducing the complexity of computations. For FFT processors, butterfly operation is the most computationally demanding stage. Traditionally, a butterfly unit is composed of complex adders and multipliers. These multipliers are usually the speedup bottleneck in the pipeline of the FFT processor. The CORDIC algorithm is an alternative method to realize the butterfly operation without using any dedicated multiplier hardware. The CORDIC algorithm is versatile and hardware efficient since it requires only addition and shift operations, which makes FFT's butterfly operations more suitable. This CORDIC algorithm is further used in Radix-4 FFT for faster computation. While converting samples taken in real time into equivalent frequency domain samples, FFT computation is used in which twiddle factor computation is done using CORDIC algorithm. By the use of this CORDIC-based FFT processor, only twiddle factor angles of butterfly operation will store in a ROM and no need to store actual twiddle factors in a ROM, so memory requirement will be reduced automatically. Vol. 5(1), Jan June 2015@ ISSN
2 The Coordinate Rotation Digital Computer algorithm is a well-known technique to perform various basic arithmetic operations including trigonometric function computation, vector magnitude estimation, polar to rectangular conversions etc. Also for so many applications CORDIC processing units is used to deliver superior performance when compared with more conventional approaches. This is due to the fact that many advanced algorithms can be interpreted as generalized computation, for which CORDIC is especially suited to. So, the CORDIC algorithm is used to realize butterfly operation of FFT, which eliminates the need for storing twiddle factors and only need to store its angle, which helps to save a lot of hardware compared to its counterparts employing other techniques. It is preferred due to its simple operations, low cost and less complexity. Conventional CORDIC-based FFT processor needs a dedicated memory bank to store the necessary twiddle factor angles for the rotation. This study proposes a modified CORDIC algorithm for FFT processors which eliminates the need for storing the twiddle factor angles. With this approach, memory requirements of an FFT processor can be reduced. Memory reduction improves with the increased radix size. Furthermore, the angle generation circuit consumes less power consumption than angle memory access. Hence, system throughput will not change by using modified CORDIC angle calculation. Fig point Radix-4 FFT DIT algorithm [9] 2. RADIX-4 FFT ALGORITHM Radix-4 algorithm makes use of 4 as their base. They can be seen to be special case of Radix-2 algorithms. With Radix-4 algorithms, the number of computations involved gets reduced considerably, compared with the Radix-2 algorithm. Figure (1) shows an example of Radix-4 Decimation in Time (DIT) method used for N=16 points FFT algorithm. As shown in FFT flow-graph inputs are in normal order while the outputs are in digit-reversed order. At input side the samples are taken from time domain which are processed with Radix-4 FFT and get equivalent components in frequency domain. The numbers over flow lines indicates the twiddle factor to be multiplied with the samples. A Radix-r FFT uses N/r Radix-r butterflies for each stage and has log r (N) stages. For example, in this case for 16 point Radix-4 FFT requires k=2 stages. Fig. 2 The basic butterfly operations for stage 1 Radix-4 FFT algorithm. Figure (2) (a) and (b) shows the basic butterfly structure of Radix-4 which have four inputs and four outputs, inputs are as x(n), x(n + N/4), x(n + N/2) and x(n + 3N/4) outputs are in digit reversed order X(k). The signal flow graph of Radix-4 DIT butterfly operation is illustrated in figure (3). Radix-4 algorithms have a computational advantage over Radix-2 algorithms because one Radix-4 butterfly does the work of four Radix-2 butterflies and Radix-4 butterflies requires only three complex multipliers compared to four complex multipliers of four Radix-2 butterflies. The arithmetic kernel of Radix- 4 DIT FFT is the buttery operation defined as Vol. 5(1), Jan June 2015@ ISSN
3 X 0 = P0 +W 1 +W 2 +W 3. (1) X 1 = P0 - jw 1 - W 2 + jw 3. (2) X 2 = P0 - W 1 + W 2 - W 3. (3) X 3 = P 0 + jw 1 - W 2 - jw 3. (4) implementations, CORDIC enables most of the code and data to be shared between routines for trigonometric and hyperbolic functions, helping to conserve memory. CORDIC algorithm is often used to implement rotations needed in modulators and demodulators. Here, CORDIC is used to calculate sine and cosine term of twiddle factor. CORDIC works by rotating the coordinate system through constant angles until the angle is reduces to zero. The angle offsets are selected such that the operations on X and Y are only shifts and adds. CORDIC algorithm performs a planar rotation. Graphically, planar rotation means transforming a vector (Xi, Yi) into a new vector (Xj, Yj). [11] Figure (3): Signal flow graph of Radix-4 DIT butterfly 3. CORDIC In 1959, Jack E. Volder introduces The CORDIC algorithm for implementing a real-time navigation computer for aeronautical applications. The algorithm was initially formulated for computing the values of trigonometric functions. In early 1970s the CORDIC techniques were extended to exponential, logarithmic, forward and inverse circular and hyperbolic functions, ratios and square roots etc., (Walther 1971). Its concepts have also been developed to include calculation of the Discrete Fourier Transform (Despain 1974). More recently (Bajard 1994) efficient hardware technique known as BKM for computing complex exponentials and trigonometric functions was proposed and has since been very widely applied.[7] In contrast, CORDIC algorithms need only adders, shifters and comparators for computing a wide range of elementary functions. The method is especially efficient when fixed point implementations of signal processing algorithms on hardware are considered. For example, CORDIC is extremely popular in hardware accelerators and also in SIMD realizations. Furthermore, almost all functional calculators employ CORDIC. Also, CORDIC is a good choice for hardware solutions such as FPGA in which cost (gate count) minimization is more important than throughput maximization. In software Figure (4): Rotate vector (Xi, Yi) to (Xj, Yj) Using a matrix form, a planar rotation for a vector of (Xi, Yi) is defined as (5) The angle rotation can be executed in several steps, using an iterative process. Each step completes a small part of the rotation. Many steps will compose one planar rotation.[11] A single step is defined by the following equation (6) Equation (6) can be modified by eliminating the factor (7) Equation (7) requires three multiplies, compared to the four needed in equation 6. Additional multipliers can be eliminated by selecting the angle steps such that the tangent of a step is a power of 2. [11] Multiplying or dividing by a power of 2 can be implemented using a Vol. 5(1), Jan June 2015@ ISSN
4 simple shift operation. The angle for each step is given by (8) All iteration-angles summed must equal the rotation angle. Where, (9) (10) (16) At this point a new variable called 'Z' is introduced. Z represents the part of the angle which has not been rotated yet. (17) For every step of the rotation Sn is computed as a sign of Zn. (18) This results in the following equation for Combining equation (7) and (11) results in (11) (12) By combining equations (9) and (18) results in a system which reduces the not rotated part of angle to zero. Sine and Cosine can be calculated using the first CORDIC scheme which calculates By using the following values as inputs (19) Besides for the coefficient, the algorithm has been reduced to a few simple shifts and additions. The coefficient can be eliminated by pre-computing the final result. The first step is to rewrite the coefficient. (13) The second step is to compute equation (13) for all values of 'n' and multiplying the results, which we will refer to as K. (14) is constant for all initial vectors and for all values of the rotation angle. It is normally referred to as the congregate constant. The derivative P (approx ) is defined here because it is also commonly used. We can now formulate the exact calculation the CORDIC performs. [11] (15) Because the coefficient K is pre-computed and taken into account at a later stage, equation 12 may be written as (20) Y i = 0 (21) Z i = 0 (22) Then, the core calculates (23) The input Z takes values from -180degrees to +180 degrees where, 0x8000 = -180 degrees 0xEFFF = +180 degrees But the core only converges in the range -90 degrees to +90 degrees. The other inputs and the outputs are all in the range of -1 to +1. The congregate constant P represented in this format results in: (24) For example, calculate sine and cosine term for 45 degrees. First the angle has to be calculated 360 o = 2 26 (For 360 degree rotaion) So for, 1 = Vol. 5(1), Jan June 2015@ ISSN
5 Therefore for 45 o, Then, core will calculates the following sine and cosine values for Zi = 8192, Sin: (dec) = 5A82 (hex) Cos: (dec) = 5A83 (hex) Table (2): List of IO Ports for Sine/Cosine CORDIC Core PORT WIDTH DIRECTION DESCRIPTION CLK 1 INPUT SYSTEM CLOCK ENA 1 INPUT CLOCK ENABLE SIGNAL AIN 16 INPUT ANGLE INPUT COS 16 OUTPUT COSINE OUTPUT SIN 16 OUTPUT SINE OUTPUT The outputs represent values in the -1 to +1 range. The results can be derived as follows 2 15 = 1.0 Table (1) shows angle calculation for some common values of degree. Although the core is very accurate small errors can be introduced by the algorithm (see example and results table). This should be only a problem when using the core over the entire output range, because the difference between +1 (0x7FFF) and -1 (0x8000) is only 1bit.[11] Table 1: Sin/Cos outputs for some common angles SIN 0X01CC 0X3FFC 0X5A82 0X6EDC 0X8000 COS 0X8000 0X6EDD 0X5A83 0X4000 0X01CC SIN COS Fig. 6 RTL view of sine and cosine generation unit of CORDIC 1.1 CORDIC simulation 4. SIMULATION RESULT By using VHDL, CORDIC is synthesize and simulated on Altera cyclone II FPGA development board. So, proposed CORDIC is shown as Fig. 5 PIN diagram of Sine/Cosine CORDIC Core Fig. 7 Compilation report of CORDIC 1. For Angle 0 degree, Sin and Cos shows the desired results at the 15th clock pulse. Timeline shows the span of 15 clock pulses. Vol. 5(1), Jan June 2015@ ISSN
6 Fig. 8 Simulation result for 0 Degree. 2. Angle 30 degrees. (1555 Hex) Fig. 9 Simulation result for 30 Degree Now angles are provided at every clock pulse to show the pipeline strategy. So the output for the 45 degrees angle will take 15 clock pulses and then the output changes at every next pulse for the next four input angles. Fig. 11 RTL view of Radix 4 FFT using CORDIC 4.3 Result Summary From above simulation results this work concluded in the following table Table 3 : Summary of FPGA implementations of Radix 4 FFT using CORDIC algorithm. Fig. 10 Simulation result for all Degree values (0, 30, 45, 60, and 90) 4.2 Simulation of Radix 4 FFT using CORDIC Parameter Number of used memory Slices/Area Core Dynamic Power Static Power Clock Frequency Throughput Throughput/Area = Xilinx ISE 14.7 Value 32/3360 (1%) 1092/12480 (8%) W W M Hz GB/sec 0.1 MB/sec From above Table, can concluded that the Radix 4 FFT using CORDIC on Xilinx xc5vlx20t-2ff323 of Vertex 5 family gives optimized area of 1092(8%) slices, Core dynamic power w, Gb/sec of throughput and clock frequency of MHz. 5. APPLICATIONS Fig. 11: Summary report of Radix 4 FFT using CORDIC 1. Television terrestrial broadcasting systems. 2. Phase correlation system. 3. Mobile receiver. Vol. 5(1), Jan June 2015@ ISSN
7 4. Implementation of digital communication system. 4. Fault characterization and classification. 6. Radar. 7. Medical Imaging a. X-ray computed tomography (CT). b. Magnetic Resonance Imaging (MRI). 6. CONCLUSION Radix-4 FFT processor using CORDIC architecture is proposed. For generation of twiddle factor CORDIC algorithm is used which helps to reduce memory size. Various parts of FFT architecture such as Butterfly unit, CORDIC model are discussed. Proposed research work emphasize on the use of techniques to reduce the computational complexity of processor design and algorithm used which result into improvement of the design significantly. REFERENCES [1] Yasodai A., Ramprasad A. V., "A new memory reduced Radix-4 CORDIC processor for FFT operation", IOSR Journal of VLSI and Signal Processing, Volume 2, Issue 5, May-Jun [2] V. Charishma, K. Sreekanth Yadav, Neelima koppala. "Design and simulation of 64 Point FFT using Radix 4 algorithm for FPGA implementation", International Journal of Engineering Trends and Technology, Volume 4, Issue 2, [3] M. Vidya, M. Vijaya kumar, G. Sriramulu. "Design and VLSI implementation of a radix-4 64-point FFT processor", International Journal of Research in Computer and Communication technology, Volume 1, Issue 7, December [4] A. S. Padekar, S. S. Belsare, "Design of a CORDIC based radix-4 FFT processor", International Journal of Computer Science and Information Technologies, Volume 5, [5] Hsi-Chin, Hsin Tze-Yun Sung, Lu-Ting Ko, "Reconfigurable VLSI architecture for FFT processor", WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS, Volume 8, Issue 6, June [6] Javier Valls, "The use of CORDIC in software defined radios: A tutorial", Sep [7] J. E. Volder. "The CORDIC trigonometric computing technique", IEEE Communications Magazine, Volume 8, [8] Erdal Oruklu, Xin Xiao and Jafar Saniie, "Reduced memory and low power architectures for CORDICbased FFT processors", Springer Science and Business Media, pp , 16 April [9] Ajay S. Padekar, Prof. S. S. Belsare, "Radix-4 FFT Architecture", International Journal of Advanced Research in Computer Science and Software Engineering, Volume 4, Issue 5, May [10] Wang Mingxing, Shi Jiangi, Tian Yinghui, Yang Zhe, "A Novel design of 1024-point pipelined FFT processor based on CORDIC algorithm", Intelligent System Design And engineering Application (ISDEA) 2012 second International Conference on Digital Object Identifier, pp , 2012 [11] Richard Herveille, "Cordic Core Specification", Rev. 0.3, 11-June-15. Vol. 5(1), Jan June 2015@ ISSN
Low Power and Memory Efficient FFT Architecture Using Modified CORDIC Algorithm
Low Power and Memory Efficient FFT Architecture Using Modified CORDIC Algorithm 1 A.Malashri, 2 C.Paramasivam 1 PG Student, Department of Electronics and Communication K S Rangasamy College Of Technology,
More informationInternational Journal of Innovative and Emerging Research in Engineering. e-issn: p-issn:
Available online at www.ijiere.com International Journal of Innovative and Emerging Research in Engineering e-issn: 2394-3343 p-issn: 2394-5494 Design and Implementation of FFT Processor using CORDIC Algorithm
More informationSTUDY OF A CORDIC BASED RADIX-4 FFT PROCESSOR
STUDY OF A CORDIC BASED RADIX-4 FFT PROCESSOR 1 AJAY S. PADEKAR, 2 S. S. BELSARE 1 BVDU, College of Engineering, Pune, India 2 Department of E & TC, BVDU, College of Engineering, Pune, India E-mail: ajay.padekar@gmail.com,
More informationImplementation of FFT Processor using Urdhva Tiryakbhyam Sutra of Vedic Mathematics
Implementation of FFT Processor using Urdhva Tiryakbhyam Sutra of Vedic Mathematics Yojana Jadhav 1, A.P. Hatkar 2 PG Student [VLSI & Embedded system], Dept. of ECE, S.V.I.T Engineering College, Chincholi,
More informationFPGA IMPLEMENTATION OF CORDIC ALGORITHM ARCHITECTURE
FPGA IMPLEMENTATION OF CORDIC ALGORITHM ARCHITECTURE Ramanpreet Kaur 1, Parminder Singh Jassal 2 Department of Electronics And Communication Engineering, Punjabi University Yadavindra College of Engineering,
More informationA Modified CORDIC Processor for Specific Angle Rotation based Applications
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 4, Issue 2, Ver. II (Mar-Apr. 2014), PP 29-37 e-issn: 2319 4200, p-issn No. : 2319 4197 A Modified CORDIC Processor for Specific Angle Rotation
More informationPerformance Analysis of CORDIC Architectures Targeted by FPGA Devices
International OPEN ACCESS Journal Of Modern Engineering Research (IJMER) Performance Analysis of CORDIC Architectures Targeted by FPGA Devices Guddeti Nagarjuna Reddy 1, R.Jayalakshmi 2, Dr.K.Umapathy
More informationFPGA Implementation of 16-Point Radix-4 Complex FFT Core Using NEDA
FPGA Implementation of 16-Point FFT Core Using NEDA Abhishek Mankar, Ansuman Diptisankar Das and N Prasad Abstract--NEDA is one of the techniques to implement many digital signal processing systems that
More informationFPGA Implementation of Discrete Fourier Transform Using CORDIC Algorithm
AMSE JOURNALS-AMSE IIETA publication-2017-series: Advances B; Vol. 60; N 2; pp 332-337 Submitted Apr. 04, 2017; Revised Sept. 25, 2017; Accepted Sept. 30, 2017 FPGA Implementation of Discrete Fourier Transform
More informationHigh Speed Radix 8 CORDIC Processor
High Speed Radix 8 CORDIC Processor Smt. J.M.Rudagi 1, Dr. Smt. S.S ubbaraman 2 1 Associate Professor, K.L.E CET, Chikodi, karnataka, India. 2 Professor, W C E Sangli, Maharashtra. 1 js_itti@yahoo.co.in
More informationFPGA Design, Implementation and Analysis of Trigonometric Generators using Radix 4 CORDIC Algorithm
International Journal of Microcircuits and Electronic. ISSN 0974-2204 Volume 4, Number 1 (2013), pp. 1-9 International Research Publication House http://www.irphouse.com FPGA Design, Implementation and
More informationVHDL Implementation of DIT-FFT using CORDIC
Available online www.ejaet.com European Journal of Advances in Engineering and Technology, 2015, 2(6): 98-102 Research Article ISSN: 2394-658X VHDL Implementation of DIT-FFT using CORDIC M Paavani 1, A
More informationAn Enhanced Mixed-Scaling-Rotation CORDIC algorithm with Weighted Amplifying Factor
SEAS-WP-2016-10-001 An Enhanced Mixed-Scaling-Rotation CORDIC algorithm with Weighted Amplifying Factor Jaina Mehta jaina.mehta@ahduni.edu.in Pratik Trivedi pratik.trivedi@ahduni.edu.in Serial: SEAS-WP-2016-10-001
More informationImplementation of Area Efficient Multiplexer Based Cordic
Implementation of Area Efficient Multiplexer Based Cordic M. Madhava Rao 1, G. Suresh 2 1 M.Tech student M.L.E College, S. Konda, Prakasam (DIST), India 2 Assoc.prof in ECE Department, M.L.E College, S.
More informationLOW-POWER SPLIT-RADIX FFT PROCESSORS
LOW-POWER SPLIT-RADIX FFT PROCESSORS Avinash 1, Manjunath Managuli 2, Suresh Babu D 3 ABSTRACT To design a split radix fast Fourier transform is an ideal person for the implementing of a low-power FFT
More informationAN FFT PROCESSOR BASED ON 16-POINT MODULE
AN FFT PROCESSOR BASED ON 6-POINT MODULE Weidong Li, Mark Vesterbacka and Lars Wanhammar Electronics Systems, Dept. of EE., Linköping University SE-58 8 LINKÖPING, SWEDEN E-mail: {weidongl, markv, larsw}@isy.liu.se,
More informationImplementation of CORDIC Algorithms in FPGA
Summer Project Report Implementation of CORDIC Algorithms in FPGA Sidharth Thomas Suyash Mahar under the guidance of Dr. Bishnu Prasad Das May 2017 Department of Electronics and Communication Engineering
More informationFPGA Based Design and Simulation of 32- Point FFT Through Radix-2 DIT Algorith
FPGA Based Design and Simulation of 32- Point FFT Through Radix-2 DIT Algorith Sudhanshu Mohan Khare M.Tech (perusing), Dept. of ECE Laxmi Naraian College of Technology, Bhopal, India M. Zahid Alam Associate
More informationRealization of Hardware Architectures for Householder Transformation based QR Decomposition using Xilinx System Generator Block Sets
IJSTE - International Journal of Science Technology & Engineering Volume 2 Issue 08 February 2016 ISSN (online): 2349-784X Realization of Hardware Architectures for Householder Transformation based QR
More informationA Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO
2402 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 6, JUNE 2016 A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO Antony Xavier Glittas,
More informationSine/Cosine using CORDIC Algorithm
Sine/Cosine using CORDIC Algorithm Prof. Kris Gaj Gaurav Doshi, Hiren Shah Outlines Introduction Basic Idea CORDIC Principles Hardware Implementation FPGA & ASIC Results Conclusion Introduction CORDIC
More informationSpeed Optimised CORDIC Based Fast Algorithm for DCT
GRD Journals Global Research and Development Journal for Engineering International Conference on Innovations in Engineering and Technology (ICIET) - 2016 July 2016 e-issn: 2455-5703 Speed Optimised CORDIC
More informationFPGA Implementation of a High Speed Multistage Pipelined Adder Based CORDIC Structure for Large Operand Word Lengths
International Journal of Computer Science and Telecommunications [Volume 3, Issue 5, May 2012] 105 ISSN 2047-3338 FPGA Implementation of a High Speed Multistage Pipelined Adder Based CORDIC Structure for
More informationLow-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units
Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units Abstract: Split-radix fast Fourier transform (SRFFT) is an ideal candidate for the implementation of a lowpower FFT processor, because
More informationFused Floating Point Arithmetic Unit for Radix 2 FFT Implementation
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 6, Issue 2, Ver. I (Mar. -Apr. 2016), PP 58-65 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Fused Floating Point Arithmetic
More informationIMPLEMENTATION OF FAST FOURIER TRANSFORM USING VERILOG HDL
IMPLEMENTATION OF FAST FOURIER TRANSFORM USING VERILOG HDL 1 ANUP TIWARI, 2 SAMIR KUMAR PANDEY 1 Department of ECE, Jharkhand Rai University,Ranchi, Jharkhand, India 2 Department of Mathematical Sciences,
More informationTHE orthogonal frequency-division multiplex (OFDM)
26 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 57, NO. 1, JANUARY 2010 A Generalized Mixed-Radix Algorithm for Memory-Based FFT Processors Chen-Fong Hsiao, Yuan Chen, Member, IEEE,
More informationModified CORDIC Architecture for Fixed Angle Rotation
International Journal of Current Engineering and Technology EISSN 2277 4106, PISSN 2347 5161 2015INPRESSCO, All Rights Reserved Available at http://inpressco.com/category/ijcet Research Article Binu M
More informationPipelined Quadratic Equation based Novel Multiplication Method for Cryptographic Applications
, Vol 7(4S), 34 39, April 204 ISSN (Print): 0974-6846 ISSN (Online) : 0974-5645 Pipelined Quadratic Equation based Novel Multiplication Method for Cryptographic Applications B. Vignesh *, K. P. Sridhar
More informationFFT/IFFTProcessor IP Core Datasheet
System-on-Chip engineering FFT/IFFTProcessor IP Core Datasheet - Released - Core:120801 Doc: 130107 This page has been intentionally left blank ii Copyright reminder Copyright c 2012 by System-on-Chip
More informationResearch Article Design of A Novel 8-point Modified R2MDC with Pipelined Technique for High Speed OFDM Applications
Research Journal of Applied Sciences, Engineering and Technology 7(23): 5021-5025, 2014 DOI:10.19026/rjaset.7.895 ISSN: 2040-7459; e-issn: 2040-7467 2014 Maxwell Scientific Publication Corp. Submitted:
More informationLinköping University Post Print. Analysis of Twiddle Factor Memory Complexity of Radix-2^i Pipelined FFTs
Linköping University Post Print Analysis of Twiddle Factor Complexity of Radix-2^i Pipelined FFTs Fahad Qureshi and Oscar Gustafsson N.B.: When citing this work, cite the original article. 200 IEEE. Personal
More informationComputing the Discrete Fourier Transform on FPGA Based Systolic Arrays
Computing the Discrete Fourier Transform on FPGA Based Systolic Arrays Chris Dick School of Electronic Engineering La Trobe University Melbourne 3083, Australia Abstract Reconfigurable logic arrays allow
More informationDesign of Delay Efficient Distributed Arithmetic Based Split Radix FFT
Design of Delay Efficient Arithmetic Based Split Radix FFT Nisha Laguri #1, K. Anusudha *2 #1 M.Tech Student, Electronics, Department of Electronics Engineering, Pondicherry University, Puducherry, India
More informationThe Serial Commutator FFT
The Serial Commutator FFT Mario Garrido Gálvez, Shen-Jui Huang, Sau-Gee Chen and Oscar Gustafsson Journal Article N.B.: When citing this work, cite the original article. 2016 IEEE. Personal use of this
More informationA CORDIC Algorithm with Improved Rotation Strategy for Embedded Applications
A CORDIC Algorithm with Improved Rotation Strategy for Embedded Applications Kui-Ting Chen Research Center of Information, Production and Systems, Waseda University, Fukuoka, Japan Email: nore@aoni.waseda.jp
More informationAnalysis of Radix- SDF Pipeline FFT Architecture in VLSI Using Chip Scope
Analysis of Radix- SDF Pipeline FFT Architecture in VLSI Using Chip Scope G. Mohana Durga 1, D.V.R. Mohan 2 1 M.Tech Student, 2 Professor, Department of ECE, SRKR Engineering College, Bhimavaram, Andhra
More informationFPGA Implementation of the CORDIC Algorithm for Fingerprints Recognition Systems
FPGA Implementation of the CORDIC Algorithm for Fingerprints Recognition Systems Nihel Neji, Anis Boudabous, Wajdi Kharrat, Nouri Masmoudi University of Sfax, Electronics and Information Technology Laboratory,
More informationAn Area Efficient Mixed Decimation MDF Architecture for Radix. Parallel FFT
An Area Efficient Mixed Decimation MDF Architecture for Radix Parallel FFT Reshma K J 1, Prof. Ebin M Manuel 2 1M-Tech, Dept. of ECE Engineering, Government Engineering College, Idukki, Kerala, India 2Professor,
More informationImplementation of a Unified DSP Coprocessor
Vol. (), Jan,, pp 3-43, ISS: 35-543 Implementation of a Unified DSP Coprocessor Mojdeh Mahdavi Department of Electronics, Shahr-e-Qods Branch, Islamic Azad University, Tehran, Iran *Corresponding author's
More informationDUE to the high computational complexity and real-time
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 15, NO. 3, MARCH 2005 445 A Memory-Efficient Realization of Cyclic Convolution and Its Application to Discrete Cosine Transform Hun-Chen
More informationHigh Performance Pipelined Design for FFT Processor based on FPGA
High Performance Pipelined Design for FFT Processor based on FPGA A.A. Raut 1, S. M. Kate 2 1 Sinhgad Institute of Technology, Lonavala, Pune University, India 2 Sinhgad Institute of Technology, Lonavala,
More informationA 4096-Point Radix-4 Memory-Based FFT Using DSP Slices
A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices Mario Garrido Gálvez, Miguel Angel Sanchez, Maria Luisa Lopez-Vallejo and Jesus Grajal Journal Article N.B.: When citing this work, cite the original
More informationFPGA Implementation of FFT Processor in Xilinx
Volume-6, Issue-2, March-April 2016 International Journal of Engineering and Management Research Page Number: 134-138 FPGA Implementation of FFT Processor in Xilinx Anup Tiwari 1, Dr. Samir Pandey 2 1
More informationDesign and Simulation of 32 and 64 Point FFT Using Multiple Radix Algorithm
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology ISSN 2320 088X IMPACT FACTOR: 6.017 IJCSMC,
More informationDesign of a Multiplier Architecture Based on LUT and VHBCSE Algorithm For FIR Filter
African Journal of Basic & Applied Sciences 9 (1): 53-58, 2017 ISSN 2079-2034 IDOSI Publications, 2017 DOI: 10.5829/idosi.ajbas.2017.53.58 Design of a Multiplier Architecture Based on LUT and VHBCSE Algorithm
More informationCORDIC Based DFT on FPGA for DSP Applications
CORDIC Based DFT on FPGA for DSP Applications Padma. V PG Scholar, Department of E.C.E SKIT College Srikalahasti, India Sudhakara Reddy. P Member IEEE Associate Professor, Department of E.C.E SKIT college
More informationEfficient Double-Precision Cosine Generation
Efficient Double-Precision Cosine Generation Derek Nowrouzezahrai Brian Decker William Bishop dnowrouz@uwaterloo.ca bjdecker@uwaterloo.ca wdbishop@uwaterloo.ca Department of Electrical and Computer Engineering
More informationIntroduction to Field Programmable Gate Arrays
Introduction to Field Programmable Gate Arrays Lecture 2/3 CERN Accelerator School on Digital Signal Processing Sigtuna, Sweden, 31 May 9 June 2007 Javier Serrano, CERN AB-CO-HT Outline Digital Signal
More informationTwiddle Factor Transformation for Pipelined FFT Processing
Twiddle Factor Transformation for Pipelined FFT Processing In-Cheol Park, WonHee Son, and Ji-Hoon Kim School of EECS, Korea Advanced Institute of Science and Technology, Daejeon, Korea icpark@ee.kaist.ac.kr,
More informationLow Power Complex Multiplier based FFT Processor
Low Power Complex Multiplier based FFT Processor V.Sarada, Dr.T.Vigneswaran 2 ECE, SRM University, Chennai,India saradasaran@gmail.com 2 ECE, VIT University, Chennai,India vigneshvlsi@gmail.com Abstract-
More informationModified Welch Power Spectral Density Computation with Fast Fourier Transform
Modified Welch Power Spectral Density Computation with Fast Fourier Transform Sreelekha S 1, Sabi S 2 1 Department of Electronics and Communication, Sree Budha College of Engineering, Kerala, India 2 Professor,
More informationImplementation of Lifting-Based Two Dimensional Discrete Wavelet Transform on FPGA Using Pipeline Architecture
International Journal of Computer Trends and Technology (IJCTT) volume 5 number 5 Nov 2013 Implementation of Lifting-Based Two Dimensional Discrete Wavelet Transform on FPGA Using Pipeline Architecture
More informationResearch Article Design and Implementation of Hybrid CORDIC Algorithm Based on Phase Rotation Estimation for NCO
Hindawi Publishing Corporation e Scientific World Journal Volume 214, Article ID 897381, 8 pages http://dx.doi.org/1.1155/214/897381 Research Article Design and Implementation of Hybrid CORDIC Algorithm
More informationImplementation techniques of CORDIC: a review
Implementation techniques of CORDIC: a review 1 Gadhiya Ravindra B., 2 Prof. Manisha C. Patel 1 PG Scholar, 2 Assistant Professor 1 Instrumentation and Control Department, 1 NL.D. College of Engineering,
More informationA Novel Distributed Arithmetic Multiplierless Approach for Computing Complex Inner Products
606 Int'l Conf. Par. and Dist. Proc. Tech. and Appl. PDPTA'5 A ovel Distributed Arithmetic Multiplierless Approach for Computing Complex Inner Products evin. Bowlyn, and azeih M. Botros. Ph.D. Candidate,
More informationVLSI Implementation of Low Power Area Efficient FIR Digital Filter Structures Shaila Khan 1 Uma Sharma 2
IJSRD - International Journal for Scientific Research & Development Vol. 3, Issue 05, 2015 ISSN (online): 2321-0613 VLSI Implementation of Low Power Area Efficient FIR Digital Filter Structures Shaila
More informationDESIGN METHODOLOGY. 5.1 General
87 5 FFT DESIGN METHODOLOGY 5.1 General The fast Fourier transform is used to deliver a fast approach for the processing of data in the wireless transmission. The Fast Fourier Transform is one of the methods
More informationImplementation Of Quadratic Rotation Decomposition Based Recursive Least Squares Algorithm
157 Implementation Of Quadratic Rotation Decomposition Based Recursive Least Squares Algorithm Manpreet Singh 1, Sandeep Singh Gill 2 1 University College of Engineering, Punjabi University, Patiala-India
More informationXilinx Based Simulation of Line detection Using Hough Transform
Xilinx Based Simulation of Line detection Using Hough Transform Vijaykumar Kawde 1 Assistant Professor, Department of EXTC Engineering, LTCOE, Navi Mumbai, Maharashtra, India 1 ABSTRACT: In auto focusing
More informationAn Implementation of Double precision Floating point Adder & Subtractor Using Verilog
IOSR Journal of Electrical and Electronics Engineering (IOSR-JEEE) e-issn: 2278-1676,p-ISSN: 2320-3331, Volume 9, Issue 4 Ver. III (Jul Aug. 2014), PP 01-05 An Implementation of Double precision Floating
More informationFast evaluation of nonlinear functions using FPGAs
Adv. Radio Sci., 6, 233 237, 2008 Author(s) 2008. This work is distributed under the Creative Commons Attribution 3.0 License. Advances in Radio Science Fast evaluation of nonlinear functions using FPGAs
More informationRUN-TIME RECONFIGURABLE IMPLEMENTATION OF DSP ALGORITHMS USING DISTRIBUTED ARITHMETIC. Zoltan Baruch
RUN-TIME RECONFIGURABLE IMPLEMENTATION OF DSP ALGORITHMS USING DISTRIBUTED ARITHMETIC Zoltan Baruch Computer Science Department, Technical University of Cluj-Napoca, 26-28, Bariţiu St., 3400 Cluj-Napoca,
More informationHIGH-PERFORMANCE RECONFIGURABLE FIR FILTER USING PIPELINE TECHNIQUE
HIGH-PERFORMANCE RECONFIGURABLE FIR FILTER USING PIPELINE TECHNIQUE Anni Benitta.M #1 and Felcy Jeba Malar.M *2 1# Centre for excellence in VLSI Design, ECE, KCG College of Technology, Chennai, Tamilnadu
More informationVLSI IMPLEMENTATION AND PERFORMANCE ANALYSIS OF EFFICIENT MIXED-RADIX 8-2 FFT ALGORITHM WITH BIT REVERSAL FOR THE OUTPUT SEQUENCES.
VLSI IMPLEMENTATION AND PERFORMANCE ANALYSIS OF EFFICIENT MIXED-RADIX 8-2 ALGORITHM WITH BIT REVERSAL FOR THE OUTPUT SEQUENCES. M. MOHAMED ISMAIL Dr. M.J.S RANGACHAR Dr.Ch. D. V. PARADESI RAO (Research
More informationResearch Article International Journal of Emerging Research in Management &Technology ISSN: (Volume-6, Issue-8) Abstract:
International Journal of Emerging Research in Management &Technology Research Article August 27 Design and Implementation of Fast Fourier Transform (FFT) using VHDL Code Akarshika Singhal, Anjana Goen,
More informationDigital Signal Processing with Field Programmable Gate Arrays
Uwe Meyer-Baese Digital Signal Processing with Field Programmable Gate Arrays Third Edition With 359 Figures and 98 Tables Book with CD-ROM ei Springer Contents Preface Preface to Second Edition Preface
More informationNovel design of multiplier-less FFT processors
Signal Processing 8 (00) 140 140 www.elsevier.com/locate/sigpro Novel design of multiplier-less FFT processors Yuan Zhou, J.M. Noras, S.J. Shepherd School of EDT, University of Bradford, Bradford, West
More informationFast Evaluation of the Square Root and Other Nonlinear Functions in FPGA
Edith Cowan University Research Online ECU Publications Pre. 20 2008 Fast Evaluation of the Square Root and Other Nonlinear Functions in FPGA Stefan Lachowicz Edith Cowan University Hans-Joerg Pfleiderer
More informationDesign of 2-D DWT VLSI Architecture for Image Processing
Design of 2-D DWT VLSI Architecture for Image Processing Betsy Jose 1 1 ME VLSI Design student Sri Ramakrishna Engineering College, Coimbatore B. Sathish Kumar 2 2 Assistant Professor, ECE Sri Ramakrishna
More informationParallel-computing approach for FFT implementation on digital signal processor (DSP)
Parallel-computing approach for FFT implementation on digital signal processor (DSP) Yi-Pin Hsu and Shin-Yu Lin Abstract An efficient parallel form in digital signal processor can improve the algorithm
More informationISSN Vol.02, Issue.11, December-2014, Pages:
ISSN 2322-0929 Vol.02, Issue.11, December-2014, Pages:1208-1212 www.ijvdcs.org Implementation of Area Optimized Floating Point Unit using Verilog G.RAJA SEKHAR 1, M.SRIHARI 2 1 PG Scholar, Dept of ECE,
More informationUser Manual for FC100
Sundance Multiprocessor Technology Limited User Manual Form : QCF42 Date : 6 July 2006 Unit / Module Description: IEEE-754 Floating-point FPGA IP Core Unit / Module Number: FC100 Document Issue Number:
More informationDesign and Simulation of 32 bit Floating Point FFT Processor Using VHDL
Design and Simulation of 32 bit Floating Point FFT Processor Using VHDL Mr.Roshan Pahune 1, Dr.Mrs.AnaghaRathkanthiwar 2 1 M.Tech Student [VLSI],Dept. of Electronics Engg, PCE, Nagpur, India 2 Associate
More informationEfficient Implementation of Low Power 2-D DCT Architecture
Vol. 3, Issue. 5, Sep - Oct. 2013 pp-3164-3169 ISSN: 2249-6645 Efficient Implementation of Low Power 2-D DCT Architecture 1 Kalyan Chakravarthy. K, 2 G.V.K.S.Prasad 1 M.Tech student, ECE, AKRG College
More informationAdaptive FIR Filter Using Distributed Airthmetic for Area Efficient Design
International Journal of Scientific and Research Publications, Volume 5, Issue 1, January 2015 1 Adaptive FIR Filter Using Distributed Airthmetic for Area Efficient Design Manish Kumar *, Dr. R.Ramesh
More informationINTEGER SEQUENCE WINDOW BASED RECONFIGURABLE FIR FILTERS.
INTEGER SEQUENCE WINDOW BASED RECONFIGURABLE FIR FILTERS Arulalan Rajan 1, H S Jamadagni 1, Ashok Rao 2 1 Centre for Electronics Design and Technology, Indian Institute of Science, India (mrarul,hsjam)@cedt.iisc.ernet.in
More informationENT 315 Medical Signal Processing CHAPTER 3 FAST FOURIER TRANSFORM. Dr. Lim Chee Chin
ENT 315 Medical Signal Processing CHAPTER 3 FAST FOURIER TRANSFORM Dr. Lim Chee Chin Outline Definition and Introduction FFT Properties of FFT Algorithm of FFT Decimate in Time (DIT) FFT Steps for radix
More informationDigital Signal Processing. Soma Biswas
Digital Signal Processing Soma Biswas 2017 Partial credit for slides: Dr. Manojit Pramanik Outline What is FFT? Types of FFT covered in this lecture Decimation in Time (DIT) Decimation in Frequency (DIF)
More informationFAST FOURIER TRANSFORM (FFT) and inverse fast
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004 2005 A Dynamic Scaling FFT Processor for DVB-T Applications Yu-Wei Lin, Hsuan-Yu Liu, and Chen-Yi Lee Abstract This paper presents an
More informationHIGH PERFORMANCE QUATERNARY ARITHMETIC LOGIC UNIT ON PROGRAMMABLE LOGIC DEVICE
International Journal of Advances in Applied Science and Engineering (IJAEAS) ISSN (P): 2348-1811; ISSN (E): 2348-182X Vol. 2, Issue 1, Feb 2015, 01-07 IIST HIGH PERFORMANCE QUATERNARY ARITHMETIC LOGIC
More informationDesign of a Floating-Point Fused Add-Subtract Unit Using Verilog
International Journal of Electronics and Computer Science Engineering 1007 Available Online at www.ijecse.org ISSN- 2277-1956 Design of a Floating-Point Fused Add-Subtract Unit Using Verilog Mayank Sharma,
More informationFast Block LMS Adaptive Filter Using DA Technique for High Performance in FGPA
Fast Block LMS Adaptive Filter Using DA Technique for High Performance in FGPA Nagaraj Gowd H 1, K.Santha 2, I.V.Rameswar Reddy 3 1, 2, 3 Dept. Of ECE, AVR & SVR Engineering College, Kurnool, A.P, India
More informationKeywords: Fast Fourier Transforms (FFT), Multipath Delay Commutator (MDC), Pipelined Architecture, Radix-2 k, VLSI.
ww.semargroup.org www.ijvdcs.org ISSN 2322-0929 Vol.02, Issue.05, August-2014, Pages:0294-0298 Radix-2 k Feed Forward FFT Architectures K.KIRAN KUMAR 1, M.MADHU BABU 2 1 PG Scholar, Dept of VLSI & ES,
More informationCORDIC Based FFT for Signal Processing System
CORDIC Based FFT for Signal Processing System Karthick S1, Priya P2, Valarmathy S3 1 2 Assistant Professor, Department of ECE, Bannari Amman Institute of Technology, Sathyamangalam, India PG Scholar ME-
More informationKeywords: Soft Core Processor, Arithmetic and Logical Unit, Back End Implementation and Front End Implementation.
ISSN 2319-8885 Vol.03,Issue.32 October-2014, Pages:6436-6440 www.ijsetr.com Design and Modeling of Arithmetic and Logical Unit with the Platform of VLSI N. AMRUTHA BINDU 1, M. SAILAJA 2 1 Dept of ECE,
More informationIMPLEMENTATION OF AN ADAPTIVE FIR FILTER USING HIGH SPEED DISTRIBUTED ARITHMETIC
IMPLEMENTATION OF AN ADAPTIVE FIR FILTER USING HIGH SPEED DISTRIBUTED ARITHMETIC Thangamonikha.A 1, Dr.V.R.Balaji 2 1 PG Scholar, Department OF ECE, 2 Assitant Professor, Department of ECE 1, 2 Sri Krishna
More informationAREA EFFIECIENT ALGORITHM FOR THE IMPLEMENTATION OF CONFIGURABLE FFT/IFFT IN FPGA
AREA EFFIECIENT ALGORITHM FOR THE IMPLEMENTATION OF CONFIGURABLE FFT/IFFT IN FPGA Arsha P.S. Department of ECE, Mohandas College of Engineering and Technology Abstract The core processing block of an OFDM
More informationA Novel Approach of Area-Efficient FIR Filter Design Using Distributed Arithmetic with Decomposed LUT
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735. Volume 7, Issue 2 (Jul. - Aug. 2013), PP 13-18 A Novel Approach of Area-Efficient FIR Filter
More informationFPGA Implementation of CORDIC Based DHT for Image Processing Applications
FPGA Implementation of CORDIC Based DHT for Image Processing Applications Shaik Waseem Ahmed 1, Sudhakara Reddy.P P.G. Student, Department of Electronics and Communication Engineering, SKIT College, Srikalahasti,
More informationRISC IMPLEMENTATION OF OPTIMAL PROGRAMMABLE DIGITAL IIR FILTER
RISC IMPLEMENTATION OF OPTIMAL PROGRAMMABLE DIGITAL IIR FILTER Miss. Sushma kumari IES COLLEGE OF ENGINEERING, BHOPAL MADHYA PRADESH Mr. Ashish Raghuwanshi(Assist. Prof.) IES COLLEGE OF ENGINEERING, BHOPAL
More informationIMPLEMENTATION OF OPTIMIZED 128-POINT PIPELINE FFT PROCESSOR USING MIXED RADIX 4-2 FOR OFDM APPLICATIONS
IMPLEMENTATION OF OPTIMIZED 128-POINT PIPELINE FFT PROCESSOR USING MIXED RADIX 4-2 FOR OFDM APPLICATIONS K. UMAPATHY, Research scholar, Department of ECE, Jawaharlal Nehru Technological University, Anantapur,
More informationDesign and Implementation of 3-D DWT for Video Processing Applications
Design and Implementation of 3-D DWT for Video Processing Applications P. Mohaniah 1, P. Sathyanarayana 2, A. S. Ram Kumar Reddy 3 & A. Vijayalakshmi 4 1 E.C.E, N.B.K.R.IST, Vidyanagar, 2 E.C.E, S.V University
More informationARCHITECTURAL DESIGN OF 8 BIT FLOATING POINT MULTIPLICATION UNIT
ARCHITECTURAL DESIGN OF 8 BIT FLOATING POINT MULTIPLICATION UNIT Usha S. 1 and Vijaya Kumar V. 2 1 VLSI Design, Sathyabama University, Chennai, India 2 Department of Electronics and Communication Engineering,
More informationVendor Agnostic, High Performance, Double Precision Floating Point Division for FPGAs
Vendor Agnostic, High Performance, Double Precision Floating Point Division for FPGAs Xin Fang and Miriam Leeser Dept of Electrical and Computer Eng Northeastern University Boston, Massachusetts 02115
More informationPower Optimized Programmable Truncated Multiplier and Accumulator Using Reversible Adder
Power Optimized Programmable Truncated Multiplier and Accumulator Using Reversible Adder Syeda Mohtashima Siddiqui M.Tech (VLSI & Embedded Systems) Department of ECE G Pulla Reddy Engineering College (Autonomous)
More informationIEEE-754 compliant Algorithms for Fast Multiplication of Double Precision Floating Point Numbers
International Journal of Research in Computer Science ISSN 2249-8257 Volume 1 Issue 1 (2011) pp. 1-7 White Globe Publications www.ijorcs.org IEEE-754 compliant Algorithms for Fast Multiplication of Double
More informationLow Latency CORDIC Architecture in FFT
Low Latency CORDIC Architecture in FFT Ms. Nidhin K.V, M.Tech Student, Ms. Meera Thampy, Assistant Professor, Dept. of Electronics & Communication Engineering, SNGCE, Kadayiruppu, Ernakulam, Kerala Abstract
More informationAbstract. Literature Survey. Introduction. A.Radix-2/8 FFT algorithm for length qx2 m DFTs
Implementation of Split Radix algorithm for length 6 m DFT using VLSI J.Nancy, PG Scholar,PSNA College of Engineering and Technology; S.Bharath,Assistant Professor,PSNA College of Engineering and Technology;J.Wilson,Assistant
More informationThree Dimensional CORDIC with reduced iterations
Three Dimensional CORDIC with reduced iterations C.T. Clarke and G.R. Nudd Department of Computer Science University of Warwick Coventry CV4 7AL United Kingdom Abstract This paper describes a modification
More information