International Journal of Innovative and Emerging Research in Engineering. e-issn: p-issn:

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1 Available online at International Journal of Innovative and Emerging Research in Engineering e-issn: p-issn: Design and Implementation of FFT Processor using CORDIC Algorithm Jignesh M Chikhaliya a, Prof. Chintan B Dave a, Jayprakash H Tiwari a a Vishwakarma Govt. Engg. College, Chandkheda, Ahmedabad, India ABSTRACT: Fast Fourier transform (FFT) is used for reducing the complexity of computations in Discrete Fourier Transform (DFT). Fast Fourier transform (FFT) is among the most widely used operations in digital signal processing. Often, a high performance FFT processor determines most of the design metrics in many applications such as image processing, sonar, general filtering, spread-spectrum communications, convolution, etc. Many of them require a good precision and real-time response. Software Defined Radio (SDR) and Synthetic Aperture Radar (SAR) are among the fastest growing application areas; in particular, Orthogonal Frequency-Division Multiplexing (OFDM) is currently a focus of research and development. Efficient hardware realization of FFT with small area, low-power dissipation and real-time computation is a significant challenge in portable devices. In this report, various FFT algorithms and architectures are described. Main goal of this dissertation is to reduce the cost of hardware. Thus, CORDIC based FFT architecture, where, need of twiddle factor angles storage is eliminated, is to be implemented during dissertation. Keywords: FFT algorithm, CORDIC, FPGA I. INTRODUCTION Fast Fourier transform (FFT) is used for reducing the complexity of computations in Discrete Fourier Transform (DFT). Fast Fourier transform (FFT) is among the most widely used operations in digital signal processing. Often, a high performance FFT processor determines most of the design metrics in many applications such as image processing, sonar, general filtering, spread-spectrum communications, convolution, etc. Many of them require a good precision and real-time response. Software Defined Radio (SDR) and Synthetic Aperture Radar (SAR) are among the fastest growing application areas [2]; in particular, Orthogonal Frequency-Division Multiplexing (OFDM) is currently a focus of research and development [3]. Efficient hardware realization of FFT with small area, low-power dissipation and realtime computation is a significant challenge in portable devices. A FFT processor consists of control logic (address generator for data and twiddle factor accesses), butterfly calculation units and a memory bank. For FFT processors, butterfly operation is the most computationally demanding stage. Generally, an FFT processor utilizes only one butterfly unit to perform all calculations iteratively, and the inplace memory access strategy is required for the least amount of memory. With in-place strategy, the outputs of a butterfly operation are stored back to the same memory location of the inputs, saving the memory usage by one half. However, correct memory addressing scheme is required to avoid the data conflict. Here, we implements an efficient addressing scheme to realize the Serial-in and Serial-out and in-place memory accessing; which produces an output at every clock cycle [4]. Traditionally, a butterfly unit consists of complex adders and multipliers. The butterfly operation can be realized by Coordinate Rotation Digital Computer (CORDIC) without using any dedicated multiplier hardware. CORDIC algorithm is suitable for the butterfly operations in FFT since it requires only add and shift operations, making it very hardware efficient. In the conventional FFT processor, a large ROM space is needed to store all the twiddle factors. To reduce the chip area, a twiddle factor generator has been proposed. The twiddle factor angles are stored in a ROM for the butterfly operation in a CORDIC-based FFT processor. Additionally, the CORDIC-based butterfly can be twice faster than traditional multiplier-based butterflies in VLSI implementations. In this study, we propose a new angle generation method and angles are generated on real time basis using proposed address decoding scheme. Here, there is no need of storing the twiddle factor angle values. By using the control signal which is based on the current FFT stage and the location of the butterfly in a stage, different twiddle factor angles can be generated in the simple and regular manner. With this approach, full memory requirements of an FFT processor can be reduced by more than 23%. Fundamentals of CORDIC algorithm and the design of CORDIC-based FFT processor are described in Section II. In Section III, the proposed memory efficient FFT algorithm and its hardware architecture are presented. 143

2 II. FFT AND CORDIC ALGORITHM The N-point DFT can be defined as, N 1 X[k] = x[n]. W N kn n=0 Where, k = 0,1,2..n, W N kn = e 2πkn/N ; In FFT, key operation is x[n]. W N kn, where W N kn = e 2πkn/N is known as Twiddle factor. x[n]. W N kn is equivalent to rotate x(n) by 2πkn/N. which can be realized easily by the CORDIC algorithm. Signal flow graph of 8-point Decimation-in-Frequency (DIF) Radix-2 FFT is shown in Fig. 1. Figure 1: Radix-2 DIF FFT using CORDIC Algorithm [6]. For N-point Radix-2 FFT, there are log2n stages and each stage contains N/2 butterfly operations. Transforming complex twiddle factor multiplications into CORDIC operations can eliminate the complex multiplications.[3] Therefore any complex multiplier based FFT architecture has its CORDIC based equivalent, which may provide a simpler implementation. In general, complex multiplications of the form given as Re(X ) j Im(X ) [Re(x) j Im(x)].e jθ, can be represented in matrix form as [ Re(X) Im(X) ] = [cosθ sinθ sinθ cosθ ] [Re(x) Im(x) ] According to CORDIC algorithm, [ x sinθ y ] = [cosθ sinθ cosθ ] [x y ] The CORDIC algorithm can be realized as an iterative sequence of shift operation and addition/subtractions. This algorithm is generalized to evaluate a set of the arithmetic functions, which includes multiplication, division, sine, cosine, arctangent, and hyperbolic functions as shown in below equation.[5] x n = x 0 cosθ y 0 sinθ y n = y 0 cosθ + x 0 sinθ This algorithm requires no dedicated multipliers or dividers. The CORDIC algorithm is well suited for FFT due to the simplicity of the operations involved. A rotation of a vector v is illustrated in Figure 2 where p n = [x 0 y 0 ] is the starting vector and p n = [x n y n ] is the same vector rotated by an angle θ. 144

3 Figure 2: General rotation of a vector [5] Rotation angle θ is partitioned into smaller rotations α i and θ = i=0 ±α i. Using iterations, x n = cosα i (x 0 y 0 sinα i ) y n = cosα i (y 0 + x 0 sinα i ) Because a rotation can be either positive or negative, σ i is introduced as the rotation direction and for a Radix-2 implementation σ i = {-1, 1}. Restricting the rotations so that α i = atan (2 i ), the parenthesis with the multiplication is reduced to a simple shift-and-add operation. x n = K i (x 0 σ i y 0 2 i ) y n = K i (y 0 + σ i x 0 2 i ) Here each iteration is multiplied with scaling factor Ki = cos (atan (2 i )). Removing the scaling factor yields an iterative shift-and-add algorithm for vector rotation, which is easily implemented in hardware. A third iterative component is needed to keep track of the rotations of the angle. The rotations are accumulated with the help of a lookup table holding the values of α i = atan (2 i ). The next rotation α i+1 is always smaller than the previous rotation α i. The accumulation of the residual angle can be implemented with one extra adder. z n = z 0 σ i α i A traditional FFT processor stores the twiddle factors in memory. Instead, a CORDIC-based FFT processor needs to store the twiddle factor angles in memory. III. DATA AND ANGLE REPRESENTATION In this architecture, 16-bit fixed point data format is used to represent input and output data. Where MSB bit is signed bit, next 7 bits (14-8 bits) are integer part, and last 8 bits (7-0) represent fractional part. The advantage of using fixed-point data over floating point data is improved operation speed. s which are used for twiddle factor calculation are represented by 32-bit number. Where first bit is sign bit and rest of bits are used to represent magnitude of angle. 2π is represented by making all 31 bits 1, π is represented by making Most Significant bit (31 st bit) 1 and rest of bits 0. By representing angle 2π in 31 bits as 2 31 and N = 2 9 for 512-point FFT, it is calculated that n. 2π/N = n /2 9 = n. 2 22, n = 0,1, bits 23-bits Fig.3: Representation [7] IV. ARCHITECTURE Conventional CORDIC-based FFT processor needs a dedicated memory bank to store the necessary twiddle factor angles for the rotation. For the Efficient Radix-2 DIF FFT processors using CORDIC algorithms, Serial-in Serial-out architecture has been proposed as shown in Figure

4 Fig. 4: FFT processor using CORDIC algorithm [7] In this proposed architecture, only single RAM has been used to store the input data or the butterfly result depending upon the stage of the FFT processor. This results in saving of the memory bits requirements for the proposed FFT processor. A. Butterfly Unit Here, for the Radix-2 butterfly, a new Parallel-in Serial-out pipelined-architecture has been proposed as shown in figure 5. In this proposed architecture, two pipeline stages are used. Adder & subtractor outputs are applied at the first pipeline stage. Register a s real and imaginary data is passed to second pipelined stage. In between, register b s real & imaginary data along with twiddle factor angle is applied to CORDIC processor. As this CORDIC processor gives output in 16 clock cycles, this CORDIC clock is made 16 times faster than FFT clock signal clk. Fig. 5: Pipelined Architecture of Radix-2 Butterfly using CORDIC [7] B. Address Generation Unit Here, as we have used single RAM architecture, we need to generate read and write addresses on real time. For Address Generation purpose, an interesting property of DIF FFT algorithm is used. Sequence of data, on which butterfly operation is performed, are in right-shifted version of binary counter output. As the FFT operation progresses, at every stage one more right-shift is performed to get the next address. Thus, we can generate address by using a counter and shifters. 146

5 Table 1. Result of Address generation unit for 16-point FFT Stage 0 Stage 1 Stage 2 Stage 3 inputs b0b3b2b1 inputs b1b0b3b2 inputs b2b1b0b3 inputs b3b2b1b C. Generation Unit At the same time, we need to generate angles for corresponding butterfly. For above generated addresses, angles to be generated are as shown below. Butterfly Counter Stage 0 Table 2: generation results for 16 bit Stage 1 Stage 2 Stage π/ π/8 2π/ π/8 2π/ π/8 4π/8 4π/ π/8 4π/8 4π/ π/8 6π/8 4π/ π/8 6π/8 4π/

6 V. CONCLUSION In this paper, CORDIC based FFT is used instead of conventional ROM based FFT processor. Twiddle factors are generated in real time, so there is no need to store angle values in ROM. This way, memory usage is largely reduced compared to conventional FFT processors. Moreover, as CORDIC algorithm gives result of multiplication of twiddle factor with input data, need of multipliers are also eliminated. Thus, logic elements required for FFT is also less compared to conventional design. ACKNOWLEDGEMENT I express my obligation and gratitude to my Guide Prof. Chintan B Dave Assistant Professor, VGEC, Chandkheda, Gandhinagar for his genuine guidance and constant encouragement throughout this project work. I am highly obliged as my honorable guide have devoted his valuable time and shared his expertise knowledge. His broad knowledge, rigorous working attitude and eagerness for new technologies are always my model to follow. I cannot finish my thesis successfully without his guidance. I extend my sincere thanks to all respected faculties of Department of Electronics and Communication Engineering, Vishwakarma government engineering college, Chandkheda for providing me such an opportunity to do my project work. I also wish to express my heartfelt appreciation to my family, friends, colleagues and many who have rendered their support for the project, both explicitly and implicitly. REFERENCES [1] J.G.Proakis, D.G.Manolakis, DSP Principles, Algorithms and Applications, PHI Publications, 4th edition, [2] Xin Xiao; Oruklu, E.; Saniie, J., "Reduced memory architecture for CORDIC-based FFT," Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, pp , May June [3] Tze-Yun Sung, Hsi-Chin Hsin, and Yi-Peng Cheng, Low power and high-speed CORDIC-based split-radix FFT processor for OFDM systems, Digital Signal Processing, vol. 20, pp , March [4] X. Xiao, E. Oruklu, and J. Saniie, Fast memory addressing scheme for radix-4 FFT implementation, IEEE International Conference on Electro/Information Technology, EIT 2009, pp , June [5] Meher, P.K.; Valls, J.; Tso-Bing Juang; Sridharan, K.; Maharatna, K., "50 Years of CORDIC: Algorithms, Architectures, and Applications," Circuits and Systems I: Regular Papers, IEEE Transactions on, vol.56, no.9, pp , Sept [6] A. Banerjee, A. S. Dhar, and S. Banerjee, "FPGA realization of a CORDIC based FFT processor for biomedical signal processing," Microprocessors and Microsystems, vol. 25, no. 3, pp , 2001 [7] P. Bansal, B. S. Dhaliwal and S. S. Gill, "Memory-efficient Radix-2 FFT processor using CORDIC algorithm," Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 International Conference on, Coimbatore, 2014, pp [8] Xilinx: Fast Fourier Transform logic IP core v7.1 Product specifications DS260 (1st March 2011). [9] Sameer Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, 2nd Edition. 148