Built-In Self-Test with Weighted Random Pattern Hardware

Transcription

1 Built-n Self-Test with Weighted Random Pattern Hardware Franc Brglez' Clay Gloster'.2 Gershon Kedem 'MCNC 2North Carolina State University 3Duke University Abstract 'Microelectronics Center of North Carolina P. 0. Box 12889, Research Triangle Park, NC This paper addresses scan-based built-in self-test (BST) of digital circuits that are highly resistant to testing with uniform random patterns. ntroducing a procedure PREWARP, we precompute test patterns for random pattern resistant faults and generate optimized distributions of weights that guarantee pattern coverage in a given number of random trials. The software implementation offers a tradeoff in the number of distributions (hardware memory) and the length of the total test time. The hardware implementation is based on a canonic weighting circuit that interfaces to a circulating memory and a pseudo-random source. 1 ntroduction Experience with random pattern testing has shown that for some circuits, several million patterns may be required for an acceptable test coverage. Recently, new approaches have been developed for computing weighted random test vectors which significantly reduce the test length requirements. Reducing the test length has potential for improving the quality of the Built-n Self-Test since it can reduce the effort to verify effectiveness of test compaction techniques such as signature analysis. Earlier approaches to calculating weights maximize fault coverage [1,2,3]. n contrast, the proposed procedure PREWARP targets specific patterns and aims to optimize pattern coverage. n addition, we can synthesize hardware that generates weighted patterns which approximates the initially specified weights [3,4,5]. Specifically, given the weights, we can automatically synthesize minimal hardware 15). We have the option of using a LFSR or a CAR as the source of random patterns [6]. The main idea of PREWARP is simple and is best illustrated by discussing fault coverage of a highly random pattern resistant benchmark c2670 shown in Fig. 1. Fault simulation of all testable faults of this 233-input benchmark circuit with patterns from a 20-bit CAR raises fault coverage to only 99.43% after 2'O-l trials (the maximum period of the CAR). At this point, we engage a deterministic test pattern generator to generate 15 additional patterns for each undetected fault, thereby raising the fault coverage to 100% of all testable faults. We find the test pattern with the least number of unassigned bits, 190 in this case. The remaining bits in the pattern have a value of either a 0 or a, = 43 in this case. According to the discussion in [5], we will require 243 random trials to cover this pattern with probability of 63% and 5 times as many trials to increase this probability to 99.33%. Note that the cost of verifying that we cover the "hardest" pattern with a larger CAR or an LFSR would be prohibitive. As an alternative, after fault simulation with the uniform random source no longer appears effective, we generate a complete set of deterministic patterns. We use these patterns to generate a set of weights that optimize pattern coverage. Using this approach, we notice a significant improvement for the benchmark in Fig. 1, even though we reduced the size of the CAR to 16 bits. Overall, we not only significantly reduced the cost of test pattern generation but also the test time for the circuit. The paper is organized as follows. We first outline a straightforward approach to generating 3-valued test patterns for random pattern resistant circuits. The process of covering these patterns produces parameters with which we can synthesize the front end of the BST hardware to generate weighted test patterns. We introduce a simple counting algorithm that outputs a set of optimized weights, given the set of patterns. We discuss a heuristic partitioning algorithm that groups patterns if we need to trade the number of random trials (test time) with the number of distributions (hardware memory size). The paper concludes with results based on a set of random pattern resistant benchmark circuits. Due to space limitations, only the key ideas and results are presented. More details are available in 171. Q, m E g 95 J Random Trials Figure 1: Enhancing fault coverage with PREWARP 0 CH2909-0/90/0000/0161$01.OO EEE 161

2 2 Synthesis for BST n a simplistic BST implementation, one would generate random patterns for a given time period and then apply precomputed patterns stored in memory. For most practically-sized circuits, one would need to store patterns that are several hundred bits wide and several hundred bits long. Clearly, such an implementation may result in excessive memory overhead and time to load and unload the memory. n our approach, we remove the need to store such patterns. nstead, we employ a weighting circuit which will, for a given set of weights, generate weighted random patterns covering all of the precomputed patterns. The weighting circuit, WARP, quantizes weights uniformly to any desired precision. t is shown in Fig. 2 and is described in full detail in [5]. The overhead of the weighting circuit is much less than that of a memory which would store these patterns directly. The process PREWARP generates all parameters required for BST, given the scan-based netlist description of the circuit under test. These parameters are then used to synthesize the BET hardware. The key components are shown in Fig. 3. The main objective is to optimize tradeoffs in effort to generate tests, time to test the circuit and the hardware costs for BET. The essential input parameters are b, the total of primary inputs and scannable latches, and s, the size of the CAR or LFSR as the source of maximal length (2' - 1) pseudo random patterns. t is essential to check that the value of b and the period of the random source do not share a common divisor. This could reduce the period of random patterns dramatically. n the first phase of the process, we rely on already proven and efficient approaches and tools that perform fault simulation and test generation [8,9,10]. f we achieve a fault coverage of loo%, we only need to synthesize the source of uniform random patterns of size s; if not, we proceed with traditional test pattern generation. t is crucial that the test pattern generator returns test patterns that are three-valued; i.e. it assigns to inputs that are not required to test a specific fault, the value X. Traditionally, such threevalued patterns are compacted into a smaller pattern set. Such pattern compaction reduces the number of unassigned inputs for Pseudo Random Source Register s- Weights Register , Circular Memory Scan Reglster Figure 2: Weighted test generation with WARP 7 (inputs = b + F.C. = 1009L 1'" +r Qe 3-V pattams Distribution ( WARP J 5 Figure 3: Synthesis for BST, driven by circuit under test many of the patterns, but it makes them unnecessarily harder to cover in a given number of random trials. n our application, we rely on a 3-valued fault simulator that reduces the size of the 3-valued pattern set while preserving the originally unassigned inputs at the value of X. n the main loop of PREWARP we select a target subset of 3-valued patterns and compute a set of weights that will maximize pattern coverage probabililies in a given number of random trials. The highlights of the algorithm will be presented in the next section; more details are available in [7]. The actual generation of random patterns and evaluation of pattern coverage is performed in WARP as described in 151. f a single distribution is sufficient to cover all the test patterns, we are done. Otherwise, we continue generating new distributions until we obtain a pattern coverage of 100%. At this point we know all the parameters required to synthesize the BST circuit that will generate weighted random patterns and fully test the circuit-under-test. The key parameters that determine the size of the weighting circuit are: random source size s (CAR or LFSR), resolution of the weighting circuit r, number of distinct weights required q, and the number of distributions to be stored in the memory d. The solution we choose is based on a trade-off in test time, the number of distributions, and the accuracy of the weights. By increasing the test period (random source size), one can reduce the number of distributions and the number of bits required for storing the weights. Our experiments confirm that we can rely on probabilistic pattern coverage with PREWARP to generate all required design parameters, without the need for explicit pattern simulation performed by WARP. The number of transistors for the weighting circuit and the pseudo-random source is directly proportional to the source size s, and the resolution r. Typically, the values of r = 3-5, and s = 16 ~ 32 are required, translating to transistors with CARS and less if we use an LFSR. The circular memory is a ROM whose size depends on the random pattern resistance of the circuit-under-test. The upper bound on the size of this memory is (r + ) * b * d bits. n practice, we find that only a fraction of the total number of distinct weights are required, so we can partition the memory into two parts, storing the addresses and. 162

3 the values of the weights separately. The size of the memory is now dominated by the value of logz(q) * b * d. Overall, the benchmark results show that the size of the required memory can be similar to the size of the source and the weighting circuit or be several times this value. We also show that the size of ROM is comparable to the size of a sequence generator that we synthesize automatically as random logic with standard cells. The latter implementation may be preferable in some cases. 3 Optimizing Pattern Coverage The notion of pattern coverage has been introduced in 161. t s definition is analogous to fault coverage: # of patterns covered pattern coverage = x 100% (1) # of patterns specified n early work, we used pattern coverage primarily in a hardware emulator WARP to evaluate the quality of weighted or uniform random pattern generation 151. n this paper, we assume that the patterns to test a particular circuit have been specified and the task remains to generate weighted distributions that will cover 100% of these patterns in a specified number of pseudo-random trials. While the hardware generates 2-valued patterns, the patterns returned by a deterministic test generator can typically be represented with three values: 0,1, and X. Covering each pattern is equivalent to detecting a single stuck-at-0 fault on the output of a decoding AND gate. A 0 in the pattern represents an inverting input, a 1 represents a non-inverting input and an X in the pattern designates inputs that are not connected to the particular decoding gate. This model forms the basis for our approach to generating weighted distributions. We use the same model to implement an efficient pattern simulator. 3.1 Counting algorithm n this section, we present a simple counting algorithm to generate a set of weights, for a given set of patterns. We show that these weights minimize the geometric mean of the projected number of random trials required for 100% pattern coverage. Let the pattern set be represented as an array, b-bits wide and M-patterns long, whereby the entries in the array have values of 0,l and X respectively. A small pattern set in Fig. 4 illustrates sixteen 7-bit wide patterns. We associate a weight or bit signal probability zi with the i-th 0 or 1 position in a pattern k and we evaluate the detection probability of this pattern as follows: Pk = (1- zi)(zj) (2) ie;, jc: where Zi, ; are sets of indices, pointing to a bit value of 0 and 1 in the k-th pattern, respectively. For example, in Fig. 4, for the 5-th pattern we find 1; = {1,4} and : = {2,3,6}. The pattern detection probability in (2) accounts for the presence of X-values in the pattern and is based on the decoder model outlined above. As in [5], we associate any probability p& with the first detection of a designated pattern in a sequence of independent Bernoulli trials. The number of trials, also equated with waiting times, is a random variable Nk which has a geometric distribution with a mean of l/pk and a variance of (1 - pk)/pk2 [ll]. We define an Projected Pattern Coverage: 49.8% ( 31 trials) 87.1% (127 trials) 99.3% (511 trials) X pl = X p2 = X X X p3 = X 0 0 X p4 = X X p5 = X p6 = X 1 1 X p7 = X p8 = p9 = X X X p10 = X pll = X p12 = X X p13 = p14 = X p15 = X p16 = Z4 23 Z2 Z1 ZO Figure 4: An example of a typical test pattern set estimator of the pattern coverage for M patterns as an average cumulative detection probability: M PCEM(?Z) = 1 - (l/m) c ( 1 - pk) (3) k=l The overall objective is to find weights zi that would minimize the number of random trials needed for 100% pattern coverage. According to (3), we should attempt to maximize each and every Pk, which in turn will minimize the mean number of trids as well as the variance. A detailed analytical effort on minimizing several objectives, including the min/max function is presented in 17). We limit ourselves here to presenting an optimum solution that minimizes the geometric mean of all pattern detection probabilities as defined below. The expression (4) can be readily differentiated, set to zero and solved for z;, yielding:.p = ni. i=o,l,...,b-l; (5) mi + n; where ni and mi represent the total number of 1 s and 0 s in the column i. t can be shown that the expression (4) has a minimum for values of zp in (5). The weights in Fig. 4 are calculated using the counting algorithm in (5) and the corresponding pattern detection probabilities are evaluated according to (2). The pattern 163

4 coverage projections, also shown in Fig. 4 are evaluated with (3). Note that in this example, we require more than 2' trials to reliably cover the complete set of patterns. Projected Pattern Coverage: 98.6% (31 trials) pl = X p2 = X p3 = X X X p4 = X p5 = X p6 = X 1 1 X p7 = X X p8 = "! " l - - i Projected Pattern Coverage: 98.8% (31 trials) X X pl = X p2 = X p3 = p4 = p5 = X 0 0 X p6 = X X p7 = X X X p8 = proposed in [5] provides for these important weights by default, without additional overhead. There are many ways to sort a set of patterns and find an acceptable partition. The sorting that we found most useful to date is based on the concept of a distance between patterns. f patterns are 2-valued, the distance between patterns is usually measured with the well-known Hamming distance. n our case, patterns are 3-valued. Let A and B represent two 3-valued patterns, each b-bits wide and let Zp,Z," assume values of 0,1 or X in the i-th position of the respective patterns. We then define distance between patterns A and B as follows: where b-1 hd(a,b) = xd(zt,z:) d(zt,z?) =,=O 1 if zp=z," 0 otherwise; Note that if both A and B become two-valued patterns, hd(a, B) is a Hamming distance between A and B. The notion of distance as defined in (6) is fundamental to the partitioning strategy discussed next. Selecting a Target Pattern Set. Let P be a set of patterns to be covered with random trials. Define a reference pattern Po. The results in this paper are based on choosing the pattern with the largest number of assigned inputs as a reference pattern. Let Pt be the largest target subset of patterns that can be covered to at least t% in 2" - 1 trials, evaluated with (3). Note that we apply the counting algorithm (5) to the target subset only. The heuristics that we have found most successful can be summarized as follows: 1. Find PO from P 3.2 Figure 5: Distance-based partitioning of a test pattern set On Partitioning a Pattern Set The need to partition a set of patterns arises whenever the weighted distribution, even though optimized, is such that we cannot cover the complete set of patterns within a specified number of random trials. f we divide test patterns into two sets, the weights that we generate for each set separately may improve pattern coverage for that set, provided we keep the number of random trials constant. However, an arbitrary partitioning of patterns will not necessarily be effective. Consider for example, taking the top 8 patterns in Figure 4 as one of the two partitions. Recalculating the weights for both partitions and making new projections results in pattern coverage of 61.7% and 48.9% after 31 trials; no overall improvement over the unpartitioned set. However, if we sort the patterns so as to decrease the overall "distance" between the respective bit positions and then make two partitions of 8 patterns each as shown in Fig. 5, we find a dramatic improvement in pattern coverage: 98.7% and 98.6% after 31 trials. The grouping of patterns that differ in the fewest possible bit positions has produced several weights with values of 0.0 and 1.0 which contributed to dramatic increase in the respective pattern detectabilities. Fortuitously, the weight,ing circuit we 2. Sort P in the order of increasing distance (6) from PO 3. For a given value of s and t, find P;' Given a value for the source size, s, the effectiveness of the approach depends on the choice of t and the method we use to find the target subset P;. Typical values oft range between 95% and 99%. We have basically experimented with two selection strategies: a greedy selection of a target set and a recursive selection of a target set. n a greedy selection, we choose the complete set of patterns, and declare patterns with projected coverage above t% as detected. n a recursive selection, we choose the largest subset in a group of sorted patterns with projected coverage above t% as our target set. Typically, we will cover more patterns initially with the greedy selection as compared to the recursive selection. Overall, the recursive selection will reach 100% pattern coverage with fewer distributions. We illustrate this with our most random pattern resistant benchmark, max63 that has 256 inputs, 4 outputs and is 100% testable. The initial distribution in Fig. 6 is based on sorting 293 test patterns. Similar distributions have been produced by a deterministic pattern generator for most circuits that we examined. Many patterns would have X-values in most bit positions, hence the distance between most patterns is relatively small. Consequently, we can cover relatively large groups of patterns in a 164

5 Circuit nouts OutDuts FC after FC after Name trials trials Table 1: Benchmark Circuit Characteristics Distance Figure 6: Pattern distribution of benchmark max63 reasonable number of trials with a single distribution only. However, as shown for max63 circuit in Fig. 7, we still required 14 distributions when we used the greedy targeting strategy and 9 distributions when we used the recursive targeting strategy. with a single set of weights. The weights are generated from a set of 3-valued deterministically generated patterns as discused earlier. Except for circuit s1196, we could achieve this objective within a period which is much lower than the initial value of 65,535. However, the last four circuits in Table 2 could not be tested with a single distribution. For circuit c7552 we had to increase the size of the source to since the number of inputs and the period of 65,535 have a common divisor of By applying the recursive selection of the target pattern set we achive 100% pattern coverage in 2-9 distributions; as we illustrated in Fig. 7, circuit max63 is the hardest one to test with weighted random patterns. Distributions Figure 7: Partitioning heuristics and pattern coverage 4 Benchmark Results None of the circuits in Table 1 can be tested with 65,535 (216-1) uniform random trials using a default UNX random number generator and only one is found testable after 1,048,575 trials. All of the subsequent experiments are performed with a CARbased pattern generator with a period of to control the cost of the overall experiment and to demonstrate a range of available trade-offs. Cellular-automata registers (CARS) were used since we have found that they would consistently produce weighted patterns with better fault and pattern coverage than LFSRs [5]. All circuits that can be tested within two periods of a given random source are listed at the top of Table 2. During the first period, the circuits are tested with uniform random patterns; during the second period the circuits are tested to completion Table 2: PC with a single weighted distribution There is a near perfect agreement between the projected and achieved pattern coverages in Table 2. n fact, we only need to compare the pattern coverage projections based on quantized weights with the weights that use the floatir.; point representation to determine the value of the resolution r at which the effects of quantization will be negligible. The required value oft ranges from 3 to 6. Replacing the weighting circuit in Fig. 2 with the one proposed in [3] degrades the pattern coverage dramatically as illustrated in Table 3. The transistor cost of ROM-based circulating memory or random logic, assuming that we need to store only a single distribution, is shown in Table 4. Note that both types of implementations require a comparable number of transistors. The ROM-based implementation will require less area, however, random logic may be easier to accomodate within a layout based on standard cells. 165

6 Circuit Name Quantization Uniform Non-uniform Pattern 11 ; : Nu; of Pattern Number of Coverage Coverage Trials Acknowledgements We thank John Calhoun, now with BM, Research Triangle Park, NC, for assisting us with the the deterministic test pattern generator. We also would like to thank Dieter Pellkofer, from the Technical University of Munich, for providing us with assistance with the 3-valued fault simulator. NT and BNR have supported the initial stages of this research. Special thanks are due to the rest of the OASS group at MCNC who are always helpful and inspiring. Table 3: Effects of quantization on pattern coverage Circuit Name c880 chkn s1196 s420 s641 s838 Circular Memory Random Logic (bits) (transistors) c2670' max63' 1024 dec32' c7552' Table 4: Hardware cost: memory versus random logic 5 Conclusions We have presented an approach that will generate weights from a set of precomputed patterns rather than from fault coverage analysis of the complete circuit. This avoids the problem of fault reconvergence. Using the concept of pattern coverage alone, we can extract all parameters needed to synthesize efficient BET hardware at a nominal cost. Reasonable tradeoffs can be made between test time and hardware costs. References [l] Robert Lisanke, Franc Brglez, Aart J. de Geus, and David Gregory. Testability-Driven Random Test-Pattern Generation. EEE Transactions on Computer-Aided Design, CAD- 6(6): , November [2] Hans-Joachim Wunderlich. On Computing Optimized nput Probabilities for Random Tests. n Proc. 2'4th Design Automation Conference, pages , [3] J. Waicukauski, E. Lindbloom, E. Eichelberger, and 0. Forlenza. A Method for Generating Weighted Random Test Patterns. BM Journal of Research and Development, 33(2): , March [4] Hans-Joachim Wunderlich. Self Test Using Unequiprobable Random Patterns. n Dig. lnt. Symposium on Fault- Tolerant Computing, pages , July F. Brglez, C. Gloster, G Kedem. Hardware-Based Weighted Random Pattern Generation for Boundary Scan. n Proc. EEE nternational Test Conference, pages , August is1 [71 C. Gloster and F. Brglez. Boundary Scan with Built-n Self Test. EEE Design B Test of Computers, 6(1):36-44, February F. Brglez, C. Gloster, G Kedem. Synthesis for BST with PREWA RP. Technical Report, Microelectronics Center of North Carolina, Research Triangle Park, NC, June Kurt J. Antreich and Michael H. Schulz. Accelerated Fault Simulation and Fault Grading in Combinational Circuits. EEE Transactions on Computer-Aided Design, CAD- 6(5): , September M. Schulz and D. Pellkofer. A Three-Valued Fast Fault Simulator for Scan-Based VLS-Logic. n European Test Conference, J. Calhoun and F. Brglez. A Framework and Method for Hierarchical Test Generation. n Proc. EEE nternational Test Conference, pages , August William Feller. ntroduction to Probability Theory and t's Applications. John Wiley & sons, New York,