RTL Power Estimation and Optimization

Transcription

1 Power Modeling Issues RTL Power Estimation and Optimization Model granularity Model parameters Model semantics Model storage Model construction Politecnico di Torino Dip. di Automatica e Informatica RTL Power Estimation Early evaluation of power consumption is essential to assess the quality of high-level optimizations MUST avoid full synthesis At the RTL, however, structural and technological properties of the design are unknown Solution: Build a power model which relates (actual) power to RTL quantities Model Granularity Power model for entire RTL design not reasonable Must build power models for blocks of smaller granularity Assume a typical architectural template (structural RTL) and refer to the corresponding blocks Datapath modules (+, *, -, ) Registers Controller Different models for different blocks! RTL Power Estimation: Basics Useful for: Design exploration. Design validation/signoff. Cycle-accurate RTL description: Statements of the HDL synthesizable subset. Limited accuracy: Resources are not instantiated. Structural RTL description: Interconnection of data-path blocks (adders, multipliers), registers, memories and controller. Higher accuracy: Resources are explicitly instantiated. Sources of estimation inaccuracy: Poor knowledge of design structure (gate or transistor). Poor modeling of dynamic effects (glitching). Poor modeling of clock and interconnect. Model Parameters Must be parameters observable at the RTL Complexity parameters Related to the relation between capacitance and complexity Size of datapath modules (# of bits) # of states of controller Activity parameters Related to the input-depend nature of power Static/transition probabilities Temporal/spatial correlation Typically, use a mix of both types

2 Model Semantics Models may have different semantics depending on how power is related to parameters Cumulative model: Models average power One power value per each parameter assignment Cycle-accurate model: Models instantaneous (i.e., cycle-by-cycle) power A series of power values per each parameter assignment Need suitable parameters! More accurate Higher analytical power (e.g., IR drop and reliability analysis) Analytical vs. Empirical Models Analytical models relate power dissipation to parameters to express activity and capacitance: Dependency based on a physical relation Best suited for: Black-box estimates (no data available for individual blocks). Fixed structure components, e.g., memories. Empirical models are based on a measure of power, from which a model is built: Best suited for library-based approaches. Can be used for custom functional blocks, as long as some real power figures are available. State-of-the-art Model Storage Models, as representations of a function, can be stored in two ways: As an equation (Equation-based models) Smaller storage size A lookup-table: (Table-based models) Larger storage size Macromodeling: Basics Macromodeling consists of generating power models for some given input data statistics. Input statistics are obtained by RTL simulation. Problem definition: Given a sequence of N vectos, derive a (simple) function whose value, for the N vectors, is as close as possible to the actual power dissipation of the N-vector sequence: P = F (Parameters, Coefficients) Model Construction Most important modeling issue Determines a broad classification of power models: Analytical (top-down) models Empirical (bottom-up) models: Macromodeling. Macromodeling: Flow Model design: Parameter selection (e.g., activities, correlation). Model template definition (e.g., additive vs. multiplicative, linear vs. non-linear). Design of the training set: Number and distribution of the input patterns Characterization: Determine power for different assignments of the parameters on an implementation of the block(s). Model extraction: Build the model by interpolation of the individual power samples (e.g., by LMS regression). Model evaluation: Use the model as a power estimator. 2

3 Macromodeling: Example RTL Integration Issues - Non-idealities Model for 4x4 array multiplier. Single parameter: Number of input transitions, NI. P = f(ni) Points: Power by simulation of patterns. Typical RTL structures: Basic modeling entities: + > - * Macro Wire Logic Need models for all objects! Macromodeling: Issues Model robustness: Sensitivity to the training set. Out-of-sample error: Error is small for input conditions close to those of the training set; it may be very large for other input statistics. Model complexity: Characterization cost (CPU time). Storage requirements. Model storage (revisited): Equation-based macromodels: Limited robustness, shorter characterization times. Table-based macromodels: Higher robustness, longer characterization times. RTL Power Optimization RTL Integration Issues Use of macromodeling-based power estimation in realistic design flow requires: Tight integration to synthesis and simulation flow Characterization requires both Possibility of using pre-characterized power models Library of power models (dynamically updated) Non-idealities: Description is in some HDL No structure Limited structure is inferred by HDL compiler May need RTL models of blocks of smaller granularities ( virtual gates, virtual MUXes, virtual registers) Models for IP blocks Memories, pre-designed components, Model integration issues Summary RTL power optimizations: RTL power management Clock gating. Operand isolation. Common-case optimizations Pre-computation. Extraction of computational kernels. Reduced-strength operators. Bus encoding. 3

4 Clock Gating: Basics Idea: Stop the clock to registers which are not in use during some particular clock cycles. Traditional implementation of load-enable registers. D_in EN CLK Reg Bank D_out Activity-Driven Clock Gating: Flow Basic procedure: A collection of flip-flops is generated, sorted according to increasing switching activity. Clock gating is applied only to those flip-flops whose switching activity is lower than a predefined threshold. Threshold is determined automatically. According to this threshold, the initial list is reduced and clock gating is applied to the newly obtained (short) list. Gated clock implementation. D_in EN Latch GCLK Reg Bank D_out CLK Clock Gating: State-of-the-Art Clock gating is the most effective power optimization feature provided by state-of-the-art EDA tools. A significant amount of power can be saved by reducing: Switching activity on the clock inputs to synchronous load-enable registers. Capacitive load on the clock tree. Current limitations: Clock gating does not take into account the switching activity of the registers it involves. Clock gating does not take advantage of situations where one part of a functional unit is in use while other parts are unused. ODC-Driven Clock Gating: Principle Clock gating turns off the clock signal when none of the primary outputs are used. However, REG and REG2 are not observable when sum_en is not active, even if other regions of the datapath are processing useful data. The rationale of ODC-driven clock gating is that registers that are not observable, during a given clock cycle, should be turned off. In_I_bus In_T_bus ireg_en REG REG2 treg_en I_bus T_bus mux_sel MUX S_bus R_bus + sum_en Outbus Clock Gating: Enhancements Activity-driven clock gating: Clock-gating should not be applied to high switching activity registers. Choice of registers to be clock-gated based on threshold. Operand Isolation: Basics Idea: Identify redundant computations of datapath components. Isolate such components using specific circuitry. ODC-driven clock gating: Registers that are not observable, during a given clock cycle, should be turned off. Conditional activation of registers based on ODC (Observability Don t-cares) conditions. Redundant computation = conditionally evaluated and/or propagated. Common situation in control-intensive designs. 4

5 Operand Isolation: Example Common-case Optimizations Example: Isolation logic AND gates OR gates LATCH d d2 Activation signal AS SEL_ SEL_ + D clk Basic principle: Optimization of the common case (i.e., the typical behavior) Implement the common case with a simpler (i.e., less power-hungry) block of logic Use the base implementation for the non-common case Conceptual scheme: A = original B = common case implementation I n I a R I b R2 m Sel A B O b O a O Operand Isolation: Issues Identification of the redundant computations. Selection of the most effective computations. Implementation of the isolation conditions. Implementation of the isolation scheme: Latches (more effective but expensive). Logic gates (cheaper but less effective). Common-case Optimizations (Cont.) Various implementations differ by: How the common case is determined How the common and non-common case are combined together Implementation of selection function How the area-power tradeoff is managed Can be directly implemented on the HDL code. RTL Power Management: RTL Integration Issues Clock gating: Naturally supported at the RTL Clock explicitly exposed at the RTL (even in source code) Latches are synthesis invariant ODC computation requires availability of RTL structure Possible on elaborated database (after HDL compilation) Issues: Determine gating conditions Instantiation of gating logic Operand isolation: Requires availability of RTL structure Possible on elaborated database (after HDL compilation) Issues: Determine redundant computations Determine isolation conditions Instantiation of isolating logic Pre-Computation: Basics Idea: Selectively pre-compute the circuit output values one clock cycle before they are required. Use pre-computed values to reduce the amount of switching in the combinational logic in the next cycle. Need to determine and synthesize small, yet efficient predictor functions. 5

6 Pre-Computation: Architecture Pre-Computation: Example g = => f = g 2 = => f = For equiprobable inputs, p(xnor) =.5 Approximately 5% power reduction. Pre-Computation: Predictor Functions (I) If either g or g2 evaluate to : Set the load enable LE to. Inputs to A in the next clock cycle do not change. If g = : The input to R2 is. f = in the next clock cycle. If g2 = : The input to R2 is. f = in the next clock cycle. Computational Kernels: Basics Idea: The typical behavior of a sequential circuit can be implemented by a block of logic that is usually: Small. Fast. Low power consuming. Rationale: When in its steady-state, a sequential circuit tends to run through a limited set of states. Computational kernel of a circuit: The logic block that implements its steady-state behavior. Pre-Computation: Predictor Functions (II) Choice of g and g 2 is critical. Target: Maximize the probability of g + g 2 being. Ideally, g f and g 2 f. This implies triplicating the circuit. In practice, g and g 2 can be computed by: Heuristically selecting a subset of inputs X = (x,...,x p ). Finding the largest function contained in f independent of X. Computational Kernels: Extraction At the state machine level: p-order computational kernel: Keep the states with steady-state probability p. Collapse the other states into a single state (idle). Synthesize the modified state machine. Example: S p=.29 S5 p=.2 S7 p=. S p=.25 S3 p=. S6 p=.2 S2 p=.8 S4 p=.32 S idle S S4.25-order computational kernel 6

7 Computational Kernels: Optimization Paradigm Use a parallel implementation that exploits the computational kernel K: Use K when possible. Otherwise, use the original circuit. Useful if Prob (K) is large. Trade-off between small vs. highly-probable kernel. Common-case optimizations: RTL integration issues Target: modules with a well-defined functionality. Not applicable to generic portions of a design Suitable for developing custom power-managed RTL blocks: Used by the synthesis tool when mapping RTL operators to RTL blocks Adders, comparators, multipliers e.g., an extension to an RTL module library (such as Synopsys DesignWare) Computational Kernels: Basic Architecture SEL = when the next state will be in the kernel. SEL = when the next state will be outside. Prob(K) = Prob (SEL = ). PI C K M U X PO NS K and C are MUTUALLY EXCLUSIVE Bus Encoding: Basics Global interconnect capacitance dominates over gate capacitance. Reducing switching activity on global buses produces significant power savings. Promising approach: Bus encoding. Processor-to-memory communication. Overhead of encoder-decoder may be significant: Latency/delay, area, power. Several encoding schemes proposed in literature: Hard to say which one is best. FF SEL Computational Kernels: Detailed Architecture Bus Encoding: Example x DSFF C p MUX o Core Processor Memory K DSFF t r u FF s MUX s S s Original stream: 3 Transitions Encoded stream: 9 Transitions Overhead of codec must be taken into account when doing the power balance. 7

8 Bus Encoding: Taxonomy Bus encoding techniques can be categorized according to three parameters: Redundancy. Knowledge of statistics. Type of activity. Parameter Redundancy Knowledge of Statistics Type of Activity Values {YES, NO} {None, Partial, Full} {Switching, Coupling} T Code: Principle Parameters: Redundancy = YES. Knowledge of statistics = Partial. Type of activity = Switching. Approach: Do not transmit a pattern if it is in-sequence. Receiver computes the new address Bus-Invert Code: Principle Parameters: Redundancy = YES. Knowledge of statistics = None. Type of activity = Switching. Approach: Look at two consecutive patterns, A and B. If H(A,B) <= N/2, then transmit B. If H(A,B) > N/2, then transmit B. N = Bus width. H(A,B) = Hamming distance between A and B. Bus Encoding: CrossTalk Power Minimization Existing encoding schemes target the minimization of the number of transistions on the bus lines: Minimization of the capacitance switched during communication. Adopted bus power model considers single-wire transitions: Inter-wire, or cross-talk capacitance switched during information transfer is neglected. Cross-talk capacitance can no longer be ignored in deep-submicron buses. Need of encoding schemes that take into account cross-talk capacitance Gray Code: Principle Parameters: Redundancy = NO. Knowledge of statistics = Partial. Type of activity = Switching. Approach: Two consecutive code-words have unit Hamming distance. Due to instruction/data locality, most memory accesses are sequential. Reduce bus switching by using Gray addressing. CrossTalk Power Minimization: Basic Concepts Cross-talk power consumption of two adjacent lines is maximal when the two lines make simultaneous opposite transitions. Cross-talk power consumption of two adjacent lines decreases as the spacing between the two lines increases. Existing solutions are based on the two concepts above. 8

9 CrossTalk Power Minimization: Solutions Wire permutation: Low cost of codec. Non-uniform wire spacing: Better Better Needs area slack in bus channel (at floor-planning time). Bus Encoding: RTL integration issues Buses in RTL: Between datapath modules (e.g., ALU to registers) Short, a true bunch of (local) wires To/from memories Longer, treated as global wires RTL bus encoding more suitable for memory buses Higher capacitance more potential savings Issues: Limited budget for codec Must privilege simple encoding schemes Strict interaction with memory library Must match encoding scheme to memory interface e.g., redundant buses 9