Multiplicationless DFT Calculation Using New Algorithms
|
|
- Brandon Henry
- 5 years ago
- Views:
Transcription
1 Multiplicationless DT Calculation Using ew Algorithms Jaya Krishna Sunkara, Chiranjeevi Muppala PG Scholar, SVUCE, Tirupati, IDIA. Asst. Prof., TJS College of Engineering, Anna University, IDIA. Abstract ew telecommunication systems are based more than ever before on digital signal processing. High speed digital telecommunication systems such as ODM and DSL need real-time high-speed computation of the Discrete ourier Transform. Thus there is a need of innovative methods to improve the speed. In this paper, we propose new methods to implement DT in an efficient way. The proposed schemes come with the simplest and efficient way to solve the complex DT calculation with less number of multiplications and additions. The methods proposed change the DT and T algorithms by considering the values of input signal. The simulation results have verified that the number of complex additions and multiplications have reduced drastically when compared to the direct evaluation and T.. Introduction rom a theoretical point of view, the complexity issue of the discrete ourier transform has reached a certain maturity. ote that Gauss, in his time, did not even count the number of operations necessary in his algorithm. In particular, Winograd's work on DTs whose lengths have coprime factors both sets lower bounds (on the number of multiplications) and gives algorithms to achieve these []-[3], although they are not always practical ones. Similar work was done for length-" DTs, showing the linear multiplicative complexity of the algorithm [4]-[7] but also the lack of practical algorithms achieving this minimum (due to the tremendous increase in the number of additions [8][9]). Considering implementations, the situation is of course more involved since many more parameters have to be taken into account than just the number of operations. evertheless, it seems that both the radix-4 and the split-radix algorithm are quite popular for lengths which are powers of, while the PA, thanks to its better structure and easier implementation, wins over the WTA for lengths having coprime factors []- []. Recently, however, new questions have come up because in software on the one hand, new processors may require different solutions (vector processors, signal processors), and on the other hand, the advent of VLSI for hardware implementations sets new constraints (desire for simple structures, high cost of multiplications versus additions). ew algorithms are proposed in [3]-[9] recently. In this paper four methods are proposed for the implementation of DT with less number of additions and multiplications. The method- method will require less number of complex multiplications and complex additions as compared with the direct evaluation method of DT. method- method relays on the property of complex conjugation and it is applicable to real sequence only. The method- method will require less number of complex multiplications and complex additions as compared with the method- method. In method- method, the property of twiddle factor was exploited. T is superior to the first two methods. But, the method-3 method avoids all trivial multiplications in T. Hence, it reduces the total number of complex multiplications to lesser than that of T. By using method-4 method, in cases the number of multiplications and additions can be zero. This can be done by checking the input. The rest of the paper is structured as follows. The next two sections discuss the first two methods proposed. Section IV presents standard T. Section V and VI presents the remaining two methods proposed. Section VII concludes the paper.. Method - A notable reduction in number of multiplications and additions is possible by applying the following property: * X ( k) X ( k) Here we need to calculate first coefficients using direct evaluation DT. The remaining coefficients can be evaluated with no extra multiplications or additions. By using method- method will require less number of complex multiplications and complex additions as compared IJCTA Mar-Apr 5 3
2 with the direct evaluation method of DT. In method- method, the number of multiplications for point DT is and the number of additions is ( ), where direct evaluation of DT requires number of complex multiplications and ( ) complex additions. TABLE I: UMBER O COMPLEX MULTIPLICATIOS AD COMPLEX ADDITIOS I METHOD- ig. Evaluation of 4-point DT using method- method umber of umber of or example, in 8 point DT can evaluated first 5 (i.e. + (/) =+8/ = 5) terms are evaluated and then next 3 terms are evaluated directly by using the conjugation property. X (5) = x*(8-5) = x*(3) X (6) = x*(8-6) = x*() X (7) = x*(8-7) = x*() 3. Method- The method- method will require less number of complex multiplications and complex additions as compared with the method- method. In method- method, the property of twiddle factor was exploited. T is superior to the first two methods. In method- by applying decimation operation in time, we can add the multiplicands of W p, W p+, etc., hence reducing the total number of. The 4-point DT calculation with respect to figure is given below. ig. Evaluation of 8-point DT using method- method orm the above diagram, the number of complex multiplications as well as complex additions are log = 8log 8 = 4 TABLE II: UMBER O COMPLEX MULTIPLICATIOS AD COMPLEX ADDITIOS I METHOD- umber of umber of Stage-I Stage-II () x() () x() () x() () x() x() x() x(3) x(3) X () () W X () () W X (3) () W () () Here the number of multiplications and additions are reduced as compare to method. In this method there are log multiplications and additions, in each butterfly diagram, for each one there are two multiplications. The evaluation of 8-point DT using method- is shown in figure. X () () W 3 () () 4. Standard ast ourier Transform DT is one of the most important tools in the field of digital signal processing. Due to its computational complexity, several T algorithms have been developed over the years. The most popular T algorithms are the Cooley-Tukey algorithms. It has been shown that the decimation-in-time (DIT) algorithms provide better signal-to-noise-ratio than the decimation-in-frequency algorithms when finite word length is used. The T butterfly structure is shown in the figure 3. IJCTA Mar-Apr 5 3
3 ig. 3 Butterfly structure of standard T ig. 5 Evaluation of 8-point DT using Method-3 TABLE III: UMBER O COMPLEX MULTIPLICATIOS AD COMPLEX ADDITIOS I METHOD-3 umber of umber of ig. 4 DIT-T calculation DIT-T calculation is shown in the figure 4. DIT is used to calculate the DT of a point sequence. The idea is used to break the point sequence into two sequences, the DT of which can be combined to give the DT of the original point sequence. Initially the -point sequence divided into (/) point sequences X e (n) and X o (n), which have the even and odd members of X(n) respectively. The (/) point DT of these two sequences are evaluated and combined to give the - point DT. 5. Method - 3 In this method-3 all trivial multiplications, i.e., multiplications with W are reduced. Hence, it reduces the total number of complex multiplications to lesser than that of T. In the calculation of -point DT using T (-) such multiplications are there. So, the number of complex multiplications in this method-3 method is log. The evaluation of DT using method-3 is shown in figure 5. The table 3 gives the number of complex additions and multiplications required in method Method-4 In method-4, depending on the inputs to every stage, the multiplications and additions will be performed as and when required. If the one of the input sample is say, then the first multiplication need not be performed, and if the input sample is, both the addition and multiplications are not required. Like this, in cases, DT can be found with zero multiplications also. The table 4 shows the comparison of number of multiplication of various techniques is given. The comparison is plotted in the figure 6. Obviously, the method-4 requires at most the number of additions and multiplications as required by the method-3. Hence the worst-case performance of method-4 is that of method- 3. ow, the best and better cases of method-4 is given in tables 5 and 6 one for 4-point and other for 8-point. TABLE IV: UMBER O MULTIPLICATIOS I THE CALCULATIO O DT DT Method- Method- T Method IJCTA Mar-Apr 5 3
4 References ig. 6 Comparison of number of multiplications required in different techniques TABLE V: UMBER O MULTIPLICATIOS REQUIRED I VARIOUS TECHIQUES OR DIERET SEQUECES O LEGTH 4 Sequence DT M- M- T M-3 M-4 {,,,} {,,,} {,,3,4} {,,,} {,,,} TABLE VI: UMBER O MULTIPLICATIOS REQUIRED I VARIOUS TECHIQUES OR DIERET SEQUECES O LEGTH 8 Sequence DT M- M- T M-3 M-4 {,,,,,,,} {,,,,,,,} {,,,,,,,} {,,,,,,,} {,,,3,4,5,6,7} Conclusions The speed of calculation of DT is crucial in many applications including medical, military and space applications. The hardware required is other concern. In this paper, an attempt has been made to reduce the number of complex additions and multiplications required to perform DT using various methods. The method- uses the property of twiddle factor and tries to substitute the calculated DT coefficients to find the remaining coefficients. The method- modifies the butterfly structure to add the common multiples of twiddle factor but found to involve more calculations than T. The method-3 skips the trivial multiplications and method-4 skips both trivial multiplications and additions. The algorithms are simulated in language C on Windows 7 machine. The suitable hardware implementations particularly the comparators have to be studied, and has to be verified for longer sequence lengths, say = 4. [] A Steven G. Johnson and Matteo rigo, A modified split-radix T with fewer arithmetic operations, IEEE Transactions on Signal Processing, 55 (), 9, 7. [] G. Plonka and M. Tasche, ast and numerically stable algorithms for discrete cosine transforms, Linear Algebra Appl., vol. 394, pp , 5. [3] M. P uschel, J. M.. Moura, J. R. Johnson, D. Padua, M. M. Veloso, B. W. Singer, J. Xiong,. ranchetti, A. Gaˇci c, Y. Voronenko, K. Chen, R. W. Johnson, and. Rizzolo, SPIRAL: Code generation for DSP transforms, Proc. IEEE, vol. 93, no., pp. 3 75, 5. [4] S. Bouguezel, M. O. Ahmad, and M.. S. Swamy, A new radix-/8 T algorithm for length-q m DTs, IEEE Trans. Circuits Syst. I, vol. 5, no. 9, pp , 4. [5] M. rigo and S. G. Johnson, The design and implementation of TW3, Proc. IEEE, vol. 93, no., pp. 6 3, 5. [6] P. Duhamel and H. Hollmann, Split-radix T algorithm, Electron. Lett., vol., no., pp. 4 6, 984. [7] M. Vetterli and H. J. ussbaumer, Simple T and DCT algorithms with reduced number of operations, Signal Processing, vol. 6, no. 4, pp , 984. [8] J. B. Martens, Recursive cyclotomic factorization a new algorithm for calculating the discrete ourier transform, IEEE Trans. Acoust., Speech, Signal Processing, vol. 3, no. 4, pp , 984. [9] H. Sorensen, M. Heideman, and C. Burrus, On computing the split-radix T, Acoustics, Speech and Signal Processing, IEEE Transactions on, 34():5 56, 3. [] K.A. Sakallah, Symmetry and satisfiability, Handbook of Satisfiability, pages , 9. [] S. Ranise and C. Tinelli, The SMT-LIB standard: Version., Department of Computer Science, The University of Iowa, Tech. Rep, 6. [] R. ieuwenhuis and A. Oliveras, On sat modulo theories and optimization problems, Theory and Applications of Satisfiability Testing-SAT 6, pages 56 69, 6. [3] R. ieuwenhuis, A. Oliveras, and C. Tinelli, Solving SAT and SAT Modulo Theories: rom an abstract Davis Putnam Logemann Loveland procedure to DPLL (T), Journal of the ACM (JACM), 53(6): , 6. [4] G. ordin, P.A. Milder, J.C. Hoe, and M. Püschel, Automatic generation of customized discrete ourier transform IPs, In Proceedings of the 4nd annual Design Automation Conference, pages ACM, 5. [5] T. Lundy and J. Van Buskirk, A new matrix approach to real Ts and convolutions of length k, Computing, 8():3 45, 7. IJCTA Mar-Apr 5 33
5 [6] V. Manquinho, O. Roussel, and M. Deters, Pseudo- Boolean Competition, [7] T. Mateer, ast ourier transform algorithms with applications, PhD thesis, Clemson University, 8. [8] A. Mishchenko. ABC: A System for Sequential Synthesis and Verification. [9] M.W. Moskewicz, C.. Madigan, Y. Zhao, L. Zhang, and S. Malik, Chaff: Engineering an efficient SAT solver, Design Automation Conference, Proceedings, pages , IEEE..B. Smith, C.D. Jones, and E.. Roberts, Article Title, Journal, Publisher, Location, Date, pp. -. Author s Profile Jaya Krishna Sunkara received B.Tech in Electronics and Communication Engineering from GKCE, Sullurpet (JTU HYD) in 6 and M.E in Information Technology from UVCE, Bangalore (Bangalore University Campus) in 9. He has held various positions in Priyadarshini college of Engineering, Sullurpet including Asst. Prof., Head of the Dept., Training & Placement Officer during 9-4. Currently he is doing his Masters in Signal Processing in SVUCE, Tirupati (Sri Venkateswara University Campus). He stood University first in ME and also qualified in GATE for 7 times, four times in EC and thrice in CS. He has published eight research papers in national and international journals. His research interests include Signal and Image Processing. Chiranjeevi Muppala received B.Tech in Electronics and Communication Engineering from KMCET, JTU HYD in 8 and M.Tech in VLSI System Design from Anuraag Engineering College, JTU HYD in. He is working as Asst. Prof., in TJS Engineering College, Anna University. Previously, he worked as Asst. Prof., in Priyadarshini college of Engineering, Sullurpet during -3. His research interests include Signal and Image Processing, VLSI Design. IJCTA Mar-Apr 5 34
MULTIPLIERLESS HIGH PERFORMANCE FFT COMPUTATION
MULTIPLIERLESS HIGH PERFORMANCE FFT COMPUTATION Maheshwari.U 1, Josephine Sugan Priya. 2, 1 PG Student, Dept Of Communication Systems Engg, Idhaya Engg. College For Women, 2 Asst Prof, Dept Of Communication
More informationAbstract. Literature Survey. Introduction. A.Radix-2/8 FFT algorithm for length qx2 m DFTs
Implementation of Split Radix algorithm for length 6 m DFT using VLSI J.Nancy, PG Scholar,PSNA College of Engineering and Technology; S.Bharath,Assistant Professor,PSNA College of Engineering and Technology;J.Wilson,Assistant
More informationLOW-POWER SPLIT-RADIX FFT PROCESSORS
LOW-POWER SPLIT-RADIX FFT PROCESSORS Avinash 1, Manjunath Managuli 2, Suresh Babu D 3 ABSTRACT To design a split radix fast Fourier transform is an ideal person for the implementing of a low-power FFT
More informationDESIGN OF PARALLEL PIPELINED FEED FORWARD ARCHITECTURE FOR ZERO FREQUENCY & MINIMUM COMPUTATION (ZMC) ALGORITHM OF FFT
IMPACT: International Journal of Research in Engineering & Technology (IMPACT: IJRET) ISSN(E): 2321-8843; ISSN(P): 2347-4599 Vol. 2, Issue 4, Apr 2014, 199-206 Impact Journals DESIGN OF PARALLEL PIPELINED
More informationFPGA Based Design and Simulation of 32- Point FFT Through Radix-2 DIT Algorith
FPGA Based Design and Simulation of 32- Point FFT Through Radix-2 DIT Algorith Sudhanshu Mohan Khare M.Tech (perusing), Dept. of ECE Laxmi Naraian College of Technology, Bhopal, India M. Zahid Alam Associate
More informationThe Barcelogic SMT Solver
The Barcelogic SMT Solver Tool Paper Miquel Bofill 1, Robert Nieuwenhuis 2, Albert Oliveras 2, Enric Rodríguez-Carbonell 2, and Albert Rubio 2 1 Universitat de Girona 2 Technical University of Catalonia,
More informationSystem Demonstration of Spiral: Generator for High-Performance Linear Transform Libraries
System Demonstration of Spiral: Generator for High-Performance Linear Transform Libraries Yevgen Voronenko, Franz Franchetti, Frédéric de Mesmay, and Markus Püschel Department of Electrical and Computer
More informationAN FFT PROCESSOR BASED ON 16-POINT MODULE
AN FFT PROCESSOR BASED ON 6-POINT MODULE Weidong Li, Mark Vesterbacka and Lars Wanhammar Electronics Systems, Dept. of EE., Linköping University SE-58 8 LINKÖPING, SWEDEN E-mail: {weidongl, markv, larsw}@isy.liu.se,
More informationResearch Article International Journal of Emerging Research in Management &Technology ISSN: (Volume-6, Issue-8) Abstract:
International Journal of Emerging Research in Management &Technology Research Article August 27 Design and Implementation of Fast Fourier Transform (FFT) using VHDL Code Akarshika Singhal, Anjana Goen,
More informationTwiddle Factor Transformation for Pipelined FFT Processing
Twiddle Factor Transformation for Pipelined FFT Processing In-Cheol Park, WonHee Son, and Ji-Hoon Kim School of EECS, Korea Advanced Institute of Science and Technology, Daejeon, Korea icpark@ee.kaist.ac.kr,
More informationThe Tangent FFT. Daniel J. Bernstein
The Tangent FFT Daniel J. Bernstein Department of Mathematics, Statistics, and Computer Science (M/C 249) University of Illinois at Chicago, Chicago, IL 60607 7045, USA djb@cr.yp.to Abstract. The split-radix
More informationEfficient Methods for FFT calculations Using Memory Reduction Techniques.
Efficient Methods for FFT calculations Using Memory Reduction Techniques. N. Kalaiarasi Assistant professor SRM University Kattankulathur, chennai A.Rathinam Assistant professor SRM University Kattankulathur,chennai
More informationDocument Version: Publisher s PDF, also known as Version of Record (includes final page, issue and volume numbers)
The tangent FFT Citation for published version (APA): Bernstein, D. J. (2007). The tangent FFT. In S. Boztas, & H. F. Lu (Eds.), Applied Algebra, Algebraic Algorithms and Error-Correcting Codes (17th International
More informationGenerating Parallel Transforms Using Spiral
Generating Parallel Transforms Using Spiral Franz Franchetti Yevgen Voronenko Markus Püschel Part of the Spiral Team Electrical and Computer Engineering Carnegie Mellon University Sponsors: DARPA DESA
More informationThe Serial Commutator FFT
The Serial Commutator FFT Mario Garrido Gálvez, Shen-Jui Huang, Sau-Gee Chen and Oscar Gustafsson Journal Article N.B.: When citing this work, cite the original article. 2016 IEEE. Personal use of this
More informationEfficient FFT Algorithm and Programming Tricks
Connexions module: m12021 1 Efficient FFT Algorithm and Programming Tricks Douglas L. Jones This work is produced by The Connexions Project and licensed under the Creative Commons Attribution License Abstract
More informationEfficient Radix-4 and Radix-8 Butterfly Elements
Efficient Radix4 and Radix8 Butterfly Elements Weidong Li and Lars Wanhammar Electronics Systems, Department of Electrical Engineering Linköping University, SE581 83 Linköping, Sweden Tel.: +46 13 28 {1721,
More informationFFT. There are many ways to decompose an FFT [Rabiner and Gold] The simplest ones are radix-2 Computation made up of radix-2 butterflies X = A + BW
FFT There are many ways to decompose an FFT [Rabiner and Gold] The simplest ones are radix-2 Computation made up of radix-2 butterflies A X = A + BW B Y = A BW B. Baas 442 FFT Dataflow Diagram Dataflow
More informationIMPROVED EXECUTION TIME FOR 2048 POINT FFT/IFFT
http:// IPROVED EECTION TIE OR 2048 POINT T/IT ASTRACT 1 pasana Sharma, 2 Waffa Choudhary 1,2 Electronics & Communication Department, AES Engg. College, Ghaziabad.(India) This paper represents 2048 point
More informationLinköping University Post Print. Analysis of Twiddle Factor Memory Complexity of Radix-2^i Pipelined FFTs
Linköping University Post Print Analysis of Twiddle Factor Complexity of Radix-2^i Pipelined FFTs Fahad Qureshi and Oscar Gustafsson N.B.: When citing this work, cite the original article. 200 IEEE. Personal
More informationA Novel Distributed Arithmetic Multiplierless Approach for Computing Complex Inner Products
606 Int'l Conf. Par. and Dist. Proc. Tech. and Appl. PDPTA'5 A ovel Distributed Arithmetic Multiplierless Approach for Computing Complex Inner Products evin. Bowlyn, and azeih M. Botros. Ph.D. Candidate,
More informationOn Resolution Proofs for Combinational Equivalence Checking
On Resolution Proofs for Combinational Equivalence Checking Satrajit Chatterjee Alan Mishchenko Robert Brayton Department of EECS U. C. Berkeley {satrajit, alanmi, brayton}@eecs.berkeley.edu Andreas Kuehlmann
More informationHigh Throughput Energy Efficient Parallel FFT Architecture on FPGAs
High Throughput Energy Efficient Parallel FFT Architecture on FPGAs Ren Chen Ming Hsieh Department of Electrical Engineering University of Southern California Los Angeles, USA 989 Email: renchen@usc.edu
More informationAnalysis of Radix- SDF Pipeline FFT Architecture in VLSI Using Chip Scope
Analysis of Radix- SDF Pipeline FFT Architecture in VLSI Using Chip Scope G. Mohana Durga 1, D.V.R. Mohan 2 1 M.Tech Student, 2 Professor, Department of ECE, SRKR Engineering College, Bhimavaram, Andhra
More informationFFT ALGORITHMS FOR MULTIPLY-ADD ARCHITECTURES
FFT ALGORITHMS FOR MULTIPLY-ADD ARCHITECTURES FRANCHETTI Franz, (AUT), KALTENBERGER Florian, (AUT), UEBERHUBER Christoph W. (AUT) Abstract. FFTs are the single most important algorithms in science and
More informationSplit-Radix FFT Algorithms Based on Ternary Tree
International Journal of Science Vol.3 o.5 016 ISS: 1813-4890 Split-Radix FFT Algorithms Based on Ternary Tree Ming Zhang School of Computer Science and Technology, University of Science and Technology
More informationReconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT in FPGA Technology
Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT in FPGA Technology N.VEDA KUMAR, BADDAM CHAMANTHI Assistant Professor, M.TECH STUDENT Dept of ECE,Megha Institute
More informationFault Tolerant Parallel Filters Based on ECC Codes
Advances in Computational Sciences and Technology ISSN 0973-6107 Volume 11, Number 7 (2018) pp. 597-605 Research India Publications http://www.ripublication.com Fault Tolerant Parallel Filters Based on
More informationThe Fast Fourier Transform Algorithm and Its Application in Digital Image Processing
The Fast Fourier Transform Algorithm and Its Application in Digital Image Processing S.Arunachalam(Associate Professor) Department of Mathematics, Rizvi College of Arts, Science & Commerce, Bandra (West),
More informationParallel-computing approach for FFT implementation on digital signal processor (DSP)
Parallel-computing approach for FFT implementation on digital signal processor (DSP) Yi-Pin Hsu and Shin-Yu Lin Abstract An efficient parallel form in digital signal processor can improve the algorithm
More informationDesign and Implementation of VLSI Architecture for. Mixed Radix FFT
International Journal of Scientific & Engineering Research, Volume 3, Issue 11, November-2012 1 Design and Implementation of VLSI Architecture for Mixed Radix FFT DrYPadma Sai*, YSwetha Sree* * (Department
More informationAn efficient multiplierless approximation of the fast Fourier transform using sum-of-powers-of-two (SOPOT) coefficients
Title An efficient multiplierless approximation of the fast Fourier transm using sum-of-powers-of-two (SOPOT) coefficients Author(s) Chan, SC; Yiu, PM Citation Ieee Signal Processing Letters, 2002, v.
More informationOn Resolution Proofs for Combinational Equivalence
33.4 On Resolution Proofs for Combinational Equivalence Satrajit Chatterjee Alan Mishchenko Robert Brayton Department of EECS U. C. Berkeley {satrajit, alanmi, brayton}@eecs.berkeley.edu Andreas Kuehlmann
More informationStochastic Search for Signal Processing Algorithm Optimization
Stochastic Search for Signal Processing Algorithm Optimization Bryan Singer Manuela Veloso May, 01 CMU-CS-01-137 School of Computer Science Carnegie Mellon University Pittsburgh, PA 1213 Abstract Many
More informationResearch Article Regressive Structures for Computation of DST-II and Its Inverse
International Scholarly Research etwork ISR Electronics Volume 01 Article ID 537469 4 pages doi:10.540/01/537469 Research Article Regressive Structures for Computation of DST-II and Its Inverse Priyanka
More informationLearning Techniques for Pseudo-Boolean Solving and Optimization
Learning Techniques for Pseudo-Boolean Solving and Optimization José Faustino Fragoso Fremenin dos Santos September 29, 2008 Abstract The extension of conflict-based learning from Propositional Satisfiability
More informationImplementation of Lifting-Based Two Dimensional Discrete Wavelet Transform on FPGA Using Pipeline Architecture
International Journal of Computer Trends and Technology (IJCTT) volume 5 number 5 Nov 2013 Implementation of Lifting-Based Two Dimensional Discrete Wavelet Transform on FPGA Using Pipeline Architecture
More informationAn Introduction to SAT Solvers
An Introduction to SAT Solvers Knowles Atchison, Jr. Fall 2012 Johns Hopkins University Computational Complexity Research Paper December 11, 2012 Abstract As the first known example of an NP Complete problem,
More informationM.N.MURTY Department of Physics, National Institute of Science and Technology, Palur Hills, Berhampur , Odisha (INDIA).
M..MURTY / International Journal of Engineering Research and Applications (IJERA) ISS: 48-96 www.ijera.com Vol. 3, Issue 3, May-Jun 013, pp.60-608 Radix- Algorithms for Implementation of Type-II Discrete
More informationMassively Parallel Seesaw Search for MAX-SAT
Massively Parallel Seesaw Search for MAX-SAT Harshad Paradkar Rochester Institute of Technology hp7212@rit.edu Prof. Alan Kaminsky (Advisor) Rochester Institute of Technology ark@cs.rit.edu Abstract The
More informationA Pearl on SAT Solving in Prolog (extended abstract)
A Pearl on SAT Solving in Prolog (extended abstract) Jacob M. Howe and Andy King 1 Introduction The Boolean satisfiability problem, SAT, is of continuing interest because a variety of problems are naturally
More informationDUE to the high computational complexity and real-time
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 15, NO. 3, MARCH 2005 445 A Memory-Efficient Realization of Cyclic Convolution and Its Application to Discrete Cosine Transform Hun-Chen
More informationSpeed Optimised CORDIC Based Fast Algorithm for DCT
GRD Journals Global Research and Development Journal for Engineering International Conference on Innovations in Engineering and Technology (ICIET) - 2016 July 2016 e-issn: 2455-5703 Speed Optimised CORDIC
More informationIJSRD - International Journal for Scientific Research & Development Vol. 4, Issue 05, 2016 ISSN (online):
IJSRD - International Journal for Scientific Research & Development Vol. 4, Issue 05, 2016 ISSN (online): 2321-0613 A Reconfigurable and Scalable Architecture for Discrete Cosine Transform Maitra S Aldi
More informationENT 315 Medical Signal Processing CHAPTER 3 FAST FOURIER TRANSFORM. Dr. Lim Chee Chin
ENT 315 Medical Signal Processing CHAPTER 3 FAST FOURIER TRANSFORM Dr. Lim Chee Chin Outline Definition and Introduction FFT Properties of FFT Algorithm of FFT Decimate in Time (DIT) FFT Steps for radix
More informationArea And Power Efficient LMS Adaptive Filter With Low Adaptation Delay
e-issn: 2349-9745 p-issn: 2393-8161 Scientific Journal Impact Factor (SJIF): 1.711 International Journal of Modern Trends in Engineering and Research www.ijmter.com Area And Power Efficient LMS Adaptive
More informationImplementation of digit serial fir filter using wireless priority service(wps)
Implementation of digit serial fir filter using wireless priority service(wps) S.Aruna Assistant professor,ece department MVSR Engineering College Nadergul,Hyderabad-501510 V.Sravanthi PG Scholar, ECE
More informationImplementation of FFT Processor using Urdhva Tiryakbhyam Sutra of Vedic Mathematics
Implementation of FFT Processor using Urdhva Tiryakbhyam Sutra of Vedic Mathematics Yojana Jadhav 1, A.P. Hatkar 2 PG Student [VLSI & Embedded system], Dept. of ECE, S.V.I.T Engineering College, Chincholi,
More informationFAST FOURIER TRANSFORM (FFT) and inverse fast
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004 2005 A Dynamic Scaling FFT Processor for DVB-T Applications Yu-Wei Lin, Hsuan-Yu Liu, and Chen-Yi Lee Abstract This paper presents an
More informationBetter test results for the graph coloring and the Pigeonhole Problems using DPLL with k-literal representation
Proceedings of the 7 th International Conference on Applied Informatics Eger, Hungary, January 28 31, 2007. Vol. 2. pp. 127 135. Better test results for the graph coloring and the Pigeonhole Problems using
More informationA modified split-radix FFT with fewer arithmetic operations
1 A modified split-radix FFT with fewer arithmetic operations Steven G. Johnson* and Matteo Frigo Abstract Recent results by Van Busir et al. have broen the record set by Yavne in 1968 for the lowest exact
More informationSPIRAL Generated Modular FFTs *
SPIRAL Generated Modular FFTs * Jeremy Johnson Lingchuan Meng Drexel University * The work is supported by DARPA DESA, NSF, and Intel. Material for SPIRAL overview provided by Franz Francheti, Yevgen Voronenko,,
More informationStreamlined real-factor FFTs
18th European Signal Processing Conference (EUSIPCO-010 Aalborg, Denmark, August 3-7, 010 Streamlined real-factor FFTs Mohammed Zafar Ali Khan ICSL IIT, Hyderabad-5005,India Email: zafar@iith.ac.in Shaik
More informationFast Block LMS Adaptive Filter Using DA Technique for High Performance in FGPA
Fast Block LMS Adaptive Filter Using DA Technique for High Performance in FGPA Nagaraj Gowd H 1, K.Santha 2, I.V.Rameswar Reddy 3 1, 2, 3 Dept. Of ECE, AVR & SVR Engineering College, Kurnool, A.P, India
More informationKeywords: Fast Fourier Transforms (FFT), Multipath Delay Commutator (MDC), Pipelined Architecture, Radix-2 k, VLSI.
ww.semargroup.org www.ijvdcs.org ISSN 2322-0929 Vol.02, Issue.05, August-2014, Pages:0294-0298 Radix-2 k Feed Forward FFT Architectures K.KIRAN KUMAR 1, M.MADHU BABU 2 1 PG Scholar, Dept of VLSI & ES,
More informationFast Fourier Transform Architectures: A Survey and State of the Art
Fast Fourier Transform Architectures: A Survey and State of the Art 1 Anwar Bhasha Pattan, 2 Dr. M. Madhavi Latha 1 Research Scholar, Dept. of ECE, JNTUH, Hyderabad, India 2 Professor, Dept. of ECE, JNTUH,
More informationRadix-4 FFT Algorithms *
OpenStax-CNX module: m107 1 Radix-4 FFT Algorithms * Douglas L Jones This work is produced by OpenStax-CNX and licensed under the Creative Commons Attribution License 10 The radix-4 decimation-in-time
More informationConstraint Satisfaction Problems
Constraint Satisfaction Problems Tuomas Sandholm Carnegie Mellon University Computer Science Department [Read Chapter 6 of Russell & Norvig] Constraint satisfaction problems (CSPs) Standard search problem:
More informationA High Speed Design of 32 Bit Multiplier Using Modified CSLA
Journal From the SelectedWorks of Journal October, 2014 A High Speed Design of 32 Bit Multiplier Using Modified CSLA Vijaya kumar vadladi David Solomon Raju. Y This work is licensed under a Creative Commons
More informationSPIRAL Overview: Automatic Generation of DSP Algorithms & More *
SPIRAL Overview: Automatic Generation of DSP Algorithms & More * Jeremy Johnson (& SPIRAL Team) Drexel University * The work is supported by DARPA DESA, NSF, and Intel. Material for presentation provided
More informationA Novel Design of 32 Bit Unsigned Multiplier Using Modified CSLA
A Novel Design of 32 Bit Unsigned Multiplier Using Modified CSLA Chandana Pittala 1, Devadas Matta 2 PG Scholar.VLSI System Design 1, Asst. Prof. ECE Dept. 2, Vaagdevi College of Engineering,Warangal,India.
More informationOPTIMIZING THE POWER USING FUSED ADD MULTIPLIER
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology IJCSMC, Vol. 3, Issue. 11, November 2014,
More informationThree-D DWT of Efficient Architecture
Bonfring International Journal of Advances in Image Processing, Vol. 1, Special Issue, December 2011 6 Three-D DWT of Efficient Architecture S. Suresh, K. Rajasekhar, M. Venugopal Rao, Dr.B.V. Rammohan
More informationHIGH SPEED REALISATION OF DIGITAL FILTERS
HIGH SPEED REALISATION OF DIGITAL FILTERS A THESIS SUBMITTED FOR THE DEGREE OF MASTER OF PHILOSOPHY IN ELECTRICAL AND ELECTRONIC ENGINEERING AT THE UNIVERSITY OF HONG KONG BY TSIM TS1M MAN-TAT, JIMMY DEPARTMENT
More informationTHE orthogonal frequency-division multiplex (OFDM)
26 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 57, NO. 1, JANUARY 2010 A Generalized Mixed-Radix Algorithm for Memory-Based FFT Processors Chen-Fong Hsiao, Yuan Chen, Member, IEEE,
More informationSum to Modified Booth Recoding Techniques For Efficient Design of the Fused Add-Multiply Operator
Sum to Modified Booth Recoding Techniques For Efficient Design of the Fused Add-Multiply Operator D.S. Vanaja 1, S. Sandeep 2 1 M. Tech scholar in VLSI System Design, Department of ECE, Sri VenkatesaPerumal
More informationNovel design of multiplier-less FFT processors
Signal Processing 8 (00) 140 140 www.elsevier.com/locate/sigpro Novel design of multiplier-less FFT processors Yuan Zhou, J.M. Noras, S.J. Shepherd School of EDT, University of Bradford, Bradford, West
More informationHigh Speed Multiplication Using BCD Codes For DSP Applications
High Speed Multiplication Using BCD Codes For DSP Applications Balasundaram 1, Dr. R. Vijayabhasker 2 PG Scholar, Dept. Electronics & Communication Engineering, Anna University Regional Centre, Coimbatore,
More informationType-IV DCT, DST, and MDCT algorithms with reduced numbers of arithmetic operations
1 Type-IV DCT, DST, and MDCT algorithms with reduced numbers of arithmetic operations Xuancheng Shao and Steven G. Johnson* arxiv:0708.4399v [cs.ds] 9 Jan 009 Abstract We present algorithms for the type-iv
More informationChapter 3 Classification of FFT Processor Algorithms
Chapter Classificatio of FFT Processor Algorithms The computatioal complexity of the Discrete Fourier trasform (DFT) is very high. It requires () 2 complex multiplicatios ad () complex additios [5]. As
More informationEquivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs
Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs Takeshi Matsumoto, Hiroshi Saito, and Masahiro Fujita Dept. of Electronics Engineering, University of Tokyo
More informationSoftware Implementation of Break-Up Algorithm for Logic Minimization
vol. 2, no. 6. 2, pp. 141-145, 2017 DOI: https://doi.org/10.24999/ijoaem/02060034 Software Implementation of Break-Up Algorithm for Logic Minimization Koustuvmoni Bharadwaj and Sahadev Roy Abstract In
More informationParallelism in Spiral
Parallelism in Spiral Franz Franchetti and the Spiral team (only part shown) Electrical and Computer Engineering Carnegie Mellon University Joint work with Yevgen Voronenko Markus Püschel This work was
More informationStochastic Search for Signal Processing Algorithm Optimization
Stochastic Search for Signal Processing Algorithm Optimization Bryan Singer and Manuela Veloso Computer Science Department Carnegie Mellon University Pittsburgh, PA 1213 Email: {bsinger+, mmv+}@cs.cmu.edu
More informationAn Area Efficient Mixed Decimation MDF Architecture for Radix. Parallel FFT
An Area Efficient Mixed Decimation MDF Architecture for Radix Parallel FFT Reshma K J 1, Prof. Ebin M Manuel 2 1M-Tech, Dept. of ECE Engineering, Government Engineering College, Idukki, Kerala, India 2Professor,
More informationEvaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits
Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits André Sülflow Ulrich Kühne Robert Wille Daniel Große Rolf Drechsler Institute of Computer Science University of Bremen
More informationDesign and Implementation of CVNS Based Low Power 64-Bit Adder
Design and Implementation of CVNS Based Low Power 64-Bit Adder Ch.Vijay Kumar Department of ECE Embedded Systems & VLSI Design Vishakhapatnam, India Sri.Sagara Pandu Department of ECE Embedded Systems
More informationUsing Synthesis Techniques in SAT Solvers
1. Introduction Using Synthesis Techniques in SAT Solvers Rolf Drechsler Institute of Computer Science University of Bremen 28359 Bremen, Germany drechsle@informatik.uni-bremen.de Abstract In many application
More informationHigh Performance Pipelined Design for FFT Processor based on FPGA
High Performance Pipelined Design for FFT Processor based on FPGA A.A. Raut 1, S. M. Kate 2 1 Sinhgad Institute of Technology, Lonavala, Pune University, India 2 Sinhgad Institute of Technology, Lonavala,
More informationImplementation of Efficient Modified Booth Recoder for Fused Sum-Product Operator
Implementation of Efficient Modified Booth Recoder for Fused Sum-Product Operator A.Sindhu 1, K.PriyaMeenakshi 2 PG Student [VLSI], Dept. of ECE, Muthayammal Engineering College, Rasipuram, Tamil Nadu,
More informationFPGA Implementation of 16-Point Radix-4 Complex FFT Core Using NEDA
FPGA Implementation of 16-Point FFT Core Using NEDA Abhishek Mankar, Ansuman Diptisankar Das and N Prasad Abstract--NEDA is one of the techniques to implement many digital signal processing systems that
More informationDesign And Simulation Of Pipelined Radix-2 k Feed-Forward FFT Architectures
Design And Simulation Of Pipelined Radix-2 k Feed-Forward FFT Architectures T.S. Ghouse basha 1, Peerla Sabeena sulthana 2 Associate Professor and Head of Department, KORM Engineering College, Kadapa,
More informationPRIME FACTOR CYCLOTOMIC FOURIER TRANSFORMS WITH REDUCED COMPLEXITY OVER FINITE FIELDS
PRIME FACTOR CYCLOTOMIC FOURIER TRANSFORMS WITH REDUCED COMPLEXITY OVER FINITE FIELDS Xuebin Wu, Zhiyuan Yan, Ning Chen, and Meghanad Wagh Department of ECE, Lehigh University, Bethlehem, PA 18015 PMC-Sierra
More informationPower and Area Efficient Implementation for Parallel FIR Filters Using FFAs and DA
Power and Area Efficient Implementation for Parallel FIR Filters Using FFAs and DA Krishnapriya P.N 1, Arathy Iyer 2 M.Tech Student [VLSI & Embedded Systems], Sree Narayana Gurukulam College of Engineering,
More informationDesign of Delay Efficient Distributed Arithmetic Based Split Radix FFT
Design of Delay Efficient Arithmetic Based Split Radix FFT Nisha Laguri #1, K. Anusudha *2 #1 M.Tech Student, Electronics, Department of Electronics Engineering, Pondicherry University, Puducherry, India
More informationVLSI IMPLEMENTATION AND PERFORMANCE ANALYSIS OF EFFICIENT MIXED-RADIX 8-2 FFT ALGORITHM WITH BIT REVERSAL FOR THE OUTPUT SEQUENCES.
VLSI IMPLEMENTATION AND PERFORMANCE ANALYSIS OF EFFICIENT MIXED-RADIX 8-2 ALGORITHM WITH BIT REVERSAL FOR THE OUTPUT SEQUENCES. M. MOHAMED ISMAIL Dr. M.J.S RANGACHAR Dr.Ch. D. V. PARADESI RAO (Research
More informationPower Optimized Programmable Truncated Multiplier and Accumulator Using Reversible Adder
Power Optimized Programmable Truncated Multiplier and Accumulator Using Reversible Adder Syeda Mohtashima Siddiqui M.Tech (VLSI & Embedded Systems) Department of ECE G Pulla Reddy Engineering College (Autonomous)
More informationModified Welch Power Spectral Density Computation with Fast Fourier Transform
Modified Welch Power Spectral Density Computation with Fast Fourier Transform Sreelekha S 1, Sabi S 2 1 Department of Electronics and Communication, Sree Budha College of Engineering, Kerala, India 2 Professor,
More informationISSN Vol.08,Issue.12, September-2016, Pages:
ISSN 2348 2370 Vol.08,Issue.12, September-2016, Pages:2273-2277 www.ijatir.org G. DIVYA JYOTHI REDDY 1, V. ROOPA REDDY 2 1 PG Scholar, Dept of ECE, TKR Engineering College, Hyderabad, TS, India, E-mail:
More informationUsing Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability
Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability Robert Wille Daniel Große Mathias Soeken Rolf Drechsler Institute of Computer Science University of Bremen,
More informationThe log-support encoding of CSP into SAT
The log-support encoding of CSP into SAT Marco Gavanelli 1 Dept. of Engineering, Ferrara University, WWW home page: http://www.ing.unife.it/docenti/marcogavanelli/ Abstract. Various encodings have been
More informationDecimation-in-Frequency (DIF) Radix-2 FFT *
OpenStax-CX module: m1018 1 Decimation-in-Frequency (DIF) Radix- FFT * Douglas L. Jones This work is produced by OpenStax-CX and licensed under the Creative Commons Attribution License 1.0 The radix- decimation-in-frequency
More informationFIR Filter Architecture for Fixed and Reconfigurable Applications
FIR Filter Architecture for Fixed and Reconfigurable Applications Nagajyothi 1,P.Sayannna 2 1 M.Tech student, Dept. of ECE, Sudheer reddy college of Engineering & technology (w), Telangana, India 2 Assosciate
More informationINTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY
INTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY A PATH FOR HORIZING YOUR INNOVATIVE WORK IMAGE COMPRESSION USING VLSI APPLICATION OF DISCRETE WAVELET TRANSFORM (DWT) AMIT
More informationA GENERATOR OF MEMORY-BASED, RUNTIME-RECONFIGURABLE 2 N 3 M 5 K FFT ENGINES. Angie Wang, Jonathan Bachrach, Borivoje Nikolić
A GENEATO OF MEMOY-BASED, UNTIME-ECONFIGUABLE 2 N 3 M 5 K FFT ENGINES Angie Wang, Jonathan Bachrach, Borivoje Nikolić University of California, Berkeley ABSTACT untime-reconfigurable, mixed-radix FFT/IFFT
More informationDESIGN OF DCT ARCHITECTURE USING ARAI ALGORITHMS
DESIGN OF DCT ARCHITECTURE USING ARAI ALGORITHMS Prerana Ajmire 1, A.B Thatere 2, Shubhangi Rathkanthivar 3 1,2,3 Y C College of Engineering, Nagpur, (India) ABSTRACT Nowadays the demand for applications
More informationDesign of 2-D DWT VLSI Architecture for Image Processing
Design of 2-D DWT VLSI Architecture for Image Processing Betsy Jose 1 1 ME VLSI Design student Sri Ramakrishna Engineering College, Coimbatore B. Sathish Kumar 2 2 Assistant Professor, ECE Sri Ramakrishna
More informationFused Floating Point Arithmetic Unit for Radix 2 FFT Implementation
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 6, Issue 2, Ver. I (Mar. -Apr. 2016), PP 58-65 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Fused Floating Point Arithmetic
More informationBatchu Jeevanarani and Thota Sreenivas Department of ECE, Sri Vasavi Engg College, Tadepalligudem, West Godavari (DT), Andhra Pradesh, India
Memory-Based Realization of FIR Digital Filter by Look-Up- Table Optimization Batchu Jeevanarani and Thota Sreenivas Department of ECE, Sri Vasavi Engg College, Tadepalligudem, West Godavari (DT), Andhra
More informationLow Power and Memory Efficient FFT Architecture Using Modified CORDIC Algorithm
Low Power and Memory Efficient FFT Architecture Using Modified CORDIC Algorithm 1 A.Malashri, 2 C.Paramasivam 1 PG Student, Department of Electronics and Communication K S Rangasamy College Of Technology,
More information