Large Scale Circuit Placement: Gap and Promise

Transcription

1 Large Scale Circuit Placement: Gap and Promise Jason Cong 1, Tim Kong 2, Joseph R. Shinnerl 1, Min Xie 1 and Xin Yuan 1 UCLA VLSI CAD LAB 1 Magma Design Automation 2

2 Outline Introduction Gap Analysis of Existing Placement Algorithms Scalable Paradigm Timing Optimization Routability Optimization Concluding Remarks Application Multi-Million Gate FPGA Placement

3 Outline Introduction Gap Analysis of Existing Placement Algorithms Scalable Paradigm Timing Optimization Routability Optimization Concluding Remarks Application Multi-Million Million Gate FPGA Placement

4 Why Still Placement Problem True, it has been studied over 30 years, but We need good solutions more then ever One of most important steps in IC implementation flow Directly defines interconnects Difficult Problem size grows 2X every months Moore s Law Cannot place hierarchically without quality degradation

5 Example of Logic Hierarchy in Final Layout By courtesy of IBM (Tony Drumm)

6 Why Still Placement True, it has been studied over 30 years, but We need good solutions more then ever One of most important steps in IC implementation flow Directly defines interconnects Difficult Problem size grows 2X every months Moore s Law Cannot place hierarchically without quality degradation We are not very good at it

7 Outline Introduction Gap Analysis of Existing Placement Algorithms Scalable Paradigm Timing Optimization Routability Optimization Concluding Remarks Application Multi-Million Million Gate FPGA Placement

8 Motivation Lack of significant progress in wirelength reduction Rate of reduction is about 5-10% every 2-3 years Latest developments in placement differ mainly in runtime Most work compare only with known heuristics Use real design based benchmarks Use synthetic benchmarks Little understanding about the divergence from the optimal

9 Placement Examples with Known Optimal Wirelength [Chang et al, 2003] Given a (real) netlist N Construct netlist N with known opt. WL and match the net distribution of N All the modules are of equal size, and there is no space between rows and adjacent modules For 2-pin nets, connect any two adjacent modules For each n-pin net, connect the n modules in a rectangular region close to a square, i.e., the length of each side is close to sqrt(n) The wirelength is of each n-pin net is given by n + n / n 2

10 Placement Examples with Known Upperbounds [Cong et al, 2003] Limitations of PEKO All the nets are local Wirelength contribution by global connections in real designs can be significant Extend PEKO by introducing non-local nets to mimic global connections Method 1: Generate a subset of i-pin nets by randomly connecting i modules on the chip Method 2: Generate a subset of i-pin nets according to wirelength distribution vector (WDV)

11 Illustration: PEKU Example Construction Input : t = 64, D = {d 2 =35,d 3 =21,d 4 =7,d 5 =4,d 6 =2, d 7 =1} a=0.2 W = {w 1 w 3 =0, w 4 =3, w 5 =3, w 6 = 0,w 7 =2,w 8 =2,w 9 =1, w 10 =0, w 11 =1, w 12 =1} Generate 28 2-pin optimally Generate 7 2-pin randomly Generate 16 3-pin optimally Generate 5 3-pin randomly Generate 6 4-pin optimally Generate 1 4-pin randomly Generate 4 5-pin optimally Generate 2 6-pin optimally Generate 1 7-pin optimally Total WL = 184

12 Studied Five State-of-the-Art Placers Capo [Caldwell et al, 2000] Based on multilevel partitioner Aims to enhance the routability Dragon [Wang et al, 2000] Uses hmetis for initial partition SA with bin-based swapping mpl [Chan et al, 2000] Nonlinear programming on the coarsest level Discrete relaxation at finer levels mpg [Chang et al, 2002] Uses FC clustering and hierarchical density control Incremental A-tree for routability Qplace [Cadence Inc.] Leading edge industrial placer Component of Silicon Ensemble

13 Experimental Results on PEKO Quality Ratio #cells Runtime(s) #cells Capo 8.6 Dragon 2.20 mpg 1.0 mpl 3.0 Qplace 5.1 Capo 8.6 Dragon 2.20 mpg 1.0 mpl 3.0 Qplace 5.1 Existing Algorithms can be 59% to 140% away from the optimal on PEKO On Examples with pads mpg and Qplace show improvement of 12% and 10% repectively Dragon, mpl, and Capo do not benefit much from the additional information There is significant room for improvement in placement algorithms

14 Experimental Results on PEKO Quality Ratio #cells Runtime(s) #cells Capo 8.6 Dragon 2.20 mpg 1.0 mpl 3.0 QPLace 5.1 Capo 8.6 Dragon 2.20 mpg 1.0 mpl 3.0 Qplace 5.1 Capo, QPlace and mpl scales well in runtime Average solution quality of each tool shows deterioration by an additional 9% to 17% when the problem size increases by a factor of 10

15 Experimental Results on PEKU Quality Ratio % of non-local nets Dragon 2.20 Capo 8.6 mpg 1.0 mpl 3.0 Qplace 5.1 The effectiveness of existing placers can vary significantly for circuits of similar size but different characteristics Comparing QRs helps to identify the technique that works best under each scenario QR (Placed Wirelength vs Upperbound) may not be tight

16 High Interest in the Community

17 Timing-driven Placement Examples with Known Optimal (TPEKO) Original longest path Artificial path Obtain a placement for the circuit from any available tool Perform timing analysis on the circuit Create an artificial combinational path with equal or larger delay than the longest path Guarantee the cells in the path are adjacent to each other Make necessary modifications

18 Quality Ratio Evaluating Timing-Driven Placement Algorithms Using TPEKO #longest path VPR PATH Evaluating two stateof-the-art FPGA placement algorithms VPR [Marquardt et al. 2000] PATH [Kong 2002] Can be far away from the optimal for difficult examples 35% on average 54% in the worst case

19 Observations from Gap Analysis Significant opportunity in placement Existing algorithms may produce solutions far away from the optimal The quality result of the same placer varies for circuits of similar size but different characteristic Scalability problem in runtime and solution quality Significant ROI Benefit equal to one to two generations of process scaling But without requiring multi-billion dollar investment (hopefully!)

20 Outline Introduction Gap Analysis of Existing Placement Algorithms Scalable Paradigm Timing Optimization Routability Optimization Concluding Remarks Application Multi-Million Million Gate FPGA Placement

21 Scalable Paradigms for Placement Assertion: some form of hierarchy is essential Three main paradigms: 1) Top-down Generalized recursive partitioning defines the hierarchy 2) Bottom-up (multilevel) 3) Flat Caveats Generalized recursive clustering defines the hierarchy Flat on the outside, but hierarchical internally Scalable may be slower than O(N), due to Moore s law Focus on global placement; assume scalability of legalization and detailed placement

22 Paradigm 1: Top-Down Placement Hierarchy Construction Cutsize-Minimizing Partitioning E.g., Capo, Feng-Shui, Dragon. Partitioning guided by wirelength-driven placements Start with a loosely constrained WL-driven solution; a quadratic objective function approximates weighted wirelength E.g., Gordian-L, BonnPlace Hierarchy Refinement The order in which subregions are partitioned matters especially under terminal propagation Can cells migrate across partition boundaries?

23 Cutsize-Driven Partitioning-Based Placement Cutsize = the number of nets not contained in just one side of the partition Rent s rule shows that wirelength and cutsize correlate to within about X2 log N [Wang et al, 2000]. Fast FM-style iterations with terminal propagation Careful cutline selection and multiway partitions can help e.g. Capo, Feng-Shui, Dragon

24 Cutsize-Driven Recursive Top-Down Partitioning After Initially, three two there stages, is only each netlist cell cell has has connectivity; been assigned no to spatial to one one of of four eight possible information subregions. is available. As few nets as possible have been cut. Apply Iterative a standard improvement partitioning by repartitioning algorithm to with the given terminal netlist. Multilevel partitioning propagation algorithms is essential. are the most effective.

25 Partitioning Guided by Approximate Placements Minimize a quadratic approximation to global wirelength Solve one large symmetric positive-definite linear system Pads prevent cells from collapsing to a single point Use the given placement to recursively partition cells Gordian-L: Minimize cutsize, but use the given placement to form initial partitions (e.g., using x- or y-coordinate median for cutline) New subregions generate new center-of mass constraints for subsequent iterations BonnPlace: To assign cells to subregions, minimize displacement from the given locations, not cutsize.

26 Example: Gordian-L-style Placement

27 Hierarchy Adjustments in Top-Down Placement by Iterative Refinement K-way partitioning followed by localized repartitioning with terminal propagation (Feng-Shui). Initial cutsize-driven quadrisection followed by bin swapping, each bin being a block of the partition, with wirelength-based annealing only at the finest level (Dragon). Unconstrained quadratic wirelength minimization over 2x2 windows of overlapping subregions, followed by repartioning inside each window (BonnPlace).

28 Paradigm 2: Multilevel Placement Coarsening: build the hierarchy by recursive aggregation (generalized clustering) Relaxation: improve the placement at each level by localized optimization Interpolation: transfer coarse-level solution to adjacent, finer level (generalized declustering) Multilevel Flow: multiple traversals over multiple hierarchies (V-cycle variations)

29 Multi-Level Optimization Framework Given problem Problem size decreases Coarsening (Clustering) Interpolation & Relaxation (optimization) Multilevel coarsening generates smaller problem sizes at coarser levels faster optimization at coarser levels May explore different aspects of the solution space at different levels Gradual refinement on good solutions from coarser levels is very efficient Successful in many applications Originally developed for PDEs Recent success in VLSI CAD: partitioning, placement, routing

30 Coarsening by clustering Multilevel Coarse Placement A bin grid structure at each level Hierarchical area density control Optimization by SA, QP, RDFL, etc. Initial Placement Refinement by placement

31 Multilevel Methods: Coarsening by Recursive Aggregation Recursive aggregation defines the hierarchy. Different aggregation algorithms can be used on different levels and/or in different V-cycles. Clustering methods First-Choice Clustering (hmetis [Karypis 1999]). AMG based aggregation An aggregate need not be a cluster. A cell can be fractionally associated to more than one aggregate Merge each vertex with its best neighbor Merged Nets

32 Multilevel Methods: Relaxation (Intralevel Optimization) Iterative improvement at each level by fast, localized computation Discrete permutation enumerations; swapping Unconstrained quadratic wirelength minimization on subsets Network-flow based improvement on subsets (RDFL) Local relaxation is sufficient. Global improvement comes from the multilevel hierarchy. Relaxations at finer levels may be quite different, e.g., more discrete, than relaxations at coarser levels.

33 Relaxation on Local Subsets Movable Cell Unrelated Cell Fixed Neighbor Original Subnetlist with Subproblem Move the red cells to their optimal positions, holding all other cells fixed and (perhaps) ignoring overlap

34 Example: Goto-based Discrete Relaxation Each cell s optimal location is readily calculated when all other cells are held fixed. Compute a chain A, B, C, D, E, where B is a randomly selected neighbor of A s optimal location, etc. Examine all permutations of the chain and take the best one. Problem: the chain is not closed (A is not necessarily near any other cell s optimal location).

35 Example: Quadratic Relaxation on Noncontiguous Subsets (QRS) Select a subset M of cells to move Identify other cells and pads, F, connected to M by nets in E M = { e E e M φ }. Decouple the horizontal and vertical problems. M is obtained as segments of length k along a DFS vertex traversal of the netlist

36 Solving the QRS subproblem Problem formulation (horizontal case): 2 ( x( v) x ) min e ( k ) ( k ) x ( v) x e E where M x v e e = 1 e v e x( v), small number. Iteratively solve the weighted quadratic minimization problem, using the current solution to determine the weight (as in Gordian-L) May result in cell overlap! e ε + ε is

37 Ripple-move legalization [Hur and Lillis, 2000] Because many forms of subset relaxation ignore overlap, postrelaxation cell swaps may be needed to remove overlap. Define a DAG on neighboring bins. Edge cost reflects the best wirelength gain over all cell swaps between two bins. Calculate a max-gain monotone path on the bin-grid graph

38 Multilevel Methods: Interpolation (Generalized Declustering) Goal: transfer a partial solution from a coarser level to its adjacent finer level Simplest approach: place all components of a cluster at its center Better approach: place each component of an aggregate at the weighted average of the aggregates to which it is strongly connected. Optionally: impose constraints; e.g., the average location of the components can be held fixed.

39 Interpolation (Declustering) Initial Coarsest Level Placement Declustering Placement Declustering Placement Final placement solution Use the same grid structure at each level Variable cluster size (may be bigger than a bin): handled by hierarchical area density control Multilevel SA engine: SA engine starts with a low temperature at each level except the coarsest level

40 AMG-style Linear Interpolation The inherited position of a cluster component ( ) can be determined by several cluster positions, not just its own. Place the C-Pt representatives Place the F-pts by weighted interpolation

41 Next finer level cells AMG-based Linear Interpolation [A. Brandt 1986] cluster constant AMG interpolation C-point Within each cluster, select the one with maximum degree as C-point; others are considered as F-points v i = Σ a v + Σ ij j C points v F points j v j a ij v j

42 Iterated Multilevel Flow Make use of placement solution from 1 st V-cycle First Choice (FC) clustering Geometric based FC clustering

43 Iterated Multilevel Flow Iterated V-Cycles F-Cycle Backtracking V-Cycle

44 Sample Impact of the Multilevel Components to mpl s overall quality First-Choice Clustering: QRS Relaxation: AMG Interpolation: Iterated V-cycles: 3 4% reduced WL 5 6% reduced WL 2 3% reduced WL 2 8% reduced WL

45 Extension: Multilevel Mixed-size Placement Level 0 Simultaneous place big and small objects Gradually fix the locations of big objects and generate overlap-free placement for big objects during multilevel placement Big objects legalization Level k Coarsest level placement small object big object fixed big object cluster

46 Example: Final Placement of ibm02 by mpg-ms

47 Paradigm 3: Embedded Multilevel Optimization Maintain a flat, nonhierarchical view of the placement problem No explicit aggregation or partitioning Use advanced hierarchical computation algorithms to perform internal iterations Example: AMG-accelerated force-directed methods Minimize weighted unconstrained quadratic wirelength Incorporate area-distribution gradients iteratively in the quadratic optimality condition (Kraftwerk) Employ algebraic multigrid (AMG) to solve the large linear systems for the optimality conditions at each step.

48 Outline Introduction Gap Analysis of Existing Placement Algorithms Scalable Paradigm Timing Optimization Routability Optimization Concluding Remarks Application Multi-Million Million Gate FPGA Placement

49 Timing Optimization Additional goal: to minimize longest-path delay or maximize the minimum slack. Difficulties: Exponential number of paths. Complex timing constraints multi-clock domain, multi-cycle, etc. Existing Algorithms Path-based algorithms Net-based algorithms

50 Path-based Algorithms Directly minimize the longest path delay. Popular approaches: Explicitly reduce the maximum length of a set of paths; the set could be pre-computed or dynamically adjusted. [Burstein & Youssef, 1985, Swartz & Sechen, 1995] 1 2 a b c 3 4 e d 5 6 D(i): edge delay (cell delay included) MAX { D(a)+D(c)+D(d) D(b)+D(c)+D(d) D(a)+D(c)+D(e) D(b)+D(c)+D(e)

51 Mathematical Programming based Approaches Popular approaches (cont d): Mathematical programming by introducing auxiliary variables (arrival time) [Jackson & Kuh, 1989, Srinivasan et al, 1991, Hamada et al, 1993, ] A(i): arrival time at i 1 2 a b c 3 4 e d 5 6 A(1)+D(a) A(3) : edge(a) A(2)+D(b) A(3) : edge(b) A(5) T(5) : endpoint 5 A(6) T(6) : endpoint 6

52 Pros and Cons Advantage(s): Accurate timing view during optimization. Disadvantage(s): High computational cost. Difficult to fit in certain placement frameworks.

53 Net-based Algorithms Timing constraints are translated into net weights (net-weighting) or length constraints (delay-budgeting). Delay budgeting: distribute slacks to all edges in the circuit to achieve zero-slack [Hauge et al, 1987, Gao et al, 1991, Luk 1991, Youssef et al, 1992, Tellez et al, 1996, ] 1 2 a b c 3 4 e d 5 6 D(a) t 1 D(b) t 2 D(c) t 3 D(d) t 4 D(e) t 5

54 Timing-Driven Placement with Delay Budgeting Construct a placement to meet all budgets. If all budgets are met, timing is GUARANTEED! Difficulty: Too many possible budgeting solutions and do not know which can be satisfied a priori. Budgeting is often done in structural domain without physical feasibility consideration Unify placement and delay budgeting? [Sarrafzadeh et al, 1997; Halpinet al, 2001; Yang et al, 2002]

55 Net Weighting Timing criticalities are translated into net weights (soft constraints); then compute a placement which minimizes total weighted delay (or WL). 1 a c d 5 2 b 3 4 e 6 Cost = w(a)*d(a) + w(b)*d(b) + w *D(c) + w(d)*d(d) + w(e)*d(e)

56 Net Weighting Principles P1: smaller slack higher weight. For example: w(e)=(1-slack(e)/t) a VPR [Marquardt et al, 2000] a:7/0 d:5/0 c:1/0 b:5/2 e:3/2 Edge label: delay/slack a=3.0 w(a) = 1.0 w(b) = w(c) = 1.0 w(d) = 1.0 w(e) =

57 Net Weighting Principles P2: more paths higher weight. For example: path-counting [Senn et al, 2002] a:7/0 b:5/2 c:1/0 d:5/0 e:3/2 w(a) = 2.0 w(b) = 2.0 w(c) = 4.0 w(d) = 2.0 w(e) = 2.0

58 Ideal Net Weighting Need to consider both principles together Ideally, we want a:7/0 c:1/0 d:5/0 w(c) > w(a)=w(d) > w(b)=w(e) b:5/2 e:3/2

59 All Path Net Weighting Problem Challenge: can we compute the impact of all paths through an edge, properly scaled by their slacks? i.e., for each edge e, compute w(e) = S " p e f(slack(p)) a:7/0 b:5/2 c:1/0 d:5/0 e:3/2 w(a)= f(slack(a-c-d)) + f(slack(a-c-e)) w(c)= f(slack(a-c-d)) + f(slack(b-c-d)) + f(slack(a-c-e)) + f(slack(b-c-e))

60 All Path Counting For certain function f, PATH algorithm ([Kong 2002]) can compute exact weights of all edges in linear time: w(e) = S " p e f(slack(p)) For example: a:7/0 d:5/0 c:1/0 b:5/2 e:3/2 f(x) = 10 -x/13 w(a) = w(b) = w(c) = w(d) = w(e) = w(c) > w(a)=w(d) > w(b)=w(e)

61 Results IT WORKS! Incorporated into state-of-the-art FPGA placer VPR. Original weighting: w(e)=(1-slack(e)/t) a 15.6% delay reduction. No runtime overhead. 4.1% wirelength increase.

62 Outline Introduction Gap Analysis of Existing Placement Algorithms Scalable Paradigm Timing Optimization Routability Optimization Concluding Remarks Application Multi-Million Million Gate FPGA Placement

63 Routability Optimization Aggressive WL minimization!= routability Routability-driven placement Routability modeling Solution techniques for routability control

64 Routability Modeling Supply Demand X Y global routing grid in chip core region Model routing supply and demand for each bin and boundary on the grid structure

65 Categories of Routability Modelinig Topology-free modeling No routing topology generated Fast Topology-based modeling Steiner tree topology generation Provide upper bound for routability estimation High complexity

66 Topology-free Modeling Bounding-box (BBOX)-based modeling [Cheng 1994] Probabilistic analysis-based modeling [Lou et al, 2001] Rent s rule-based modeling [Yang et al, 2002] Pin density-based modeling [Hu & Marek- Sadowska 2002, Brenner & Rohe, 2003]

67 Topology-free Modeling Stochastic Analysis [Lou et al, 2001] s t 6 Probability of a 2-pin net crossing bin(i,j) in a mxn bin grid P(i,j) = C(i, j)/f(m,n) C(i,j): #routes crossing bin(i,j) F(m,n): #routes from bin(1,1) to bin(m,n) Decompose multi-pin nets into 2-pin nets

68 Topology-free Modeling Pin Density Based [Hu & Marek-Sadowska 2002,Brenner & Rohe, 2003] Calculated weighted wirelength F = (1+1+1)/3*4=4 Let P(b) linear with respect to #pin P ( b) BB s b i CF = wi i Di D i : degree of net i BB i : bounding box of net i P s (b) : heuristic function capturing pin density in bin b Can be combine with probabilistic analysis-based modeling i

69 Topology-based Modeling Precomputed Steiner tree topology for wiring demand estimation [Mayrhofer & Lauther, 1990] Congestion-avoidance two-bend routing for 2-pin nets [Chang et al, 2003] IncAtree with incremental updates support for multi-pin nets [Chang et al, 2003]

70 Topology-based Modeling Fast LZ-routing for Two-pin Nets [Chang et al, 2003] HVH Left region VHV Right region Decide HVH or VHV: Select the less congested layer Binary search on V-stem (or H-stem) Initial left region and right region to cover bounding box Repeat Query wire usage on both regions Select region with less congestion Wire usage query can be done in O(log grid_size)

71 Topology-based Modeling Fast Incremental A-tree Routing [Chang et al, 2003] Simple incremental A-tree Recursively Quad-partition grids Each pin recursively connects to lower left corner of each level of partition For net with bounding box length B, at most 2 *log B edge updates for each pin move, except the root. Each edge routed by LZ-router Root(source pin) First Quadrant

72 Optimization Techniques for Routability Net weighting Transfer congestion picture into bin weights and optimization weighted WL Used in iterative placement, such as SA-based placer [Hu & Marek-Sadowska, 2002, Chang et al, 2003] Cell weighting (a.k.a cell inflation) Weight cell size based on the congestion picture Use partitioner or implicit/explicit bin density control to move inflated cell out of congested region Used in constructive placement and iterative placement[parakh 1998, Brenner & Rohe, 2003, Yang et al, 2003]

73 Outline Introduction Gap Analysis of Existing Placement Algorithms Scalable Paradigm Timing Optimization Routability Optimization Concluding Remarks Application Multi-Million Million Gate FPGA Placement

74 Concluding Remarks There is significant opportunity to improve the placement technologies Three scalable paradigms 1) Top-down Generalized recursive partitioning defines the hierarchy 2) Bottom-up (multilevel) Generalized recursive clustering defines the hierarchy 3) Flat Flat on the outside, but hierarchical internally Timing and routability optimization can be achieved through weighted wirelength optimization

75 Outline Introduction Gap Analysis of Existing Placement Algorithms Scalable Paradigm Timing Optimization Routability Optimization Concluding Remarks Application Multi-Million Gate FPGA Placement