ECE 5745 Complex Digital ASIC Design Topic 13: Physical Design Automation Algorithms

Transcription

1 ECE 7 Complex Digital ASIC Design Topic : Physical Design Automation Algorithms Christopher atten School of Electrical and Computer Engineering Cornell University

2 Placement Global Routing Detailed Routing Part : CAD Algorithms Placement x = a'bc + a'bc' y = b'c' + ab' + ac x = a'b y = b'c' + ac RTL to Logic Synthesis Technology Independent Synthesis Technology Dependent Synthesis Global Routing Detailed Routing ECE 7 T: Physical Design Automation Algorithms /

3 Placement Global Routing Detailed Routing Placement KLMH a b d e c f g h Linear Placement a c b g h d f e VDD h e d a h e d a g f c b g f c b GND D Placement Placement and Routing with Standard Cells Adapted from [Khang ] VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter : Global and Detailed Placement ECE 7 T: Physical Design Automation Algorithms / Lienig

4 Placement Global Routing Detailed Routing Global vs. Detailed Placement Global Placement Detailed Placement Adapted from [Khang ] ECE 7 T: Physical Design Automation Algorithms /

5 Placement Global Routing Detailed Routing Placement Objective Functions Total Wirelength Number of Cut Nets Wire Congestion Signal Delay. Optimization Objectives Total Wirelength KLMH e h a k j f h c f l i VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter : Global and Detailed Placement 6 b j g d k i d c e l b a g 0 Springer Verlag Lienig Adapted from [Khang ] ECE 7 T: Physical Design Automation Algorithms / pringer Verlag

6 Placement Global Routing Detailed Routing Results of Placement Good vs. ad Placement ad placement causes routing congestion resulting in: Increases in circuit area (cost) and wiring Longer wires more capacitance Longer delay Higher dynamic power dissipation Good placement Circuit area (cost) and wiring decreases Shorter wires less capacitance Shorter delay Less dynamic power dissipation Kurt Keutzer Adapted from [Devadas 06] ECE 7 T: Physical Design Automation Algorithms 6 /

7 Placement Global Routing Detailed Routing. Introduction Partitioning KLMH Circuit: 6 Cut c b 7 8 Cut c a lock A lock lock A lock Cut c a : four external connections Cut c b : two external connections Adapted from [Khang ] ECE 7 T: Physical Design Automation Algorithms 7 / VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter : Netlist and System Partitioning Lienig

8 . Terminology Placement Global Routing Detailed Routing Partitioning Terminology lock (Partition) Graph G : Nodes,,. 6 6 Cells Graph G : Nodes,, 6. Collection of cut edges Cut set: (,), (,), (,6), Adapted from [Khang ] ECE 7 T: Physical Design Automation Algorithms 8 / VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter : Netlist and System Partitioning

9 .. Kernighan-Lin (KL) Algorithm Placement Global Routing Detailed Routing Kernighan-Lin (KL) Algorithm Given: A graph with n nodes where each node has the same weight. Goal: A partition (division) of the graph into two disjoint subsets A and with minimum cut cost and A = = n. Example: n = lock A 6 lock 7 8 Adapted from [Khang ] ECE 7 T: Physical Design Automation Algorithms 9 /

10 .. Kernighan-Lin (KL) Algorithm Terminology Placement Global Routing Detailed Routing Kernighan-Lin (KL) Algorithm Concepts KLMH Cost D(v) of moving a node v D(v) = E c (v) E nc (v), 6 where E c (v) is the set of v s incident edges that are cut by the cut line, and E nc (v) is the set of v s incident edges that are not cut by the cut line. Node : D() = -= 7 8 High costs (D > 0) indicate that the node should move, while low costs (D < 0) indicate that the node should stay within the same partition. Node 7: D(7) = -= Adapted from [Khang ] ECE 7 T: Physical Design Automation Algorithms 0 / VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter : Netlist and System Partitioning 0

11 .. Kernighan-Lin (KL) Algorithm Terminology Placement Global Routing Detailed Routing Kernighan-Lin (KL) Algorithm Concepts KLMH Gain of swapping a pair of nodes a und b g = D(a) + D(b) -* c(a,b), 6 where D(a), D(b) are the respective costs of nodes a, b c(a,b) is the connection weight between a and b: If an edge exists between a and b, then c(a,b) = edge weight (here ), otherwise, c(a,b) = The gain g indicates how useful the swap between two nodes will be The larger g, the more the total cut cost will be reduced Adapted from [Khang ] ECE 7 T: Physical Design Automation Algorithms / VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter : Netlist and System Partitioning

12 Placement Global Routing Detailed Routing Kernighan-Lin (KL) Algorithm Concepts.. Kernighan-Lin (KL) Algorithm Terminology KLMH Gain of swapping a pair of nodes a und b Node 7: D(7) = -= g = D(a) + D(b) -* c(a,b), 6 where D(a), D(b) are the respective costs of nodes a, b c(a,b) is the connection weight between a and b: If an edge exists between a and b, then c(a,b) = edge weight (here ), otherwise, c(a,b) = 0. Node : D() = -= 7 8 g (,7) = D() + D(7) - * c(a,b) = + = 6 => Swapping nodes and 7 would reduce the cut size by 7 8 Adapted from [Khang ] VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter : Netlist and System Partitioning ECE 7 T: Physical Design Automation Algorithms / Lienig

13 Placement Global Routing Detailed Routing Kernighan-Lin (KL) Algorithm Concepts.. Kernighan-Lin (KL) Algorithm Terminology KLMH Gain of swapping a pair of nodes a und b Node : D() = -= g = D(a) + D(b) -* c(a,b), 6 where D(a), D(b) are the respective costs of nodes a, b c(a,b) is the connection weight between a and b: If an edge exists between a and b, then c(a,b) = edge weight (here ), otherwise, c(a,b) = 0. Node : D() = -= 7 8 g (,) = D() + D() - * c(a,b) = + 0 = 6 => Swapping nodes and would reduce the cut size by 7 8 Adapted from [Khang ] VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter : Netlist and System Partitioning ECE 7 T: Physical Design Automation Algorithms / Lienig

14 Placement Global Routing Detailed Routing Kernighan-Lin (KL) Algorithm Example.. Kernighan-Lin (KL) Algorithm Example KLMH Cut cost: 9 Not fixed:,,,,,6,7,8 Cut cost: 6 Not fixed:,,,6,7,8 Cut cost: Not fixed:,,7,8 Cut cost: 7 Not fixed:,8 Cut cost: 9 Not fixed: D() = D() = D() = D(6) = D() = D(7) = D() = D(8) = D() = - D(6) = D() = - D(7)=- D() = D(8)=- D() = - D() = - D(7)=- D(8)=- D() = - D(8)=- g = +-0 = Swap (,) G = g = g = +-0 = Swap (,6) G = G + g =8 g = ---0 = -6 Swap (,7) G = G + g = g = ---0 = - Swap (,8) G = G + g = 0 Adapted from [Khang ] VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter : Netlist and System Partitioning ECE 7 T: Physical Design Automation Algorithms / Lienig

15 Placement Global Routing Detailed Routing Kernighan-Lin (KL) Algorithm Example.. Kernighan-Lin (KL) Algorithm Example KLMH D() = D() = D() = D(6) = D() = D(7) = D() = D(8) = D() = - D(6) = D() = - D(7)=- D() = D(8)=- D() = - D() = - D(7)=- D(8)=- D() = - D(8)=- g = +-0 = Swap (,) G = g = g = +-0 = Swap (,6) G = G + g =8 g = ---0 = -6 Swap (,7) G = G + g = g = ---0 = - Swap (,8) G = G + g = 0 Maximum positive gain G m = 8 with m =. Since G m > 0, the first m = swaps (,) and (,6) are executed. 6 Since G m > 0, more passes are needed until G m VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter : Netlist and System Partitioning 7 Adapted from [Khang ] ECE 7 T: Physical Design Automation Algorithms / Lienig

16 Placement Global Routing Detailed Routing Min-Cut Placement Use partitioning algorithm (such as KL) to divide netlist into two regions Use partitioning algorithm to recursively divide the two partitions into two smaller regions (four regions total) Each cut heuristically minimizes the number of cut nets Adapted from [Khang ] ECE 7 T: Physical Design Automation Algorithms /

17 .. Min-Cut Placement Example Placement Global Routing Detailed Routing Min-Cut Example Given: 6 Task: x placement with minimum wirelength using alternative cutline directions and the KL algorithm Adapted from [Khang ] ECE 7 T: Physical Design Automation Algorithms 6 / VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter : Global and Detailed Placem

18 Placement Global Routing Detailed Routing Min-Cut Example..cut Min-Cut-Platzierung: eispiel 6 KLMH Vertical cut cut : L={,,}, R={,,6} KL Algorithms cut cut Adapted from [Khang ] ECE 7 T: Physical Design Automation Algorithms 7 /

19 Placement Global Routing Detailed Routing Min-Cut Example 6 KLMH 0 0 Horizontal cut cut L : T={,}, ={,0} cut Horizontal cut cut R : T={,}, ={6,0} 0 cut L 0 6 cut R cut TL cut TR cut L cut R 6 VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter : Global and Detailed Placement 6 Adapted from [Khang ] ECE 7 T: Physical Design Automation Algorithms 8 / Lienig

20 Placement Global Routing Detailed Routing Analytical Placement with Quadratic Placement Algorithm.. Analytic Placement Quadratic Placement KLMH Objective function is quadratic; sum of (weighted) squared Euclidean distance represents placement objective function L( P) = n i, j= c ij ( ) ( ) ) x x + y y i j i where n is the total number of cells, and c(i,j) is the connection cost between cells i and j. j Only two-point-connections Minimize objective function by equating its derivative to zero which reduces to solving a system of linear equations Adapted from [Khang ] ECE 7 T: Physical Design Automation Algorithms 9 /

21 Placement Global Routing Detailed Routing Minimizing Objective Function Clumps Cells Together yout after Min-cut Adapted from [Devadas 06] Now global placement problem will be solved again ECE 7 T: Physical Design Automation Algorithms 0 /

22 First Iteration Placement Global Routing Detailed Routing Using Partitioning to Pull Cells Apart Second Iteration Third Iteration Kurt Keutzer A. Kahng 0 Kurt Keutzer Fourth Iteration A. Kahng Kurt Keutzer A. Kahng Kurt Keutzer A. Kahng Adapted from [Devadas 06,Kahng ] ECE 7 T: Physical Design Automation Algorithms /

23 Placement Global Routing Detailed Routing Part : CAD Algorithms Placement x = a'bc + a'bc' y = b'c' + ab' + ac x = a'b y = b'c' + ac RTL to Logic Synthesis Technology Independent Synthesis Technology Dependent Synthesis Global Routing Detailed Routing ECE 7 T: Physical Design Automation Algorithms /

24 .Placement Introduction: GlobalGeneral Routing Routing Detailed Problem Routing General Routing Problem Netlist: N = {C, D 6, } N = {D,, C, A } N = {C, D } N = {, A, C } A N N N N C Technology Information (Design Rules) D 6 Adapted from [Kahng ] ECE 7 T: Physical Design Automation Algorithms /

25 Placement Global Routing Detailed Routing. Introduction Routing Algorithm Taxonomy KLMH Routing Multi-Stage Routing of Signal Nets Global Routing Detailed Routing Timing-Driven Routing Large Single- Net Routing Geometric Techniques Coarse-grain assignment of routes to routing regions Fine-grain assignment of routes to routing tracks Net topology optimization and resource allocation to critical nets Power (VDD) and Ground (GND) routing Non-Manhattan and clock routing VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter : Global Routing 9 Adapted from [Kahng ] ECE 7 T: Physical Design Automation Algorithms / Lienig

26 Placement Global Routing Detailed Routing. Introduction Global vs. Detailed Routing KLMH Global Routing Detailed Routing N N N N N N N N N N N N N N N N Horizontal Segment Vertical Segment Via 0 Springer Verlag VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter : Global Routing Adapted from [Kahng ] ECE 7 T: Physical Design Automation Algorithms / Lienig

27 . Terminology and Definitions Placement Global Routing Detailed Routing Terminology: Channel Channel Rectangular routing region with pins on two opposite sides Standard cell layout (Two-layer routing) Adapted from [Kahng ] ECE 7 T: Physical Design Automation Algorithms 6 /

28 . Terminology and Definitions Placement Global Routing Detailed Routing Terminology: Channel Channel Rectangular routing region with pins on two opposite sides Routing channel Routing channel Standard cell layout (Two-layer routing) Adapted from [Kahng ] ECE 7 T: Physical Design Automation Algorithms 7 /

29 . Terminology and Definitions Placement Global Routing Detailed Routing Terminology: Capacity Capacity Number of available routing tracks or columns Horizontal Routing Channel C D C d pitch A C A C D Adapted from [Kahng ] ECE 7 T: Physical Design Automation Algorithms 8 /

30 . Terminology and Definitions Placement Global Routing Detailed Routing Terminology: Switchbox KLMH Switchbox (Two-layer macro cell layout) Intersection of horizontal and vertical channels Vertical Channel C Horizontal Channel A Horizontal Channel C A Horizontal channel is routed after vertical channel is routed Vertical Channel Adapted from [Kahng ] VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter : Global Routing 8 ECE 7 T: Physical Design Automation Algorithms 9 / Lienig

31 . Optimization Goals Placement Global Routing Detailed Routing Terminology: Feed-Through Cells KLMH Standard-cell design If number of metal layers is limited, feedthrough cells must be used to route across multiple cell rows A Feedthrough cells A Variable-die, standard cell design: A A A Total height = Cell row heights + All channel heights 0 Springer Verlag VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter : Global Routing Adapted from [Kahng ] 6 Lienig ECE 7 T: Physical Design Automation Algorithms 0 /

32 . Optimization Goals Placement Global Routing Detailed Routing Optimizing Wirelength vs. Number of Feedthroughs KLMH Standard-cell design Steiner tree solution with minimal wirelength Steiner tree solution with fewest feedthrough cells 0 Springer Verlag Adapted from [Kahng ] ECE 7VLSI Physical Design: From Graph Partitioning T: to Physical Timing Closure Design Automation Algorithms Chapter : Global Routing / 7 Lienig

33 Placement Global Routing Detailed Routing KLMH Rectilinear Routing Definining routing regions Pin connections Pins assigned to grid cells 0 Springer Verlag VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter : Global Routing Adapted from [Kahng ] ECE 7 T: Physical Design Automation Algorithms /

34 Placement Global Routing Detailed Routing Rectilinear Routing A A A A A A A A A A A Pins assigned to grid cells Rectilinear Steiner minimum tree (RSMT) Assigned routing regions and feedthrough cells Sequential Steiner Tree Heuristic VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter : Global Routing Adapted from [Kahng ] ECE 7 T: Physical Design Automation Algorithms /

35 .6. Rectilinear Routing Placement Global Routing Detailed Routing Heuristic Sequential Steiner Tree Algorithm A Sequential Steiner Tree Heuristic. Find the closest (in terms of rectilinear distance) pin pair, construct their minimum bounding box (M). Find the closest point pair (p M,p C ) between any point p M on the M and p C from the set of pins to consider. Construct the M of p M and p C. Add the L-shape that p M lies on to T (deleting the other L-shape). If p M is a pin, then add any L-shape of the M to T.. Goto step until the set of pins to consider is empty VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter : Global Routing Adapted from [Kahng ] ECE 7 T: Physical Design Automation Algorithms /

36 .6. Rectilinear Routing: Example Sequential Steiner Tree Heuristic Placement Global Routing Detailed Routing Heuristic Sequential Steiner Tree Example VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter : Global Adapted Routing from [Kahng ] ECE 7 T: Physical Design Automation Algorithms /

37 .6. Placement Rectilinear Routing: Global Routing Example Sequential Detailed Steiner Routing Tree Heuristic Heuristic Sequential Steiner Tree Example Adapted from [Kahng ] VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter : Global Routing ECE 7 T: Physical Design Automation Algorithms /

38 Placement Global Routing Detailed Routing Part : CAD Algorithms Placement x = a'bc + a'bc' y = b'c' + ab' + ac x = a'b y = b'c' + ac RTL to Logic Synthesis Technology Independent Synthesis Technology Dependent Synthesis Global Routing Detailed Routing ECE 7 T: Physical Design Automation Algorithms 6 /

39 Placement Global Routing Detailed Routing 6. Terminology Detailed Routing Channel and Switchbox Routing E E KLMH C D C D E D A C A C Adapted from [Khang ] VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 6: Detailed Routing 8 ECE 7 T: Physical Design Automation Algorithms 7 / Lienig

40 Placement Global Routing Detailed Routing 6.. Horizontal Constraint Graphs Horizontal Constraint Graphs KLMH Column a b c d e f g h i j k 0 D E F G 0 D 0 0 A C E C E A F H 0 H G S(b) = {A,, C} Let S(col) denote the set of nets that pass through column col S(col) contains all nets that either () are connected to a pin in column col or () have pin connections to both the left and right of col Since horizontal segments cannot overlap, each net in S(col) must be assigned to a different track in column col S(col) represents the lower bound on the number of tracks in colum col; lower bound of the channel height is given by maximum cardinality of any S(col) VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 6: Detailed Routing Adapted from [Khang ] 6 ECE 7 T: Physical Design Automation Algorithms 8 / Lienig

41 Placement Global Routing Detailed Routing 6.. Horizontal Constraint Graphs Horizontal Constraint Graph Example KLMH Column a b c d e f g h i j k 0 D E F G 0 D 0 0 A C E C E A F H 0 H G Focus on columns which are not subsets of any other column S(a) S(b) S(c) S(d)S(e) S(f)S(g) S(h) S(i) S(j) S(k) A 0 D E F G 0 D 0 0 C E D A C E C E A F H 0 H G F G VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 6: Detailed Routing 9 Adapted from [Khang ] H S(a) = {A} S(b) = {A,,C} S(c) = {A,,C,D,E} S(d) = {A,,C,D,E} S(e) = {A,,D,E} S(f) = {A,D,F} S(g) = {D,F},G} S(h) = {D,G,H} S(i) = {D,G,H} S(j) = {G,H} S(k) = {G} ECE 7 T: Physical Design Automation Algorithms 9 / Lienig

42 Placement Global Routing Detailed Routing 6.. Horizontal Constraint Graphs Horizontal Constraint Graph Example KLMH Column a b c d e f g h i j k 0 D E F G 0 D 0 0 A C E C E A F H 0 H G A S(c) S(f)S(g) S(i) 0 D E F G 0 D 0 0 C E D F G H S(c) S(f) S(g) S(i) A G F H C D E A C E C E A F H 0 H G Adapted from [Khang ] VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 6: Detailed Routing 0 ECE 7 T: Physical Design Automation Algorithms 0 / Lienig

43 6.. Vertical Constraint Graphs Placement Global Routing Detailed Routing Vertical Constraint Graphs 0 D E F G 0 D 0 0 A C E C E A F H 0 H G D G E F C A H Adapted from [Khang ] ECE 7 T: Physical Design Automation Algorithms / VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 6: Detailed Routing

44 Placement Global Routing Detailed Routing 6.. Left-Edge Algorithm Example Left-Edge Algorithm Example 0 A D E A F G 0 D I J J C E C E F H I H G I. Generate VCG and zone representation A D J A G E I G C H I C H F D J E F Adapted from [Khang ] ECE 7 VLSI Physical Design: From Graph Partitioning to Timing Closure T: Physical Design Automation Algorithms Chapter 6: Detailed Routing /

45 Placement Global Routing Detailed Routing Left-Edge Algorithm Example 6.. Left-Edge Algorithm Example KLMH A D J A G E I G C H I C H F D J E F. Consider next track. Find left-to-right ordering of all unassigned nets If curr_net has no parents and does not cause conflicts on curr_track assign curr_net curr_track = : Net A Net J. Delete placed nets (A, J ) in VCG and zone represenation Adapted from [Khang ] VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 6: Detailed Routing 9 ECE 7 T: Physical Design Automation Algorithms / Lienig

46 Placement Global Routing Detailed Routing Left-Edge Algorithm Example curr_track = 0 A D E A F G 0 D I J J C E C E F H I H G I Adapted from [Khang ] ECE 7 T: Physical Design Automation Algorithms /

47 Placement Global Routing Detailed Routing Left-Edge Algorithm Example 6.. Left-Edge Algorithm Example KLMH D G E I G C H I C H F D E F. Consider next track. Find left-to-right ordering of all unassigned nets If curr_net has no parents and does not cause conflicts on curr_track assign curr_net curr_track = : Net D. Delete placed nets (D ) in VCG and zone representation Adapted from [Khang ] VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 6: Detailed Routing ECE 7 T: Physical Design Automation Algorithms / Lienig

48 Placement Global Routing Detailed Routing Left-Edge Algorithm Example curr_track = 0 A D E A F G 0 D I J J C E C E F H I H G I Adapted from [Khang ] ECE 7 T: Physical Design Automation Algorithms 6 /

49 Placement Global Routing Detailed Routing Left-Edge Algorithm Example 6.. Left-Edge Algorithm Example KLMH G E I G C H I C H F E F. Consider next track. Find left-to-right ordering of all unassigned nets If curr_net has no parents and does not cause conflicts on curr_track assign curr_net curr_track = : Net E Net G. Delete placed nets (E, G ) in VCG and zone representation Adapted from [Khang ] VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 6: Detailed Routing ECE 7 T: Physical Design Automation Algorithms 7 / Lienig

50 Placement Global Routing Detailed Routing Left-Edge Algorithm Example curr_track = 0 A D E A F G 0 D I J J C E C E F H I H G I Adapted from [Khang ] ECE 7 T: Physical Design Automation Algorithms 8 /

51 Placement Global Routing Detailed Routing Left-Edge Algorithm Example 6.. Left-Edge Algorithm Example KLMH I C H I C H F F. Consider next track. Find left-to-right ordering of all unassigned nets If curr_net has no parents and does not cause conflicts on curr_track assign curr_net curr_track = : Net C Net F Net I. Delete placed nets (C, F, I ) in VCG and zone representation Adapted from [Khang ] VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 6: Detailed Routing ECE 7 T: Physical Design Automation Algorithms 9 / Lienig

52 Placement Global Routing Detailed Routing Left-Edge Algorithm Example curr_track = 0 A D E A F G 0 D I J J C E C E F H I H G I Adapted from [Khang ] ECE 7 T: Physical Design Automation Algorithms 0 /

53 Placement Global Routing Detailed Routing Left-Edge Algorithm Example 6.. Left-Edge Algorithm Example KLMH H H. Consider next track. Find left-to-right ordering of all unassigned nets If curr_net has no parents and does not cause conflicts on curr_track assign curr_net curr_track = : Net Net H. Delete placed nets (, H ) in VCG and zone representation Adapted from [Khang ] VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 6: Detailed Routing 7 ECE 7 T: Physical Design Automation Algorithms / Lienig

54 Placement Global Routing Detailed Routing Left-Edge Algorithm Example curr_track = 0 A D E A F G 0 D I J J C E C E F H I H G I Routing result Adapted from [Khang ] ECE 7 T: Physical Design Automation Algorithms /

55 Placement Global Routing Detailed Routing Acknowledgments [Devadas 06] S. Devadas, VLSI CAD Flow: Logic Synthesis, Placement, and Routing, MIT 6.7 Complex Digital Systems Guest Lecture Slides, 006. [Kahng ] A.. Kahng, J. Liening, I.L. Markov, and J. Hu. Companion Slides for VLSI Physical Design: From Graph Partitioning to Timing Closure, Springer 0. ECE 7 T: Physical Design Automation Algorithms /