GPU-Accelerated Topology Optimization on Unstructured Meshes
|
|
|
- Gabriel Hawkins
- 6 years ago
- Views:
Transcription
1 GPU-Accelerated Topology Optimization on Unstructured Meshes Tomás Zegard, Glaucio H. Paulino University of Illinois at Urbana-Champaign July 25, 2011 Tomás Zegard, Glaucio H. Paulino (UIUC) GPU TOP on Unstructured Meshes July 25, / 20
2 Introduction Why? What? How? Is this madness? Goal Study the feasibility of the topology optimization algorithm to be implemented in a massively parallel fashion using conventional off-the-shelf hardware. (Hopefully) Speed up the process and prepare for future trends in computer architecture. Breaking up the title: GPU-Accelerated Topology Optimization on Unstructured Meshes What are GPUs? Why GPUs? Where can I find these GPUs? Why unstructured meshes? Challenges in parallelizing TOP... Tomás Zegard, Glaucio H. Paulino (UIUC) GPU TOP on Unstructured Meshes July 25, / 20
3 GPUs: A cheap massively parallel processor Or your own private and portable supercomputer... A GPU is a Graphics Processing Unit - The video card on your computer. They have evolved to a tremendous level of parallelism to keep up with the gaming, movie and professional graphics industry. CONTROL ALU ALU ALU ALU CACHE DRAM (a) Schematic of a CPU DRAM (b) Schematic of a GPU Tomás Zegard, Glaucio H. Paulino (UIUC) GPU TOP on Unstructured Meshes July 25, / 20
4 Unstructured Meshes Is real world structured? Or based on cubes? Real applications have complex boundaries and/or restrictions.? P (c) MBB beam & holes (-15,51) (-40,7.2) F =-50 y? (0,0) F =-10 x F =-10 y F =-15 x F =-10 y F =10 x (37,37) (40,54) R=38.25 (d) Curved and diagonal boundaries (42,43.5) (61,7.2) I have never seen a saw-toothed surface in a consumer product. Less room for interpretation issues. Tomás Zegard, Glaucio H. Paulino (UIUC) GPU TOP on Unstructured Meshes July 25, / 20
5 Race Condition The first big challenge... Race Condition A flaw where the output and/or result of a process is wrong because two events that cannot take place at the same time race against each other to influence the result. It is easier understood with a simple and practical example: = read store read store time (e) Sequential code with correct result Tomás Zegard, Glaucio H. Paulino (UIUC) GPU TOP on Unstructured Meshes July 25, / 20
6 Race Condition The first big challenge... What if the +3 operation occurs concurrently with the +7 operation? read store read store (f) Parallel code with wrong result time read store read store (g) Parallel code with wrong result time Tomás Zegard, Glaucio H. Paulino (UIUC) GPU TOP on Unstructured Meshes July 25, / 20
7 Graph Coloring Race hazard free FEM assembly... Only 4 colors are required to assemble a 2D structured mesh of Q4 elements, and 8 for B8. This does not apply for unstructured meshes. (h) Structured 2D mesh (i) Unstructured 2D mesh Tomás Zegard, Glaucio H. Paulino (UIUC) GPU TOP on Unstructured Meshes July 25, / 20
8 Greedy Coloring Greedy coloring is not good... most of the time. Greedy coloring algorithms are among the fastest (and worst) ones. But! There is a thread restriction: Number of elements per color Thread-constrained Greedy Coloring Algorithm Efficiency Lower Bound Coloring Algorithm 10 2 Colors NumberOfElements / NumberOfThreads (j) Coloring efficiency for a random mesh Tomás Zegard, Glaucio H. Paulino (UIUC) GPU TOP on Unstructured Meshes July 25, / 20
9 Areas, Volume Fraction and Others Reduction done the right way, the parallel way... The calculation of the domain area, volume fraction, change variable and others requires a reduction. A reduction traverses a large list and reduces it to a single value (k) Binary reduction Tomás Zegard, Glaucio H. Paulino (UIUC) GPU TOP on Unstructured Meshes July 25, / 20
10 Filter Cleaning up undesired things... The filter for each element is not obvious to compute as in a structured mesh. (l) Sample of a filter The search is done using the communication matrix (moving through neighbors) on a Breadth-First Search fashion (BFS). Stored in a very compact, simple and easy to read structure. Tomás Zegard, Glaucio H. Paulino (UIUC) GPU TOP on Unstructured Meshes July 25, / 20
11 Code Organization How it works... Legend CPU GPU Input File Input Parse Pre-Cruncher Assembly Assembly Apply B.C. Apply B.C. CPU Solver GPU Solver CPU Solver GPU Solver Sensitivity Sensitivity Filter Filter Density Upd. Density Upd. Output File Tomás Zegard, Glaucio H. Paulino (UIUC) GPU TOP on Unstructured Meshes July 25, / 20
12 Example 1: Bike A domain is generated considering the geometrical restrictions from an actual bike. Loading is expected to resemble a plausible loading scenario on a bike. (-15,51) (-40,7.2) F =-50 y? (0,0) F =-10 x F =-10 y F =-15 x F =-10 y F =10 x (37,37) (40,54) R=38.25 (42,43.5) (61,7.2) (n) Bike domain and boundary conditions E = , ν = 0.3, f = 0.3, p = 3 and R = iterations, elements and nodes. Tomás Zegard, Glaucio H. Paulino (UIUC) GPU TOP on Unstructured Meshes July 25, / 20
13 Example 1: Bike (o) CPU chain (p) CPU chain (GPU solver) (q) GPU chain (r) GPU chain (CPU solver) Tomás Zegard, Glaucio H. Paulino (UIUC) GPU TOP on Unstructured Meshes July 25, / 20
14 Examples 1: Bike What have we done?! (s) Final bike design with components traced Tomás Zegard, Glaucio H. Paulino (UIUC) GPU TOP on Unstructured Meshes July 25, / 20
15 Examples 2 & 3: Messerschmitt-Bölkow-Blohm Beam Example 2: Structured, 1 : 6 aspect ratio. 30 iterations, elements and nodes. Example 3: Unstructured, 0.4 : 1 : 6 - D : H : L ratio. 30 iterations, elements and nodes.? P (t) MBB beam with holes E = 100, ν = 0.3, f = 0.3, p = 3 and R = Tomás Zegard, Glaucio H. Paulino (UIUC) GPU TOP on Unstructured Meshes July 25, / 20
16 Examples 2 & 3: Messerschmitt-Bo lkow-blohm Beam (u) MBB: CPU chain (v) MBB: GPU chain (CPU solver) (w) MBB hole: CPU chain (x) MBB hole: GPU chain (CPU solver) Toma s Zegard, Glaucio H. Paulino (UIUC) GPU TOP on Unstructured Meshes July 25, / 20
17 Benchmarks Did we do well? Compute Chains Speedup 10 2 TOP Kernels Speedup Bike MBB MBB hole Speedup 0.6 Bike MBB MBB hole Speedup GPU Solver N.A. GPU Solver N.A. CPU CPU -X GPU GPU -X 10-1 No data for GPU Assemb. Solve Sensit. Filter Update (y) Runtime speedup (z) Broken down speedup Tomás Zegard, Glaucio H. Paulino (UIUC) GPU TOP on Unstructured Meshes July 25, / 20
18 Conclusions What have we learned so far? TOP in GPUs for unstructured meshes is indeed plausible and the current naïve implementation is slightly faster. The solver dominates the overall speedup taking approximately 90% of the runtime. Differences in the floating point precision and error handling does make a difference. A Greedy coloring algorithm is used with excellent results for large and practical problems. Current 1.0 to 1.1 speedup may not seem appealing now. But from this point onwards, improvements would raise the speedup to a clearly better-than-the-cpu code. Tremendous need for an efficient GPU solver. Tomás Zegard, Glaucio H. Paulino (UIUC) GPU TOP on Unstructured Meshes July 25, / 20
19 Future Work Where do we go from here? Full support for 3D problems. Support for Continuous Approximation of Material Distribution (CAMD) approach. Matsui K, Terada K, (2004) Faster and better coloring algorithms or race-condition-free assembly procedures. Cecka C, Lew AJ, Darve E, (2010) Add a flag to the code that indicates if the mesh is structured, and act accordingly. Schmidt S, Schulz V, (2009) Replace the GPU solver with a GOOD one. Tomov S, Nath R, Ltaief H, Dongarra J, (2010) Tomás Zegard, Glaucio H. Paulino (UIUC) GPU TOP on Unstructured Meshes July 25, / 20
20 Questions & Comments Tomás Zegard, Glaucio H. Paulino (UIUC) GPU TOP on Unstructured Meshes July 25, / 20
HARNESSING IRREGULAR PARALLELISM: A CASE STUDY ON UNSTRUCTURED MESHES. Cliff Woolley, NVIDIA
HARNESSING IRREGULAR PARALLELISM: A CASE STUDY ON UNSTRUCTURED MESHES Cliff Woolley, NVIDIA PREFACE This talk presents a case study of extracting parallelism in the UMT2013 benchmark for 3D unstructured-mesh
Register and Thread Structure Optimization for GPUs Yun (Eric) Liang, Zheng Cui, Kyle Rupnow, Deming Chen
Register and Thread Structure Optimization for GPUs Yun (Eric) Liang, Zheng Cui, Kyle Rupnow, Deming Chen Peking University, China Advanced Digital Science Center, Singapore University of Illinois at Urbana
PolyTop++: an efficient alternative for serial and parallel topology optimization on CPUs & GPUs
Struct Multidisc Optim (2015) 52:845 859 DOI 10.1007/s00158-015-1252-x RESEARCH PAPER PolyTop++: an efficient alternative for serial and parallel topology optimization on CPUs & GPUs Leonardo S. Duarte
On Level Scheduling for Incomplete LU Factorization Preconditioners on Accelerators
On Level Scheduling for Incomplete LU Factorization Preconditioners on Accelerators Karl Rupp, Barry Smith rupp@mcs.anl.gov Mathematics and Computer Science Division Argonne National Laboratory FEMTEC
Accelerated Load Balancing of Unstructured Meshes
Accelerated Load Balancing of Unstructured Meshes Gerrett Diamond, Lucas Davis, and Cameron W. Smith Abstract Unstructured mesh applications running on large, parallel, distributed memory systems require
Optimizing Energy Consumption and Parallel Performance for Static and Dynamic Betweenness Centrality using GPUs Adam McLaughlin, Jason Riedy, and
Optimizing Energy Consumption and Parallel Performance for Static and Dynamic Betweenness Centrality using GPUs Adam McLaughlin, Jason Riedy, and David A. Bader Motivation Real world graphs are challenging
Analytical Modeling of Parallel Systems. To accompany the text ``Introduction to Parallel Computing'', Addison Wesley, 2003.
Analytical Modeling of Parallel Systems To accompany the text ``Introduction to Parallel Computing'', Addison Wesley, 2003. Topic Overview Sources of Overhead in Parallel Programs Performance Metrics for
Lecture 7: Parallel Processing
Lecture 7: Parallel Processing Introduction and motivation Architecture classification Performance evaluation Interconnection network Zebo Peng, IDA, LiTH 1 Performance Improvement Reduction of instruction
Parallel Direct Simulation Monte Carlo Computation Using CUDA on GPUs
Parallel Direct Simulation Monte Carlo Computation Using CUDA on GPUs C.-C. Su a, C.-W. Hsieh b, M. R. Smith b, M. C. Jermy c and J.-S. Wu a a Department of Mechanical Engineering, National Chiao Tung
Basics of Performance Engineering
ERLANGEN REGIONAL COMPUTING CENTER Basics of Performance Engineering J. Treibig HiPerCH 3, 23./24.03.2015 Why hardware should not be exposed Such an approach is not portable Hardware issues frequently
[8] GEBREMEDHIN, A. H.; MANNE, F.; MANNE, G. F. ; OPENMP, P. Scalable parallel graph coloring algorithms, 2000.
![[8] GEBREMEDHIN, A. H.; MANNE, F.; MANNE, G. F. ; OPENMP, P. Scalable parallel graph coloring algorithms, 2000.](/thumbs/83/88367799.jpg "[8] GEBREMEDHIN, A. H.; MANNE, F.; MANNE, G. F. ; OPENMP, P. Scalable parallel graph coloring algorithms, 2000.")
9 Bibliography [1] CECKA, C.; LEW, A. J. ; DARVE, E. International Journal for Numerical Methods in Engineering. Assembly of finite element methods on graphics processors, journal, 2010. [2] CELES, W.;
HYPERDRIVE IMPLEMENTATION AND ANALYSIS OF A PARALLEL, CONJUGATE GRADIENT LINEAR SOLVER PROF. BRYANT PROF. KAYVON 15618: PARALLEL COMPUTER ARCHITECTURE
HYPERDRIVE IMPLEMENTATION AND ANALYSIS OF A PARALLEL, CONJUGATE GRADIENT LINEAR SOLVER AVISHA DHISLE PRERIT RODNEY ADHISLE PRODNEY 15618: PARALLEL COMPUTER ARCHITECTURE PROF. BRYANT PROF. KAYVON LET S
GPU-Accelerated Parallel Sparse LU Factorization Method for Fast Circuit Analysis
GPU-Accelerated Parallel Sparse LU Factorization Method for Fast Circuit Analysis Abstract: Lower upper (LU) factorization for sparse matrices is the most important computing step for circuit simulation
Scalable Dynamic Adaptive Simulations with ParFUM
Scalable Dynamic Adaptive Simulations with ParFUM Terry L. Wilmarth Center for Simulation of Advanced Rockets and Parallel Programming Laboratory University of Illinois at Urbana-Champaign The Big Picture
Introduction to CUDA Algoritmi e Calcolo Parallelo. Daniele Loiacono
Introduction to CUDA Algoritmi e Calcolo Parallelo References q This set of slides is mainly based on: " CUDA Technical Training, Dr. Antonino Tumeo, Pacific Northwest National Laboratory " Slide of Applied
IMPLEMENTATION OF THE. Alexander J. Yee University of Illinois Urbana-Champaign
SINGLE-TRANSPOSE IMPLEMENTATION OF THE OUT-OF-ORDER 3D-FFT Alexander J. Yee University of Illinois Urbana-Champaign The Problem FFTs are extremely memory-intensive. Completely bound by memory access. Memory
In topology optimization, the parameterization of design and approximation of its response are closely linked through the discretization process
In topology optimization, the parameterization of design and approximation of its response are closely linked through the discretization process For example, in the element-based approach, the design variables
GPU Programming Using NVIDIA CUDA
GPU Programming Using NVIDIA CUDA Siddhante Nangla 1, Professor Chetna Achar 2 1, 2 MET s Institute of Computer Science, Bandra Mumbai University Abstract: GPGPU or General-Purpose Computing on Graphics
Why Use the GPU? How to Exploit? New Hardware Features. Sparse Matrix Solvers on the GPU: Conjugate Gradients and Multigrid. Semiconductor trends
Imagine stream processor; Bill Dally, Stanford Connection Machine CM; Thinking Machines Sparse Matrix Solvers on the GPU: Conjugate Gradients and Multigrid Jeffrey Bolz Eitan Grinspun Caltech Ian Farmer
ACHIEVING MINIMUM LENGTH SCALE AND DESIGN CONSTRAINTS IN TOPOLOGY OPTIMIZATION: A NEW APPROACH CHAU HOAI LE
ACHIEVING MINIMUM LENGTH SCALE AND DESIGN CONSTRAINTS IN TOPOLOGY OPTIMIZATION: A NEW APPROACH BY CHAU HOAI LE B.E., Hanoi National Institute of Civil Engineering, 1997 THESIS Submitted in partial fulfillment
CUDA. Matthew Joyner, Jeremy Williams
CUDA Matthew Joyner, Jeremy Williams Agenda What is CUDA? CUDA GPU Architecture CPU/GPU Communication Coding in CUDA Use cases of CUDA Comparison to OpenCL What is CUDA? What is CUDA? CUDA is a parallel
Scalable GPU Graph Traversal!
Scalable GPU Graph Traversal Duane Merrill, Michael Garland, and Andrew Grimshaw PPoPP '12 Proceedings of the 17th ACM SIGPLAN symposium on Principles and Practice of Parallel Programming Benwen Zhang
CS8803SC Software and Hardware Cooperative Computing GPGPU. Prof. Hyesoon Kim School of Computer Science Georgia Institute of Technology
CS8803SC Software and Hardware Cooperative Computing GPGPU Prof. Hyesoon Kim School of Computer Science Georgia Institute of Technology Why GPU? A quiet revolution and potential build-up Calculation: 367
POST-SIEVING ON GPUs
POST-SIEVING ON GPUs Andrea Miele 1, Joppe W Bos 2, Thorsten Kleinjung 1, Arjen K Lenstra 1 1 LACAL, EPFL, Lausanne, Switzerland 2 NXP Semiconductors, Leuven, Belgium 1/18 NUMBER FIELD SIEVE (NFS) Asymptotically
CS 475: Parallel Programming Introduction
CS 475: Parallel Programming Introduction Wim Bohm, Sanjay Rajopadhye Colorado State University Fall 2014 Course Organization n Let s make a tour of the course website. n Main pages Home, front page. Syllabus.
Storage Hierarchy Management for Scientific Computing
Storage Hierarchy Management for Scientific Computing by Ethan Leo Miller Sc. B. (Brown University) 1987 M.S. (University of California at Berkeley) 1990 A dissertation submitted in partial satisfaction
VTK-m: Uniting GPU Acceleration Successes. Robert Maynard Kitware Inc.
VTK-m: Uniting GPU Acceleration Successes Robert Maynard Kitware Inc. VTK-m Project Supercomputer Hardware Advances Everyday More and more parallelism High-Level Parallelism The Free Lunch Is Over (Herb
Performance impact of dynamic parallelism on different clustering algorithms
Performance impact of dynamic parallelism on different clustering algorithms Jeffrey DiMarco and Michela Taufer Computer and Information Sciences, University of Delaware E-mail: jdimarco@udel.edu, taufer@udel.edu
Introduction to Parallel Computing. CPS 5401 Fall 2014 Shirley Moore, Instructor October 13, 2014
Introduction to Parallel Computing CPS 5401 Fall 2014 Shirley Moore, Instructor October 13, 2014 1 Definition of Parallel Computing Simultaneous use of multiple compute resources to solve a computational
GTC 2013: DEVELOPMENTS IN GPU-ACCELERATED SPARSE LINEAR ALGEBRA ALGORITHMS. Kyle Spagnoli. Research EM Photonics 3/20/2013
GTC 2013: DEVELOPMENTS IN GPU-ACCELERATED SPARSE LINEAR ALGEBRA ALGORITHMS Kyle Spagnoli Research Engineer @ EM Photonics 3/20/2013 INTRODUCTION» Sparse systems» Iterative solvers» High level benchmarks»
Lecture 7: Parallel Processing
Lecture 7: Parallel Processing Introduction and motivation Architecture classification Performance evaluation Interconnection network Zebo Peng, IDA, LiTH 1 Performance Improvement Reduction of instruction
Chasing Away RAts: Semantics and Evaluation for Relaxed Atomics on Heterogeneous Systems
Chasing Away RAts: Semantics and Evaluation for Relaxed Atomics on Heterogeneous Systems Matthew D. Sinclair, Johnathan Alsop, Sarita V. Adve University of Illinois @ Urbana-Champaign hetero@cs.illinois.edu
PARALLEL ID3. Jeremy Dominijanni CSE633, Dr. Russ Miller
PARALLEL ID3 Jeremy Dominijanni CSE633, Dr. Russ Miller 1 ID3 and the Sequential Case 2 ID3 Decision tree classifier Works on k-ary categorical data Goal of ID3 is to maximize information gain at each
«Computer Science» Requirements for applicants by Innopolis University
«Computer Science» Requirements for applicants by Innopolis University Contents Architecture and Organization... 2 Digital Logic and Digital Systems... 2 Machine Level Representation of Data... 2 Assembly
Game Level Layout from Design Specification
Copyright of figures and other materials in the paper belongs original authors. Game Level Layout from Design Specification Chongyang Ma et al. EUROGRAPHICS 2014 Presented by YoungBin Kim 2015. 01. 13
Efficient Multi-GPU CUDA Linear Solvers for OpenFOAM
Efficient Multi-GPU CUDA Linear Solvers for OpenFOAM Alexander Monakov, amonakov@ispras.ru Institute for System Programming of Russian Academy of Sciences March 20, 2013 1 / 17 Problem Statement In OpenFOAM,
High Performance Computing on GPUs using NVIDIA CUDA
High Performance Computing on GPUs using NVIDIA CUDA Slides include some material from GPGPU tutorial at SIGGRAPH2007: http://www.gpgpu.org/s2007 1 Outline Motivation Stream programming Simplified HW and
Performance Analysis of the Lattice Boltzmann Method on x86-64 Architectures
Performance Analysis of the Lattice Boltzmann Method on x86-64 Architectures Jan Treibig, Simon Hausmann, Ulrich Ruede Zusammenfassung The Lattice Boltzmann method (LBM) is a well established algorithm
Efficient Tridiagonal Solvers for ADI methods and Fluid Simulation
Efficient Tridiagonal Solvers for ADI methods and Fluid Simulation Nikolai Sakharnykh - NVIDIA San Jose Convention Center, San Jose, CA September 21, 2010 Introduction Tridiagonal solvers very popular
Introduction to CUDA Algoritmi e Calcolo Parallelo. Daniele Loiacono
Introduction to CUDA Algoritmi e Calcolo Parallelo References This set of slides is mainly based on: CUDA Technical Training, Dr. Antonino Tumeo, Pacific Northwest National Laboratory Slide of Applied
Quiz for Chapter 1 Computer Abstractions and Technology
Date: Not all questions are of equal difficulty. Please review the entire quiz first and then budget your time carefully. Name: Course: Solutions in Red 1. [15 points] Consider two different implementations,
EE382N (20): Computer Architecture - Parallelism and Locality Fall 2011 Lecture 14 Parallelism in Software V
EE382 (20): Computer Architecture - Parallelism and Locality Fall 2011 Lecture 14 Parallelism in Software V Mattan Erez The University of Texas at Austin EE382: Parallelilsm and Locality, Fall 2011 --
HPC Algorithms and Applications
HPC Algorithms and Applications Dwarf #5 Structured Grids Michael Bader Winter 2012/2013 Dwarf #5 Structured Grids, Winter 2012/2013 1 Dwarf #5 Structured Grids 1. dense linear algebra 2. sparse linear
Lecture 1: Introduction and Computational Thinking
PASI Summer School Advanced Algorithmic Techniques for GPUs Lecture 1: Introduction and Computational Thinking 1 Course Objective To master the most commonly used algorithm techniques and computational
Pattern Gradation and Repetition with Application to High-Rise Building Design
Pattern Gradation and Repetition with Application to High-Rise Building Design Lauren L. Stromberg, Glaucio H. Paulino, William F. Baker 10 th US National Congress on Computational Mechanics Columbus,
G P G P U : H I G H - P E R F O R M A N C E C O M P U T I N G
Joined Advanced Student School (JASS) 2009 March 29 - April 7, 2009 St. Petersburg, Russia G P G P U : H I G H - P E R F O R M A N C E C O M P U T I N G Dmitry Puzyrev St. Petersburg State University Faculty
GENERAL-PURPOSE COMPUTATION USING GRAPHICAL PROCESSING UNITS
GENERAL-PURPOSE COMPUTATION USING GRAPHICAL PROCESSING UNITS Adrian Salazar, Texas A&M-University-Corpus Christi Faculty Advisor: Dr. Ahmed Mahdy, Texas A&M-University-Corpus Christi ABSTRACT Graphical
Double-Precision Matrix Multiply on CUDA
Double-Precision Matrix Multiply on CUDA Parallel Computation (CSE 60), Assignment Andrew Conegliano (A5055) Matthias Springer (A995007) GID G--665 February, 0 Assumptions All matrices are square matrices
Accelerating Leukocyte Tracking Using CUDA: A Case Study in Leveraging Manycore Coprocessors
Accelerating Leukocyte Tracking Using CUDA: A Case Study in Leveraging Manycore Coprocessors Michael Boyer, David Tarjan, Scott T. Acton, and Kevin Skadron University of Virginia IPDPS 2009 Outline Leukocyte
A modified Q4/Q4 element for topology optimization
Struct Multidisc Optim (009) 7:55 6 DOI 0.007/s0058-008-08-5 RESEARCH PAPER A modified Q/Q element for topology optimization Glaucio H. Paulino Chau H. Le Received: November 005 / Revised: 9 November 007
COMP 633 Parallel Computing.
COMP 633 Parallel Computing http://www.cs.unc.edu/~prins/classes/633/ Parallel computing What is it? multiple processors cooperating to solve a single problem hopefully faster than a single processor!
Pipelining and Vector Processing
Chapter 8 Pipelining and Vector Processing 8 1 If the pipeline stages are heterogeneous, the slowest stage determines the flow rate of the entire pipeline. This leads to other stages idling. 8 2 Pipeline
Performance and accuracy of hardware-oriented. native-, solvers in FEM simulations
Robert Strzodka, Stanford University Dominik Göddeke, Universität Dortmund Performance and accuracy of hardware-oriented native-, emulated- and mixed-precision solvers in FEM simulations Number of slices
Performance potential for simulating spin models on GPU
Performance potential for simulating spin models on GPU Martin Weigel Institut für Physik, Johannes-Gutenberg-Universität Mainz, Germany 11th International NTZ-Workshop on New Developments in Computational
EE382N (20): Computer Architecture - Parallelism and Locality Lecture 10 Parallelism in Software I
EE382 (20): Computer Architecture - Parallelism and Locality Lecture 10 Parallelism in Software I Mattan Erez The University of Texas at Austin EE382: Parallelilsm and Locality (c) Rodric Rabbah, Mattan
EECS4201 Computer Architecture
Computer Architecture A Quantitative Approach, Fifth Edition Chapter 1 Fundamentals of Quantitative Design and Analysis These slides are based on the slides provided by the publisher. The slides will be
GPGPU LAB. Case study: Finite-Difference Time- Domain Method on CUDA
GPGPU LAB Case study: Finite-Difference Time- Domain Method on CUDA Ana Balevic IPVS 1 Finite-Difference Time-Domain Method Numerical computation of solutions to partial differential equations Explicit
Greedy algorithms is another useful way for solving optimization problems.
Greedy Algorithms Greedy algorithms is another useful way for solving optimization problems. Optimization Problems For the given input, we are seeking solutions that must satisfy certain conditions. These
Power Estimation of UVA CS754 CMP Architecture
Introduction Power Estimation of UVA CS754 CMP Architecture Mateja Putic mateja@virginia.edu Early power analysis has become an essential part of determining the feasibility of microprocessor design. As
The Fast Multipole Method on NVIDIA GPUs and Multicore Processors
The Fast Multipole Method on NVIDIA GPUs and Multicore Processors Toru Takahashi, a Cris Cecka, b Eric Darve c a b c Department of Mechanical Science and Engineering, Nagoya University Institute for Applied
Krishnan Suresh Associate Professor Mechanical Engineering
Large Scale FEA on the GPU Krishnan Suresh Associate Professor Mechanical Engineering High-Performance Trick Computations (i.e., 3.4*1.22): essentially free Memory access determines speed of code Pick
Review of previous examinations TMA4280 Introduction to Supercomputing
Review of previous examinations TMA4280 Introduction to Supercomputing NTNU, IMF April 24. 2017 1 Examination The examination is usually comprised of: one problem related to linear algebra operations with
CS140 Final Project. Nathan Crandall, Dane Pitkin, Introduction:
Nathan Crandall, 3970001 Dane Pitkin, 4085726 CS140 Final Project Introduction: Our goal was to parallelize the Breadth-first search algorithm using Cilk++. This algorithm works by starting at an initial
Towards Breast Anatomy Simulation Using GPUs
Towards Breast Anatomy Simulation Using GPUs Joseph H. Chui 1, David D. Pokrajac 2, Andrew D.A. Maidment 3, and Predrag R. Bakic 4 1 Department of Radiology, University of Pennsylvania, Philadelphia PA
8.1 Background. Part Four - Memory Management. Chapter 8: Memory-Management Management Strategies. Chapter 8: Memory Management
Part Four - Memory Management 8.1 Background Chapter 8: Memory-Management Management Strategies Program must be brought into memory and placed within a process for it to be run Input queue collection of
Summary: Open Questions:
Summary: The paper proposes an new parallelization technique, which provides dynamic runtime parallelization of loops from binary single-thread programs with minimal architectural change. The realization
Supplementary Materials for
advances.sciencemag.org/cgi/content/full/4/1/eaao7005/dc1 Supplementary Materials for Computational discovery of extremal microstructure families The PDF file includes: Desai Chen, Mélina Skouras, Bo Zhu,
Optimizing Memory-Bound Numerical Kernels on GPU Hardware Accelerators
Optimizing Memory-Bound Numerical Kernels on GPU Hardware Accelerators Ahmad Abdelfattah 1, Jack Dongarra 2, David Keyes 1 and Hatem Ltaief 3 1 KAUST Division of Mathematical and Computer Sciences and
Multiprocessors and Thread Level Parallelism Chapter 4, Appendix H CS448. The Greed for Speed
Multiprocessors and Thread Level Parallelism Chapter 4, Appendix H CS448 1 The Greed for Speed Two general approaches to making computers faster Faster uniprocessor All the techniques we ve been looking
Memory Hierarchy Management for Iterative Graph Structures
Memory Hierarchy Management for Iterative Graph Structures Ibraheem Al-Furaih y Syracuse University Sanjay Ranka University of Florida Abstract The increasing gap in processor and memory speeds has forced
X10 specific Optimization of CPU GPU Data transfer with Pinned Memory Management
X10 specific Optimization of CPU GPU Data transfer with Pinned Memory Management Hideyuki Shamoto, Tatsuhiro Chiba, Mikio Takeuchi Tokyo Institute of Technology IBM Research Tokyo Programming for large
Chapter 8: Memory- Management Strategies. Operating System Concepts 9 th Edition
Chapter 8: Memory- Management Strategies Operating System Concepts 9 th Edition Silberschatz, Galvin and Gagne 2013 Chapter 8: Memory Management Strategies Background Swapping Contiguous Memory Allocation
Optimization Principles and Application Performance Evaluation of a Multithreaded GPU Using CUDA
Optimization Principles and Application Performance Evaluation of a Multithreaded GPU Using CUDA Shane Ryoo, Christopher I. Rodrigues, Sara S. Baghsorkhi, Sam S. Stone, David B. Kirk, and Wen-mei H. Hwu
Cache Capacity Aware Thread Scheduling for Irregular Memory Access on Many-Core GPGPUs
Cache Capacity Aware Thread Scheduling for Irregular Memory Access on Many-Core GPGPUs Hsien-Kai Kuo, Ta-Kan Yen, Bo-Cheng Charles Lai and Jing-Yang Jou Department of Electronics Engineering National Chiao
Data parallel algorithms 1
Data parallel algorithms (Guy Steele): The data-parallel programming style is an approach to organizing programs suitable for execution on massively parallel computers. In this lecture, we will characterize
Evaluation and Exploration of Next Generation Systems for Applicability and Performance Volodymyr Kindratenko Guochun Shi
Evaluation and Exploration of Next Generation Systems for Applicability and Performance Volodymyr Kindratenko Guochun Shi National Center for Supercomputing Applications University of Illinois at Urbana-Champaign
Fast Multipole and Related Algorithms
Fast Multipole and Related Algorithms Ramani Duraiswami University of Maryland, College Park http://www.umiacs.umd.edu/~ramani Joint work with Nail A. Gumerov Efficiency by exploiting symmetry and A general
GPU Sparse Graph Traversal. Duane Merrill
GPU Sparse Graph Traversal Duane Merrill Breadth-first search of graphs (BFS) 1. Pick a source node 2. Rank every vertex by the length of shortest path from source Or label every vertex by its predecessor
CSCI 402: Computer Architectures. Parallel Processors (2) Fengguang Song Department of Computer & Information Science IUPUI.
CSCI 402: Computer Architectures Parallel Processors (2) Fengguang Song Department of Computer & Information Science IUPUI 6.6 - End Today s Contents GPU Cluster and its network topology The Roofline performance
Maximize automotive simulation productivity with ANSYS HPC and NVIDIA GPUs
Presented at the 2014 ANSYS Regional Conference- Detroit, June 5, 2014 Maximize automotive simulation productivity with ANSYS HPC and NVIDIA GPUs Bhushan Desam, Ph.D. NVIDIA Corporation 1 NVIDIA Enterprise
Chapter 27 Cluster Work Queues
Chapter 27 Cluster Work Queues Part I. Preliminaries Part II. Tightly Coupled Multicore Part III. Loosely Coupled Cluster Chapter 18. Massively Parallel Chapter 19. Hybrid Parallel Chapter 20. Tuple Space
A POWER CHARACTERIZATION AND MANAGEMENT OF GPU GRAPH TRAVERSAL
A POWER CHARACTERIZATION AND MANAGEMENT OF GPU GRAPH TRAVERSAL ADAM MCLAUGHLIN *, INDRANI PAUL, JOSEPH GREATHOUSE, SRILATHA MANNE, AND SUDHKAHAR YALAMANCHILI * * GEORGIA INSTITUTE OF TECHNOLOGY AMD RESEARCH
GraFBoost: Using accelerated flash storage for external graph analytics
GraFBoost: Using accelerated flash storage for external graph analytics Sang-Woo Jun, Andy Wright, Sizhuo Zhang, Shuotao Xu and Arvind MIT CSAIL Funded by: 1 Large Graphs are Found Everywhere in Nature
Introducing Overdecomposition to Existing Applications: PlasComCM and AMPI
Introducing Overdecomposition to Existing Applications: PlasComCM and AMPI Sam White Parallel Programming Lab UIUC 1 Introduction How to enable Overdecomposition, Asynchrony, and Migratability in existing
2D rendering takes a photo of the 2D scene with a virtual camera that selects an axis aligned rectangle from the scene. The photograph is placed into
2D rendering takes a photo of the 2D scene with a virtual camera that selects an axis aligned rectangle from the scene. The photograph is placed into the viewport of the current application window. A pixel
Parallel Programming Interfaces
Parallel Programming Interfaces Background Different hardware architectures have led to fundamentally different ways parallel computers are programmed today. There are two basic architectures that general
Flexible Hardware Mapping for Finite Element Simulations on Hybrid CPU/GPU Clusters
Flexible Hardware Mapping for Finite Element Simulations on Hybrid /GPU Clusters Aaron Becker (abecker3@illinois.edu) Isaac Dooley Laxmikant Kale SAAHPC, July 30 2009 Champaign-Urbana, IL Target Application
Toward Runtime Power Management of Exascale Networks by On/Off Control of Links
Toward Runtime Power Management of Exascale Networks by On/Off Control of Links, Nikhil Jain, Laxmikant Kale University of Illinois at Urbana-Champaign HPPAC May 20, 2013 1 Power challenge Power is a major
Center for Computational Science
Center for Computational Science Toward GPU-accelerated meshfree fluids simulation using the fast multipole method Lorena A Barba Boston University Department of Mechanical Engineering with: Felipe Cruz,
Real-Time Shape Editing using Radial Basis Functions
Real-Time Shape Editing using Radial Basis Functions, Leif Kobbelt RWTH Aachen Boundary Constraint Modeling Prescribe irregular constraints Vertex positions Constrained energy minimization Optimal fairness
Computer and Information Sciences College / Computer Science Department CS 207 D. Computer Architecture
Computer and Information Sciences College / Computer Science Department CS 207 D Computer Architecture The Computer Revolution Progress in computer technology Underpinned by Moore s Law Makes novel applications
Scan Primitives for GPU Computing
Scan Primitives for GPU Computing Agenda What is scan A naïve parallel scan algorithm A work-efficient parallel scan algorithm Parallel segmented scan Applications of scan Implementation on CUDA 2 Prefix
Optimization solutions for the segmented sum algorithmic function
Optimization solutions for the segmented sum algorithmic function ALEXANDRU PÎRJAN Department of Informatics, Statistics and Mathematics Romanian-American University 1B, Expozitiei Blvd., district 1, code
Parallel Programming: Background Information
1 Parallel Programming: Background Information Mike Bailey mjb@cs.oregonstate.edu parallel.background.pptx Three Reasons to Study Parallel Programming 2 1. Increase performance: do more work in the same
Parallel Programming: Background Information
1 Parallel Programming: Background Information Mike Bailey mjb@cs.oregonstate.edu parallel.background.pptx Three Reasons to Study Parallel Programming 2 1. Increase performance: do more work in the same
Acceleration of a Python-based Tsunami Modelling Application via CUDA and OpenHMPP
Acceleration of a Python-based Tsunami Modelling Application via CUDA and OpenHMPP Zhe Weng and Peter Strazdins*, Computer Systems Group, Research School of Computer Science, The Australian National University
Computational Fluid Dynamics using OpenCL a Practical Introduction
19th International Congress on Modelling and Simulation, Perth, Australia, 12 16 December 2011 http://mssanz.org.au/modsim2011 Computational Fluid Dynamics using OpenCL a Practical Introduction T Bednarz
Figure 6.1: Truss topology optimization diagram.
6 Implementation 6.1 Outline This chapter shows the implementation details to optimize the truss, obtained in the ground structure approach, according to the formulation presented in previous chapters.
AdaStreams : A Type-based Programming Extension for Stream-Parallelism with Ada 2005
AdaStreams : A Type-based Programming Extension for Stream-Parallelism with Ada 2005 Gingun Hong*, Kirak Hong*, Bernd Burgstaller* and Johan Blieberger *Yonsei University, Korea Vienna University of Technology,
Kartik Lakhotia, Rajgopal Kannan, Viktor Prasanna USENIX ATC 18
Accelerating PageRank using Partition-Centric Processing Kartik Lakhotia, Rajgopal Kannan, Viktor Prasanna USENIX ATC 18 Outline Introduction Partition-centric Processing Methodology Analytical Evaluation