ELEN : Project Progress Report. Second Order Delay Computation for RC networks with Non-Tree Topology

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1 ELEN : Project Progress eport Second Order Delay Coputation for C networks wi Non-Tree Topology ajeshwary Tayade //003 PDF created wi pdffactory trial version

2 : Introduction Wi DSM technologies, Interconnect delay is turning out to be a ore doinating coponent of e total syste delay. A lot of work has been devoted towards accurate and efficient coputation of interconnect delay. The ost popular interconnect odel is e C-π odel which will be eployed in is project. A coprehensive coverage of e tiing etrics at are being traditionally used for delay estiation is given in []. These eods are suarized below: ) Elore Delay: Estiates e delay in ters of e step response of e equivalent C circuit. Elore observed at e step response of a C circuit can be viewed as e CDF function of a rando variable. Then e 50% delay point t d corresponds to e edian of e CDF function. The Elore delay approxiates e edian to e ean of e distribution and is given by T D = G C () where G and C are e pa conductance atrix and node capacitance vector respectively. Thus for a generalized network, Elore delay coputation requires a single atrix inversion. In [], it was shown at for C-tree topologies, Elore delay can be coputed using siple pa tracing algori instead of a atrix inversion. In [] it was proved at Elore delay fors e upper bounds on e delay for bo rap and step input signal. Due to its siplicity Elore delay has been e ost popular etric for interconnect delay estiation for years. The ain proble of Elore delay is at it neglects e resistive shielding effect [] for long nets. Thus e Elore delay can be seen as a good bound, but e estiates obtained are good only for soe regularstructure circuits such as clock tree. ) AWE: Autoatic Wavefor Evaluation [3] is a highly accurate but coputationally intensive eod, in which e syste transfer function is first obtained using e syste oents. Each oent coputation requires just e DC-analysis of e equivalent Ccircuit and us e transfer function of any order can be obtained. Once e transfer function is obtained, e syste response and delay can be observed for any generalized input function. (Note at oent coputation for a C-tree topology is siple, but for non-tree topologies it requires atrix inversion.) PDF created wi pdffactory trial version

3 3) Model Order eduction: These eods try to achieve a trade-off between e accuracy of AWE and e siplicity of Elore delay by approxiating nd or 3 rd order systes as in [4] [5]. The proble wi ese eods at it syste function obtained can be unstable and/or can produce coplex poles. Also after obtaining e syste ipulse response, non-linear operations have to be used to deterine e syste delay. 4) Probability Interpretation: This eod is a continuation of Elore s concept of viewing e syste ipulse response as a PDF of a statistical distribution. The ain idea is at we want to find e edian of e step response. So we try to atch e syste stepresponse to soe well-known CDF and e proble of delay calculation now translates into e proble of coputing e edian of is distribution. The atching in turn is done by equating e first ree central oents of e distribution (ean, variance and skewness) to e first ree circuit oents. This approach was proposed in [6] in which a tie-shifted incoplete Gaa function was used for odeling. In [7] is sae odeling is extended to atch e hoogenous portion of e step response to e gaa distribution. In [] e odeling was furer siplified by using e Weibull distribution for atching; e advantage being at e edian of e Weibull distribution is a direct function of its paraeters. These eods involves non-linear apping and hence is based on look-up-table evaluation. One ore advantage of is eod is at after e syste oents are obtained, delay calculation is independent of e circuit topology (no instability issues) which akes is eod a better choice for generalized topology. In is project e objective is to obtain e second-order delay estiates for a generalized Cesh (i.e. tree or non-tree). All capacitances are grounded and ere are no resistive pas to ground. As entioned above a tree structure provides a huge coputational gain and hence ost eods are focused towards solving for tree structures. In is project we use e Tree-Link partitioning algori to calculate e first two oents of e non-tree circuit and en use e WED (Weibull based delay) approxiation in [] to copute e second-order delay. The report is organized as follows: Section gives describes e Tree-link Partitioning eod and how it has been ipleented in e project. Section 3 describes e Weibull Distribution and WED eod. Section 4 gives e coplete procedure in brief and e ipleentation details, probles faced etc. Section 5 describes e exaples on which e eod was ipleented and section 6 suarizes e project. PDF created wi pdffactory trial version 3

4 : Non-Tree Topology and Tree-Link Partitioning As entioned in e first section, ost delay estiation eods need to copute e circuit oents. Each oent calculation can be represented as a siple dc-analysis procedure and hence can be solved using atrix inversion. For a C Tree network, i.e. a topology where ere is a unique pa fro any node to e source, we need not calculate e atrix inverse. The solution is obtained using a siple tree-traversal algori [] in O(n) tie-coplexity. However consider a general C network also called a C esh: Figure : Non Tree-circuit topology Here ere are two pas fro source S to node B, naely S-A-B and S-E-F-F-B. Thus if we want to calculate e delay at node B, it is not clear what links to use for e load-side capacitance and which ones to use for e driver-side esistance values. For such cases we cannot use siple tree traversal procedure and ight need to use a direct atrix-inverse procedure for delay calculation. A siple solution for is proble is proposed in [9], called a Tree-link Partitioning algori. The basic idea is to first obtain a spanning tree for e given network using Dep-First-Search and use e edges not part of e tree as links. The node voltages (in our case oents) are coputed for e spanning tree first using e tree-traversal procedure and en each link is added while updating e node voltages using Large Change Sensitivity analysis. The Tree/Link Partitioning eod proposed in [9] obtains e first order delay (Elore) as shown below: t di = n j= i, j C [ v ( ) v (0)] v ( ) v (0) i j i i i Now using Large Change sensitivity if e node voltages (which correspond to e oents in our case) of a circuit are known, en e result of adding a resistive branch is given by: ) vk v v = v + l Y ξ Assuing e initial and final voltages are sae in bo e cases, we obtain: () (3) PDF created wi pdffactory trial version 4

5 vk vk t vl vl t v ) ( ( ) ( ) ( ( ) ( ))) ( ) v ) (0) = v( ) v(0) Y ξ + (4) Thus e Elore delay for e non-tree circuit becoes: tˆ d ( t t ) = td Y ξ (5) ( d, k d, l + ) We need to estiate e second order delays for higher accuracy and at would require bo first and second oents. The details of e eod used for oent calculation is given in section 4. 3: Weibull Based Delay (WED) The PDF of a -paraeter Weibull distribution is given by: P WEI ( t) The CDF is given by C WEI α α ( t / β ) = αβ t e for t,α,β >0 (6) α ( t / β ) ( t) = e (7) Here α and β are e two paraeters, α is called e shape paraeter and β is e location paraeter. Figure shows plots of Weibull Distribution for different values of α and sae β. The idea is to atch e step-response of e circuit to e CDF of a Weibull distribution. This can be done by atching e statistical oents of e Weibull CDF to e circuit oents. The first two oents (naely e ean and variance) of e Weibull distribution is given by: µ WEI = βγ( + θ ) and σ = β ( Γ( + θ ) Γ ( + θ )) where θ = /α WEI (8) Given e circuit oents and, e central oents (ean and variance) are obtained as µ = and σ = (9) Now, we have σ WEI Γ( + θ ) =, (0) µ WEI Γ ( + θ ) PDF created wi pdffactory trial version 5

6 CDF of Weibull distribution for different alpha, beta= alpha= alpha= alpha= Then Matching e Circuit ean and variance to at of e Weibull distribution, we obtain: Now, Let Γ ( + θ ) = Γ ( + θ ) ; () Γ( + θ ) r = = () Γ ( + θ) Then Given e circuit oents, e value of θ can be obtained using e inverse Gaa function. Since is is a non-linear relation and is coplicated to solve, it is ipleented using a siple Look-up Table. After θ is obtained, en fro e ean atching, we get β = Γ(+ θ) The 50% delay point is en obtained using e forula for e edian of e Weibull distribution: (3) θ t 0.5 = β (ln()) (4) Thus e ain advantage of using is eod is at once e two circuit oents are obtained at each node, a siple algori (described later) can be used to get e delay irrespective of e circuit topology. 4: Procedure In e above two sections we have discussed two different papers/concepts. The first one is a eod to obtain e first order delay for a non-tree C circuit using Tree-Link partitioning, and PDF created wi pdffactory trial version 6

7 e second one is a procedure to obtain circuit delay using Weibull distribution approxiation of e step-response. In is project, we cobine e two ideas to get e second-order delay of a generalized C circuit. The WED eod requires e first two circuit oents and after at e delay calculation is just based on Look-up Tables. So e ain issue is to copute e oents of e C-non-tree circuit correctly. As entioned in section, we first get a spanning tree of e circuit and calculate e first and second order oents for is tree-circuit. Let e four oents be denoted as tree tree,, non tree, non tree. Fro equation (5) it is clear at e first order oent for e non-tree can be easily coputed by adding one link at a tie and using siple large-changesensitivity analysis. Thus e first oent for node i after adding a link k-l is given by, nontree, i tree tree k tree l,, = i Y, ξ (5) + The question now was to choose between e following two eods for coputing ) Meod : r r r r v ( s) = + s + s r r ˆ s + ˆ Thus r ˆ 0 s + K k r = s + = r k + l l Y sy ξ ξ and r + r ˆ s = r k + k l + s l Y Y ξ ξ non tree This eod was presented in e progress-report and it akes an underlying assuption at e large-change-sensitivity analysis is applicable to ac signal. The eod is shown in Figure a. ) Meod : Figure (b) shows e second eod used. We know at value of depends on at of. In e first eod e eod uses e new values i.e. tree is coputed using e non tree values. tree values, while e second The results in section 5 shows e delay values obtained using bo e eods. PDF created wi pdffactory trial version 7

8 Figure (a): Meod to copute second-order non-tree oent Figure (b): Meod to copute e second-order non-tree oent The entire procedure requires e following steps: ) Given an input interconnect geoetry in rectilinear space; create a C-circuit using e pi-odel. In y progra, e input was taken as a file and each node object knows its node capacitance and connections to oer nodes. Note at in rectilinear space, each node has only 4 possible connections, naely left, top, right and botto. The input file also has e total nuber of nodes, e unit r and unit c values and e driver resistance value. ) This collection of node now fors a graph. Perfor DFS on is graph wi e source node as e root. The DFS traverses only certain edges which for e DFS tree (or spanning tree). The rest of e edges are recorded as e Links of e graph. 3) For e above obtained DFS tree, calculate e oents for each node. Note at e node capacitance for e tree nodes is e sae as e node capacitance of e original (non-tree) circuit. The first oents for e Tree-circuit were calculated using siple pa traversal procedure. The oents obtained for each node of e DFS tree are en updated by adding one link at a tie. The first oent is updated directly using equation (5). The second oents are coputed using bo Meod and Meod as explained above. 4) The basic algori for WED is as follows: Calculate r = /^ Use a look-up table to find θ fro log0(r) Use a look-up table to obtain Γ( + θ) fro θ Let β = -/( Γ( + θ)) The 50% delay td = β(ln)^ θ 5) The Look-up table for finding θ was taken directly fro [], while at for obtaining Γ(+ θ) was generated using MATLAB. First e WED algori was tested for Tree circuits and en was used for Non-tree circuits. In e exaples below, circuit, are fro e hoework probles and e results show at e delay obtained using e WED eod is wiin acceptable range of e spice results. Circuits 3-6 are arbitrarily chosen non-tree topology circuits. PDF created wi pdffactory trial version 8

9 5: esults Here we show e actual C circuits instead of e interconnect geoetry. ) Circuit : Tree Topology Node Spice WED % error.9769e e e e e e e e-8.4 ) Circuit : Tree Topology Node Spice WED % error 3.966e e e e e e e e e e PDF created wi pdffactory trial version

10 3) Circuit 3: Non-tree, Links : (-5) Node Spice Progra % error Progra %error e e e e e e e e e e e e e e e e e e ) Circuit 4: Non-Tree, Links: (-3) Node Spice Progra % error Progra % error e e e e e e e-9.60e e e-9.943e e e e e e-9.34e e e-9.53e e PDF created wi pdffactory trial version 0

11 5) Circuit 5: Links (-4), (-5) Node Spice Progra % error Progra % error 6.308e e e e e e e e e e e e e e e e e e e e e-0.5 6) Circuit 6: Links (-4),(-5), (6-9) Node Spice Progra % error Progra % error.0384e e e e e e e e e PDF created wi pdffactory trial version

12 5.0965e e e e e e e e e e e e e e e e e e : Suary and Conclusion Fro e results it is clear at e delay coputation using Meod have really high percentage error. Meod gives considerably accurate results except of a couple of cases which can be ought of as outliers. Thus we can safely conclude at Meod should be used for higher order oent calculation using e Tree-Link Partitioning algori. In suary second-order delay for C-non tree circuits can be obtained using e Tree-link Partitioning Algori along wi e Weibull based delay approxiation wi quite good accuracy. The coputation tie is considerably low since we do a siple pa tracing for oent calculation and use look-up tables for delay calculation. This is a huge saving as copared to e odel-order reduction techniques at requires non-linear solution eods and ay run into stability issues. eference: [] Paul Penfield and Jorge ubinstein, Signal Delay in C Tree Networks, IEEE Trans. on Coputer- Aided Design, CAD-, (July 983), pp. 0-. [] L. Pileggi, Tiing Metrics for Physical Design of Deep Sub Micron Technologies, Int l Syposiu on Physical Design, April 998 [3] L. T. Pillage and.a. ohrer, Asyptotic Wavefor Evaluation for Tiing Analysis, IEEE Transactions on Coputer Aided Design, 9(4), pp , 990. [4] K. J. Kerns, I. L. Weple, A. T. Yang, Stable and Efficient eduction of Substrate Model Network using Congruence Transforation, ICCAD, Nov [5] B. Tutuianu, F. Dartu and L. Pileggi, An Explicit C-Circuit Delay Approxiation Based on e First Three Moents of e Ipulse esponse, Proc. ACM/IEEE Design Autoation Conf., 996. [6] ony Kay and Lawrence Pileggi, PIMO: Probability Interpretation of Moents for Delay Calculation, Proc. IEEE/ACM Design Autoation Conference, 998 [7] Tao-Lin, Erah Acar, L. Pileggi, h-gaa: An C Delay Metric Based on a Gaa Distribution Approxiation of e Hoogeneous esponse, Proc. IEEE Transactions on Coputer-Aided Design, 6:507-54, Deceber 997 [8] Pak K. Chan and Martine Schlag, Bounds on Signal Delay in C Mesh Network, Proc. IEEE Transactions on Coputer-Aided Design, Vol 8. No. 6, June 989 PDF created wi pdffactory trial version

13 [9] Pak K. Chan and Kevin Karplus, Coputing Signal Delay in General C networks by Tree/Link Partitioning, Proc. IEEE Transactions on Coputer-Aided Design, Vol 9. No. 8, June 990 [0] Lin, Tzu-Mu and Mead, Carver A. (983) Signal Delay in General C Networks wi Application to Tiing Siulation of Digital Integrated Circuits. []. Gupta, B. Tutuianu and L. Pileggi, The Elore Delay as a Bound for C Trees Generalized input signals Proc. IEEE Transactions on Coputer-Aided Design, Vol 6. No., June 997 [] F. Liu, C. V. Kashyap and C. J. Alpert, A Delay Metric for C Circuits Based on e Weibull Distribution, ICCAD 00 PDF created wi pdffactory trial version 3