Extension and VLSI Implementation of the Majority-Gate Algorithm for Gray-Scale Morphological Operations

Transcription

1 Extension and VLSI Implementation of the Majority-Gate Algorithm for Gray-Scale Morphological Operations A Gasteratos, I Andreadis and Ph Tsalides Laboratory of Electronics Section of Electronics and Information Systems Technology Department of Electrical and Computer Engineering Democritus University of Thrace Xanthi, Greece ioannis@orfeaseeduthgr Abstract : This paper presents the design and VLSI implementation of a new ASIC which performs in real-time the morphological operations of dilation and erosion The ASIC's architecture is based on the extension of the majority-gate algorithm for morphological operations The ASIC was implemented using a DLM, 07 ìm, CMOS, N-well process and it occupies a silicon area of 1478mm 2 Its maximum speed of operation is 925 MHz Targeted applications include machine vision applications, where the need for short processing times is crucial Subject terms : image processing, mathematical morphology, majoritygate, ASICs

2 1 Introduction Mathematical morphology is a methodology for image processing which is based on set theory and topology [1, 2] It offers a unified approach to many computer vision problems, such as noise removal, feature extraction, skeletonizing etc The two basic morphological operations are dilation and erosion, from which all the other morphological operators are extracted Morphological operators can decompose complex shapes into more meaningful representations and separate them from the undesirable parts The techniques of mathematical morphology have been also described within the context of overall image algebra [3, 4] This approach provides readily understood algorithms that fit to the structure of the universal image processing techniques In mathematical morphology pivotal role plays the structuring element, ie an image, normally smaller than the image under process, which is sequentially translated through the image and it is convolved with the region it overlays Various structuring elements are used to perform mathematical morphology operations and they are primarily dependent on the image pixel conductivity A technique for the decomposition of gray-scale structuring elements has been proposed in [5] Using this technique, smaller size structuring elements are applied to images sequentially The final effect is similar to that of a larger structuring element This is very useful when the size of the structuring element is limited by the architecture of the processing machine Pipeline architectures for the implementation of the basic morphological transformation are described in [6] However, these structures are rather slow when implemented using conventional comparators The threshold decomposition technique significantly increases the execution speed [7, 8] 2

3 Through this technique, gray-scale morphological operations are decomposed into binary operations with the same dimensionality as the original operations The main drawback of this technique is its demand on hardware, when the number of gray-levels of the image and the structuring element increases Another approach for the implementation of gray-scale morphological operations has been recently proposed [9, 10] This is based on the majority-gate algorithm and it has been originally used for median filtering [11] In this technique hardware complexity expands linearly according to the number of the image gray-levels This paper presents, for the first time, the design and VLSI implementation of a new ASIC, suitable to perform in real-time the operations of dilation and erosion on gray-scale images The maximum/minimum operator needed to compute these operations is based on the extension of the majority-gate algorithm The redundancy of temporal signals has been proven and this has led to a simpler implementation of the Processing Elements (PEs) Additionally, it has been shown that there is no need for different PEs to calculate max/min operators The proposed ASIC can handle 3 x 3 pixels data windows of 8-bit resolution for both image and structuring element The ASIC's architecture is easily scalable, regarding both the image size and the image resolution Its frequency of operation is 925 MHz (worst case) and its throughput rate of operations is 1110 MIPS The die size dimensions for the chip are 376mm x 393mm = 1478mm 2, for a DLM, 07 ìm, CMOS, N-well technology process The ASIC is intended to be used in time critical applications Real-time techniques are important not only in terms of improving productivity, but also in reducing operator errors associated with visual feedback delays 2 Gray-scale Morphology 3

4 The concepts of binary morphology have been applied to gray-scale images by Sternberg [12] In terms of gray-scale morphology dilation is given by : ( f k )( x,y) = max { f ( x - i, y - j ) + k ( i, j)} where f : F ( i, j ) K ( x, y ) ( i, j ) F (1) E is the image under process and k : K E is the structuring element, E is the Euclidean space of dimension 1 and F, K E E Similarly, erosion is given by : ( f È k )( x, y ) = min { f ( x + i, y +j ) k ( i, j )} ( i, j ) K (2) These formulas are suitable for VLSI implementation The number of additions/subtractions is equal to the size of the structuring element, ie i x j All these operations can be executed in parallel Also, a local max/min operator is required 3 The Extension of the Majority-gate Algorithm The majority-gate algorithm is a bit-sliced algorithm, in which the bits of each addition/subtraction results [eqns (1) and (2)] are processed by dedicated PEs in different stages of a pipeline machine Suppose that there are n numbers whose the maximum (or the minimum) is required In the first stage of the process the most significant bits (MSBs) of these numbers are processed The numbers whose MSBs are "1" (or "0") are candidates to be the maximum (or the minimum) Thus, the MSB of the required maximum (or the minimum) number is "1" ( or "0") All the other numbers are rejected and are not taken into consideration in the next stages of the process The flag signal f classifies the numbers into two categories More specifically, if f ="1" then the number is a candidate for the next stage of the process, otherwise the number is excluded from the process 4

5 If all of the MSBs are "0" (or "1") then all of them are candidates to be the maximum (or the minimum) and the MSB of the result is "0" (or "1") The procedure is repeated in the next stage for the lower order bits of the numbers which remain candidates Let m be the output signal of the max/min operator and n the window size of the operator Then, the operator has n inputs b i Also, o j representation of m is the j th bit of the binary It has been shown that [9] : o j = (t 1,j ) OR (t 2,j ) OR OR (t n,j ) for the max operator and (3) oj = (t 1,j ) AND (t 2,j ) AND AND (t n,j ) for the min operator (4) where t i,j is a temporal signal defined as: t i,j = (f i,j ) AND (b i,j ) for the max operator and (5) t i,j = (f i,j ) OR (b i,j ) for the min operator (6) and f i,j is the flag signal indicating whether b i remains within the set of the maxima or the minima : f i,j +1 = (f i,j ) AND [(ti,j ) XNOR (o j )] for the max operator and (7) f i,j +1 = (f i,j ) OR [(t i,j ) XOR (o j )] for the min operator (8) Thus, the implementation of max/min operators (based on the above eqns) requires two different PEs As it will be shown in this paper a single circuit can execute both operations The redundancy of the temporal signals is also shown By substituting eqn (5) into eqn (7) and using Boolean algebra laws : f i,j+1 = (f i,j ) AND {[(f i,j ) AND (bi,j )] XNOR (o j )} 5

6 = (f i,j ) AND[{[( fi,j )AND( bi,j ) ] AND (o j )} OR {[(f i,j ) AND (b i,j )] AND (o j )}] = (f i,j ) AND {[(f i,j ) OR (b i,j )] AND (o j ) OR [(f i,j ) AND (b i,j ) AND (o j )]} = (f i,j ) AND{[(f i,j ) AND(o j )] OR[(b i,j ) AND(o j )] OR[(fi,j ) AND(bi,j)AND(oj )]} = [(fi,j ) AND (b i,j ) AND (o j )] OR [(f i,j ) AND (b i,j ) AND (o j )] = (fi,j ) AND {[(b i,j ) AND (o j )] OR [(b i,j ) AND (o j )]} = (f i,j ) AND [(b i,j ) XNOR (o j )] for the max operator (9) Similarly it can be shown that : f i,j+1 =(f i,j ) OR [(b i,j ) XOR (o j )] for the min operator (10) Furthermore, substituting eqn (5) into eqn (3) : o j =[(b 1,j ) AND (f 1,j )] OR [(b 2,j ) AND (f 2,j )] OR OR [(b n,j ) AND (f n,j )] (11) Also, eqns (9) and (10) can be rewritten as follows : f i,j =(f i,j -1 ) AND [(b i,j -1 ) XNOR (o j-1 )] (12) f i,j =(f i,j -1 ) OR [(b i,j -1 ) XOR (o j-1 )] (13) for the max operator for the min operator and by substituting eqn (12) into eqn (11) : o j =[(b 1,j ) AND {(f 1,j -1 ) AND [(b 1,j -1 ) XNOR (o 0 )]}] OR [(b 2,j ) AND {(f 2,j -1 ) AND [(b 2,j -1 ) XNOR (o 1 )]}] OR OR [(b n,j ) AND {(f n,j -1 ) AND [(b n,j -1 ) XNOR (o n-1 )]}] (14) Similarly, using eqns (4), (6) and (14) it can be shown that : 6

7 o j =[(b 1,j ) OR {(f 1,j -1 ) OR [(b 1,j -1 ) XOR (o 0 )]}] AND [(b 2,j ) OR {(f 2,j -1 ) OR [(b 2,j -1 ) XOR (o 1 )]}] AND AND [(b n,j ) OR {(f n,j -1 ) OR [(b n,j -1 ) XOR (o n-1 )]}] (15) and by applying De Morgan's law on eqn (14) : o j =[(b 1, j ) AND {(f 1,j -1 ) AND [(b 1, j-1 ) XNOR (o 0 )]}] OR [(b 2, j ) AND {(f 2,j -1 ) AND [(b 2, j-1 ) XNOR (o 1 )]}] OR OR [(b n, j ) AND {(f n,j-1 ) AND [(b n, j-1 ) XNOR (o n-1 )]}] (16) From eqns (9) and (14) it is clear that coefficients t i,j are not needed for the computation of f i,j + 1 and, therefore, a simpler hardware implementation can be achieved Also, eqns (14) and (16) show that there is no need for realization of different circuits in order to compute the max and the min operators The max operator circuit can be implemented using eqn (14), whereas the min operator circuit can be implemented by the same circuit, by simply inverting both the inputs and the outputs As an illustration, suppose that the minimum of n binary numbers is required If these numbers are complemented bit by bit, then the minimum becomes maximum and it can be traced by a max operator circuit By inverting the previous result the minimum is obtained 4 Circuit Description and VLSI Implementation of the Proposed Algorithm The block diagram of the circuit of the proposed ASIC is shown in Figure 1 The pipeline technique has been adopted, since this allows complex operations to be performed in one clock cycle The input data is a 3 x 3 pixel image window or an up to 3 x 3 pixel structuring element, each having 7

8 a gray-scale resolution of up to 8 bits This size and gray-scale resolution of the structuring element is suitable to most image processing morphological applications Data is latched in the first stage of the pipeline by means of eighteen eightbit latches (L1) The first nine latches hold the image data, whereas the other nine latches hold the structuring element Signal INIT, shown in Figure 1, controls two arrays of three state buffers (TSBs) and it is used to load the structuring element Since one structuring element is used to process the image, it is loaded once, at the beginning of the process, and it is held by means of feedback registers, as it is depicted in Figure 1 When INIT="1", data is loaded to the latches and the feedback path is in the third state In this way data conflict is avoided Similarly, when INIT="0", the input TSBs are in the third state and data follows the feedback path Global signal MODE is used to select the operation When this is "1" dilation is performed, whereas "0" selects the erosion operation Eqns (1) and (2) show that in dilation operation the reflection of the structuring element, with respect to the origin, interacts with the image window, whereas in erosion operation it interacts exactly with the image pixels it overlays Image data is collected by 9 multiplexers MUX, which are controlled by the signal MODE Data paths for both dilation and erosion are shown in Figure 2 In the same stage the pixels of structuring element remain either unchanged for the operation of dilation or they are complemented for the operation of erosion, by means of XNOR gates controlled by the signal MODE XNOR gates are used in this circuit, instead of XOR gates, since they exhibit smaller propagation delay In the next stage of the pipeline, data is fed to nine eight-bit adders In the case of erosion the 1's complements of the pixels of the structuring element are added to the image data and the carry in (C in ) bit to the adder is "1" Thus, 8

9 the 2's complements of the pixels of the structuring element are added to the image pixels This is equivalent to the subtraction operation The next stages of the pipeline implement the max/min operation on the results of the additions/subtractions, in order to complete the dilation/erosion operations This circuit consists of nine cascaded max/min PEs Figure 3 shows the implementation of the PE based on eqns (14) and (16) In order to compute the min values (erosion), b i,j and b i,j - 1 are inverted by means of XNOR gates, controlled by MODE signal However, there is no need to invert f i,j - 1, since they are obtained inverted from the previous PE This can be seen by applying De Morgan's law to eqn (12) and comparing the result with eqn (13) The initial conditions for the max/min circuit are: f i,1 ="1", b 0 ="1", o 0 = "1" for the dilation operation and f i,1 ="0", b 0 ="0", o 0 = "0" for the erosion operation These conditions are provided by signal MODE The first PE processes the MSB and determines, by inverting the flags of the other results, which of the addition or subtraction results remain within the set of maxima or minima The set of the flags is collected by the nine-bit latch L**4 At the same time the MSB of the maximum or minimum number o 1 is obtained and it is collected by latch L*4 In the following stages the consequent bits are processed and in the last stage the max/min number is computed There is no need to carry in the remaining stages all the b i,j coefficients and, therefore, those which have been processed are rejected Thus, the resolution of latches L5 to L11 is reduced by one bit in each stage, whereas the resolution of latches L*5 to L*12 is increased, in order to hold the result The result either of the dilation operation or the erosion operation may be outside the range of 8-bit, ie [0255] More specifically, the dilation result 9

10 may be greater than 255 and the erosion result may be negative These cases can be easily detected by testing the MSB of the result In the case of dilation if the result is less than 255 then its MSB is "0", otherwise its MSB is "1" In the case of erosion the MSB presents the sign of the result, which is either "1" or "0" for positive or negative numbers, respectively (a negative result is presented in 2's complement form) Therefore, in order to ensure that the result o is limited to the range [0255], it is clipped in such a way that o=255 if o > 255 or o=0 if o < 0 Clipping can be implemented by a digital circuit, which tests the MSB and produces a constant value, which is either "255" or "0", in the case of dilation or erosion, respectively However, if an application demands the result not to be clipped, an ASIC of 9-bit resolution can be used Such a device can be easily constructed as the proposed architecture is scalable The complexity of the above described hardware structure grows linearly with the resolution of the input data Thus, for an ASIC of N-bit resolution, N-bit latches (L1, L2) and N- bit multiplexers and adders are required Latches L3 have a (N+1)-bit resolution and the PEs of the max/min circuit are (N+1)-bit A block level layout of the ASIC, including the pads, is shown in Figure 4 The dimensions for the core of the chip are 287mm x 305mm = 848mm 2 and the die size dimensions for the chip are 377mm x 393 mm = 1478mm 2 The inputs to the ASIC are the 3 x 3 image window of 8-bit resolution, the clock, MODE and INIT signals, the power and ground connections, whereas the output is the 9-bit new image pixel value The hardware demand of the proposed technique compares favorably to the threshold decomposition technique Table 1 shows the number of standard cells required by the threshold decomposition and the majority-gate technique, for a 3 x 3 image data window From this Table it becomes clear that the majority-gate is advantageous in terms of silicon area 10

11 The simulation and test language STL, a high level language, has been used to examine the functionality of the ASIC The maximum frequency of operation (worst case) is 925 MHz and it's internal computational rate of operations is 925 x 12 = 1110 MIPS The high speed of operation of this ASIC has been achieved by pipelining the data 5 Conclusions The design and VLSI implementation of a new ASIC which performs the morphological operations of gray-scale dilation and erosion, based on the extension of the majority gate algorithm was presented in this paper It can handle 3 x 3 image windows of up to 8-bit resolution Its frequency of operation is 925 MHz (worst case) and its internal computational rate is 1110 MIPS Targeted applications include industrial pattern recognition applications, robotics, and military systems Most of these applications are generally characterized by data throughput requirements that can only be met by dedicated hardware capable of operating in real-time With a DLM, 07 ìm, CMOS, N-well technology process the die size dimensions for the chip are 376 x 393 mm = 1478 mm2 REFERENCES 1 J Serra, Image Analysis and Mathematical Morphology, Vol I, Academic Press, London (1982) 2 R M Haralick and L G Shapiro, Computer and Robot Vision, Vol I, Addison-Wesley, N York (1992) 3 E R Dougherty and D Sinha, "Computational Gray-Scale Mathematical Morphology on Lattices (A Comparator-based Algebra)-Part I : Architecture", Real-Time Imag, 1 (1), (1995) 11

12 4 E R Dougherty and D Sinha, "Computational Gray-Scale Mathematical Morphology on Lattices (A Comparator-based Algebra)-Part II : Image Operators", Real-Time Imag, 1 (4), (1995) 5 F Y Shih and O R Mitchell, "Decomposition of Gray-Scale Morphological Structuring Elements", Pattern Recognition, 24 (3), (1991) 6 L Abbott, R M Haralick and X Zhuang, "Pipeline Architectures for Morphologic Image Analysis", Machine Vision and Applications, 1 (1), (1988) 7 F Y Shih, and O R Mitchell, "Threshold Decomposition of Gray- Scale Morphology into Binary Morphology", IEEE Trans Pattern Analysis and Machine Intelligence, 11 (1), (1989) 8 I Andreadis, A Gasteratos and Ph Tsalides, "An ASIC for Fast Grey Scale Dilation" Microprocessors and Microsystems, 20 (2),89-95 (1996) 9 C Chen and D L Yang, "Realisation of Morphological Operations" IEE Proc-Circuits Devices Syst, 142 (6), (1995) 10 A Gasteratos, I Andreadis and Ph Tsalides, "Improvement of the Majority Gate Algorithm for Grey Scale Dilation/Erosion" Electronics Letters, 32 (9), (1996) 11 C L Lee and C W Jen, "Bit-Sliced Median Filter Design Based on Majority Gate", IEE Proc-G, 139 (1), (1992) 12 S R Sternberg, "Grayscale Morphology" Computer Vision, Graphics and Image Processing, 35 (3) (1986) FIGURE CAPTIONS 12

13 Figure 1 Block diagram of the dilation and erosion computation circuit Figure 2 Data paths for : (a) Dilation and (b) Erosion Figure 3 Max/min PE for a 3x3 image window data Figure 4 Layout of the ASIC 13

14 pi : image, or structuring element data p1 L1 MUX L2 Adder L3 L4 L11 p2 L1 MUX L2 Adder L3 L4 L11 p9 TSBs L1 L1 MUX XNORs L2 L2 Adder C in L3 b f 0 0 b1 PE f 1 L4 L**4 L11 L**11 b 8 b 9 PE L1 XNORs L2 o 1 L*4 o 0 o 8 L*11 o 9 L*12 m L1 XNORs L2 INIT MODE F/F F/F F/F F/F F/F MAX/MIN CIRCUIT Figure 1 14

15 stucturing element image window (a) (b) Figure 2 15

16 oj -1 MAX/MIN bj -1<0> fj -1<0> bj <0> bj -1<8> fj-1<8> bj<8> oj fj<0> fj <8> Figure 3 16

17 Figure 4 17

18 Threshold Decompositio n (sc * ) Majority- Gate (sc * ) 4-bit 3, bit 674,500 1,200 *sc : standard cells Table 1 Hardware considerations for the threshold decomposition and the majority-gate techniques using 3 x 3 image windows 18

19 Antonios Gasteratos received the Diploma Degree from the Department of Electrical and Computer Engineering, Democritus University of Thrace, Greece, in 1994 He is currently a PhD candidate in the Department of Electrical and Computer Engineering, Democritus University of Thrace, Greece His research interests are mainly in mathematical morphology, parallel architectures and VLSI image processing He is a member of the Technical Chamber of Greece (TEE) Ioannis Andreadis received the Diploma Degree from the Department of Electrical Engineering, Democritus University of Thrace, Greece, in 1983, and the MSc and PhD degrees from the University of Manchester Institute of Science and Technology (UMIST), UK, in 1985 and 1989, respectively His research interests are mainly in machine vision and VLSI based computing architectures for machine vision He joined the Department of Electrical and Computer Engineering, Democritus University of Thrace, Greece, in 1992 He is a member of the Technical Chamber of Greece (TEE) and the IEEE Philippos Tsalides was born in Mirina Limnou, Greece, on October 14th 1953 He received the Diploma Degree from the University of Padova, Italy, in 1979 and the PhD degree from Democritus University of Thrace, Greece, in 1985 He is the Professor of Applied Electronics in the Department of Electrical and Computer Engineering, Democritus University of Thrace, Greece His current research interests include VLSI architectures, VLSI systems, BIST Techniques, Applications of Cellular Automata in Image Processing, as well as in Computational Systems He has published a number of papers and a Textbook on VLSI Systems (Basic Principles of Design and Fabrication) He is a fellow member of the IEE and a member of the Technical Chamber of Greece (TEE) 19