ISSCC 2003 / SESSION 2 / MULTIMEDIA SIGNAL PROCESSING / PAPER 2.6

Transcription

1 ISSCC 2003 / SESSION 2 / MULTIMEDIA SIGNAL PROCESSING / PAPER A 51.2GOPS Scalable Video Recognition Processor for Intelligent Cruise Control Based on a Linear Array of Way VLIW Processing Elements Shorin Kyo, Takuya Koga, Shin ichiro Okazaki, Ryoichi Uchida, Satoshi Yoshimoto, Ichiro Kuroda NEC, Kawasaki, Japan Video recognition for intelligent cruise control (ICC) and other intelligent transport system (ITS) applications requires not only high computation performance but also high programmability. This is due to the necessity of using various recognition algorithms to cope with changing situations, sizes, and appearances of target objects such as vehicles, lane marks and obstacles. Existing microprocessors and DSPs provide high programmability but fail to offer enough performance because insufficient architectural support exists for the required pixel parallelism and non-continuous memory access. Dedicated ASICs[1] and configurable devices[2] have to devote die spaces to each recognition algorithm for each exclusively existing situation such as driving on highways versus local streets, or stop-and-go versus normal cruise. An integrated memory array processor for car electronics (IMAP-CE) provides both high performance and programmability for ICC applications is characterized by the following. 1) Parallel execution by a multiple of 128 SIMD 4-way VLIW processing elements (PEs). 2) Parallel algorithm design is facilitated by a linear PE connection and the ability of simultaneous access of data located in different memory address by each PE (indexed addressing). 3) Automatic background video data mapping for each PE is acheived by an asynchronous shift register (SR) structure. 4) An optimizing extended C compiler generates fully efficient codes. Figure shows the IMAP-CE containing a 16b RISC control processor (CP), a linear processor array (LPA) of 128 RISC type 8b PEs, and an interface unit. Each PE executes up to 4 instructions per clock cycle to provide a peak performance of 51.2 GOPS in a single chip, or up to GOPS in a cascade connected 16-chip configuration at 100MHz. CP issues up to 4 instructions per clock cycle, within which one is decoded for the CP, and as many as 4 are decoded and broadcast to the LPA. To facilitate instruction/data broadcast from the CP, the LPA is hierarchically consisted of 16 PE groups (PEG), where each PEG further consists of 8 linearly connected PEs. A 64b line buffer of each PEG is mutually connected in a SR configuration for burst transfer of data between the off-chip SDRAM and PE RAM blocks. Figure shows the CP (6-stage) and PE (3-stage) pipelines bridged by the instruction broadcast (BC1), CP data broadcast (BC2), and PE data reduction (RDU: extract an 8b data out of 8bx128, or produce an 1b status by wired ORing 1bx128) pipes. The cascade connection of multiple chips to form a larger LPA is supported for extra performance requirements. In Fig , the inter-pe data path is pulled out as pins, and an inter-pe data selector is used for selecting between the looped back PE data of the chip, and PE data from adjacent chips. In Fig , additional selector logics of the RDU pipe are used for selecting PE status/data from other chips supplied by a 1bx16/16bx1 configurable bus (CPDATA). Figure shows that, in the 1bx16 mode, each chip sends its own 1b status to all the other chips by using a separate 1b of CPDATA and uses the remaining 15b to receive data from the other chips. In the 16bx1 mode the particular chip possessing the requested PE data drives all bits of CPDATA to broadcast the data to all other chips. A combination of the LPA configuration with the indexed addressing capability, which is enabled by assigning each PE a separate RAM block, are shown to provide a base for parallel implementation of various image processing tasks [3]. This is unachievable by a conventional SIMD stream instruction design such as the Intel MMX/SSE instruction set, due to the parallelism being restricted only to continuously located memory data. Automatic background video data mapping is achieved by assigning a mutually connected SR, comprised of 4-sub-SRs, to each PE. The inter-connection between the 4x8b sub-srs is configurable into any of the 4 modes shown in Fig This enables mapping of up to 4 columns of video data to each PE, in case the horizontal pixel number of the video data exceeds the PE number. Whenever a video data line is shifted in completely, an interrupt signal is generated by the CP s video-interrupt-generator. The interrupt signal in turn invokes a software interrupt routine to run in the horizontal or vertical blank period of the video signal. During this time the video clock used for driving the sub-sr flip-flops (FFs) is shut off and ensures collision free asynchronous access to the sub- SRs by the PEs within the interrupt routine. A parallel data structure extended C language, called one dimensional C (1DC) is developed [3] to provide high programmability. As each PE is designed as a RISC processor with 24 general purpose registers, conventional compile techniques are fully adopted for creating an efficient optimizing 1DC compiler. A significant feature of the compiler is the virtualization of number of PE and video data mapping, by which source code modification is not required even if the number of chips or the video data mapping of a target system changes. The IMAP-CE is fabricated using 0.18µm 7M CMOS process and the 11x11mm 2 die contains 32.7M transistors. Figure summarizes the LSI features, and Fig shows the die micrograph. The evaluation of the image filters.in Fig shows that the IMAP-CE runs 3 to 50 times faster than a 2.8 GHz general-purpose processor. Figure also shows a 33ms/frame performance using a single chip IMAP-CE running the 1DC written ICC application of lane marking, road area, and vehicle detection, in which various complicated algorithms are combined for obtaining robust recognition results under bad weather conditions[4]. The results demonstrate the potential of IMAP-CE as a device solution for various timing-crucial ICC applications. References [1] M. Hariyama, et al., "VLSI Processor for Reliable Stereo Matching Based on Adaptive Window-Size Selection, IEEE Int. Conf. on Robotics and Automation, vol. 2, pp , May, [2] Y. Kondo, et al., "4 GOPS 3 way-vliw image recognition processor based on a configurable media-processor, ISSCC Digest of Technical Papers, pp , [3] S. Kyo, et al., "Efficient Implementation of Image Processing Algorithms on Linear Processor Arrays using the Data Parallel Language 1DC, IAPR Workshop on Machine Vision and Applications, pp , [4] S. Kyo, et al., "A Robust Vehicle Detecting and Tracking System for Wet Weather Conditions using the IMAP-VISION Image Processing Board, IEEE/IEEJ/JSAI Int. Conf. on Intelligent Transportation System, pp , 1999.

2 ISSCC 2003 / February 19, 2003 / Salon 1-6 / 4:15 PM 2 Figure 2.6.1: Processor block diagram. Figure 2.6.2: CP and LPA pipeline structure. Figure 2.6.3: CPDATA bus configuration. Figure 2.6.4: The four possible sub-sr inter-connections. Figure 2.6.5: Performance comparison results. Figure 2.6.6: Chip specifications.

3 2 Figure 2.6.7: Die micrograph.

4 Figure 2.6.1: Processor block diagram.

5 Figure 2.6.2: CP and LPA pipeline structure.

6 Figure 2.6.3: CPDATA bus configuration.

7 Figure 2.6.4: The four possible sub-sr inter-connections.

8 Figure 2.6.5: Performance comparison results.

9 Figure 2.6.6: Chip specifications.

10 Figure 2.6.7: Die micrograph.