NAR-5510 Series Communication Appliance. User s Manual. Revision: 0.1

Transcription

1 NAR-5510 Series Communication Appliance User s Manual Revision: 0.1 CE This certificate of conformity of NAR-5500 series with actual required safety standards in accordance with 89/366 ECC-EMC Directive and LVD 73/23 ECC UL This product meets all safety requirements per UL60950 standard. Portwell Inc. 3F, No. 92, Sec. 1, Nei-Hu Rd., Taipei 114, Taiwan, R.O.C. Headquarter: FAX: info@mail.portwell.com.tw

2 Table of Contents Chapter 1 Introduction About This Manual Manual Organization Technical Support Information...2 Chapter 2 Getting Started Included Hardware Before You Begin The Chassis Open the Chassis Remove and Install DIMM Remove and Install Compact Flash Card Remove and Install Battery Install HDD Ear Mount Kit Installation Product Specifications Hardware Configuration Setting Install a Different Processor Use a Client Computer BIOS Setup Information Reset to Default Information ByPass & WDT Programming Guide About EZIO Features Technical Support Information Mechanical Specification General Specification Product Outlook Interface Pin Assignment Hardware installation EZIO Function Command Character Generator ROM (CGROM) Sample Codes GPIO Sample Code...63 Chapter 3 Operation Guide Brief Guide of NAR-5510 System Board System Architecture...66 Appendixes A NAR-5510 Series CPLD Upgrade Procedure...67 Appendixes B Bypass and WDT Sample Code (C Language)...71 NAR-5510 SeriesUser s Manual 1

3 Chapter 1 Introduction 1.1 About This Manual This manual contains all required information for setting up and using the NAR-5510 series. NAR-5510 provides the essential platform for delivering optimal performance and functionality in the value communications appliance market segment. This manual should familiarize you with NAR-5510 operations and functions. NAR-5510 series provide up to eight on-board Ethernet ports to serve communication applications like Firewall, requiring eight Ethernet ports to connect external network (internet), demilitarized zone and internal network. Feature of NAR-5510 series includes: Versatile networking and I/O capabilities: 6 Ethernet ports Four PCI-Express Gigabits Ethernet (Intel 82541PI) Two USB ports and two COM ports Two PCI 32bit/33MHz Gigabits Ethernet (Intel 82541PI) Up to 2GB DDR400 on 2 x 184-pin DIMM sockets. Three SATA connectors for SATA HDD User-friendly LCD control panel 1.2 Manual Organization This manual describes how to configure your NAR-5510 system to meet various operating requirements. It is divided into three chapters, with each chapter addressing the basic concept and operation of this system. Chapter 1: Chapter 2: Chapter 3: Introduction. This section describes how this document is organized. It includes brief guidelines and overview to help find necessary information. Hardware Configuration Setting and Installation. This chapter demonstrated the hardware assembly procedure, including detailed information. It shows the definitions and locations of Jumpers and Connectors that can be used to configure the system. Descriptions on how to properly mount the CPU and main memory are also included to help perform a safe installation. This chapter will provide detailed instruction on how to set up NAR-5510 series. Operation Information. This section provides illustrations and information on the system architecture and how to optimize its performance. Any updates to this manual, technical clarification and answers to frequently asked questions would be posted on the web site: Technical Support Information Users may find helpful tips or related information on Portwell's web site: A direct contact to Portwell's technical person is also available. For further support, users may also contactportwel sheadquarter in Taipei or local distributors. Taipei Office Phone Number: NAR-5510 SeriesUser s Manual 2

4 Chapter 2 Getting Started This section describes how the hardware installation and system settings should be done. The following hardware is included in package: 2.1 Included Hardware NAR-5510 Communication Appliance System Board One null serial port cable 2.2 Before You Begin To prevent damage to any system board, it is important to handle it with care. The following measures are generally sufficient to protect your equipment from static electricity discharge: When handling the board, use a grounded wrist strap designed for static discharge elimination and touch a grounded metal object before removing the board from the antistatic bag. Handle the board by its edges only; do not touch its components, peripheral chips, memory modules or gold contacts. When handling processor chips or memory modules, avoid touching their pins or gold edge fingers. Restore the communications appliance system board and peripherals back into the antistatic bag when they are not in use or not installed in the chassis. Some circuitry on the system board can continue operating even though the power is switched off. Under no circumstances should the Lithium battery cell used to power the real-time clock be allowed to be shorted. The battery cell may heat up under these conditions and present a burn hazard. WARNING! 1. "CAUTION: DANGER OF EXPLOSION IF BATTERY IS INCORRECTLY REPLACED. REPLACE ONLY WITH SAME OR EQUIVALENT TYPE RECOMMENDED BY THE MANUFACTURER. DISCARD USED BATTERIES ACCORDING TO THE MANUFACTURER S INSTRUCTIONS" 2. This guide is for technically qualified personnel who have experience installing and configuring system boards. Disconnect the system board power supply from its power source before you connect/disconnect cables or install/remove any system board components. Failure to do this can result in personnel injury or equipment damage. 3. Avoid short-circuiting the lithium battery; this can cause it to superheat and cause burns if touched. 4. Do not operate the processor without a thermal solution. Damage to the processor can occur in seconds. 5. Do not block air vents. Minimum 1/2-inch clearance required. NAR-5510 SeriesUser s Manual 3

5 2.3 The Chassis The system is integrated in a customized 1U chassis (Fig. 2-1, Fig. 2-2). On the front panel you will find a 4-push-button LCD module (EZIO), right LAN ports, two USB ports and a COM port. Fig. 2-1 Front view of the chassis NAR / NAR-5510B-810 Fig. 2-2 Rear view of the chassis 2.4 Open the Chassis 1. Loosen the eight screws of the chassis, three on each side and the rest two on the back, to remove the top lead (Fig. 2-3). Fig. 2-3 Take off screws NAR-5510 SeriesUser s Manual 4

6 2. The top lead (Fig. 2-4) can be removed from the base stand (Fig. 2-5). Fig. 2-4 The top lead Fig. 2-5 The base stand Follow these steps to upgrade RAM module: 2.5 Remove and Install DIMM 1. Unlock a DIMM socket by pressing the retaining clips outward 2. Align a DIMM on the socket such that the notch on the DIMM matches the break on the socket NAR-5510 SeriesUser s Manual 5

7 3. Firmly insert the DIMM into the socket until the retaining clips snap back in place and the DIMM is properly seated Follow these steps to remove a DIMM: 1. Simultaneously press the retaining clips outward to unlock the DIMM 2. Remove the DIMM from the socket 2.6 Remove and Install Compact Flash Card 1. Insert the Compact Flash Card (Fig. 2-7) into the CF interface (Fig. 2-8). NAR-5510 SeriesUser s Manual 6

8 Fig. 2-6 Compact Flash Card Fig. 2-7 Insert Compact Flash Card into the CF interface 2. The completed installation of Compact Flash Card is shown as Fig Fig. 2-8 Completion of Compact Flash Card connection 2.7 Remove and Install Battery 1. Press the metal clip back to eject the button battery (Fig. 2-9). 2. Replace it with a new one by pressing the battery with fingertip to restore the battery (Fig. 2-10). Fig. 2-9 Eject the battery Fig Restore the battery 2.8 Install HDD NAR-5510 SeriesUser s Manual 7

9 The system has an internal drive bay for one 3.5" SATA hard disk drive. If the HDD is not preinstalled, you can install it by yourself. Follow the steps below to install the HDD: 1. Fasten the four screws to lock HDD and bracket together (Fig. 2-11a, 2-11b). Fig. 2-11aA 3.5 SATA HDD and the HDD bracket Fig. 2-11b Fix HDD to the bracket 2. Connect the IDE cable to HDD (Fig. 2-12). 3. Connect IDE cable to NAR-5500RB CPU Board (Fig. 2-13). Fig Connect HDD to NAR-5500RB M/B Fig Drive two screws back 2.9 Ear Mount Kit Installation The NAR-5510 series shipped with 2 ear mount kits. The following is the installation instruction of these ear mounts: 1. Take out the L shape ear mount kits. One ear mount fits on one side of the chassis, 2. Placing the side with four holes agonists the chassis and the side with two holes face outward. (Fig. 2-14) 3. Fasten four screws on each side (Fig. 2-14) NAR-5510 SeriesUser s Manual 8

10 Fig.2-14 Fasten the screws to the side 2.10 Product Specifications Model: Main Processor: BIOS: Main Memory: Chipset: IDE Interface: SATA Interface Serial Ports: USB Interface: Auxiliary I/O Interfaces: Power Input: PCI Slot: On-board Ethernet: Hardware Monitor: NAR-5510 series Intel LGA775 Pentium 4 processors up to 3.4GHz with 800 MHz FSB Award system BIOS with 512KB flash ROM to support DMI, PnP, APM function 2 x 184-pin DIMM sockets support DDR 400, up to 2G unbuffered Memory, w/o ECC. North Bridge: Intel 915GV South Bridge: Intel ICH6 (ICH6R for system with RAID 0,1) Two independent IDE channels for CF socket and 40-pin IDE connector. 40-pin IDE supports ATA100 or above Two groups of SATA connectors on board: (1) One SATA connector on board edge for direct-attach installation of a 3.5 SATA HDD. (2) Two vertical SATA connectors are provide the RAID 0/1 function from ICH6R Support two high-speed 16550C compatible UARTs with 16-byte T/R FIFOs Support LCD/Key pad module (Portwell proprietary) Support two USB2.0 ports for high speed I/O peripheral devices System reset switch, power okay LED and HDD LED interface Support one AC input jack (power requirement: 110V ~ 220V auto switch) One PCI slot for half-size PCI card (Model NAR-5510) Max bit GbE ports via Intel 82541PI with RJ PCI-Express GbE ports via 88E8053 with RJ-45. Support on-board hardware monitor for CPU fan x 1 Chassis fan x 3 System voltages: Vcore, 3.3V, +5V and +12V Environmental Operating Temperature: 0 C ~ 35 C NAR-5510 Requirements: SeriesUser s Manual 9

11 Requirements: Storage Temperature: -40 C ~ 80 C Relative Humidity: 5% ~ 95%, non-condensing Dimension: 16.9"(D) x 14."(W) x 1.75 (H) 2.11 Hardware Configuration Setting This section gives the definitions and shows the positions of jumpers, headers and connectors. All of the configuration jumpers on NAR-5510B CPU Board are in the proper position. The default settings set by factory are marked with a star ( ). Jumpers In general, jumpers on NAR-5510 system board are used to select options for certain features. Some of the jumpers are configurable for system enhancement. The others are for testing purpose only and should not be altered. To select any option, cover the jumper cap over (Short) or remove (NC) it from the jumper pins according to the following instructions. Here NC stands for Not Connected. Location of Jumpers NAR-5510 SeriesUser s Manual 10

12 Figure 2-15 Location of Jumpers Function of Jumpers CONNECTOR FUNCTION REMARK JP1 RTC Battery Setting JP2 GPIO J25 Power 5V/3.3V Selector JP5 Bypass CPLD update download port JP6/JP7 Bypass Default Mode Setting JP8 Watch Dog Timing Setting J1/2 System Fan J3/4 CPU Fan J5/6 System Fan J7 PCI slot J9 ATX 12V POWER CONNECTOR J10 ATX POWER CONNECTOR J11 VGA Port J12/13 System Fan NAR-5510 SeriesUser s Manual 11

13 CONNECTOR FUNCTION REMARK J14 DDR CHANNEL A J15 DDR CHANNEL B J16/17 AUX FAN J18 LPC DEBUG J19 CF Connector J20 SATA 1 J21 IDE slot J22/23 System Fan J24 PS/2 KEYBOARD MOUSE J25 GPIO J26 EZIO Power J27 COM 2 J29 USB 1/2 EXTERNAL CONNECTOR J32 Giga Ethernet LAN / PCI J33 Giga Ethernet LAN / PCI J34 Giga Ethernet LAN / PCI - E J35 Giga Ethernet LAN / PCI - E J41 CONSOLE (RJ45) J43 LAN J44 LAN J49 SATA slot 3 J50 SATA slot 2 J52 Front Panel Jumper Setting JP1: RTC battery setting 1-2(default): normal mode 2-3: clear mode. RTC data be clear JP2: GPIO J25 power 5V/3.3V selector 1-2: GPIO J25 power is 5V 2-3(default): GPIO J25 power is 3.3V JP6: LAN BP (Bypass) Power-On default mode setting 1-2(default): A normal, LED ON 4-5(default): B normal, LED ON 2-3: A bypass, LED OFF J43/J44 bypass 5-6: B bypass, LED OFF J34/J35 bypass JP7: BP(Bypass) Enable/Disable NAR-5510 SeriesUser s Manual 12

14 1-2: BP A disable 2-3: BP A enable (default) 4-5: BP B disable 5-6: BP B enable (default) JP8: Watch Dog Timing Enable/Disable 1-2:Watch Dog Timing enable (default) 2-3: Watch Dog Timing disable J24: PS/2 KEYBOARD MOUSE 6 KEY DATA 7 NP 8 GND 9 KEY VCC 10 KEY CLK 1 MOUSE DATA 2 NP 3 GND 4 MOUSE VCC 5 MOUSE CLK J25: GPIO 6 IO24 (3VSB) 7 IO27 (3VSB) 8 I30 (3V) 9 I31 (3V) 10 POWER 1 IO34 (3V) 2 IO33 (3V) 3 IO32 (3V) 4 IO28 (3VSB) 5 GND J41: CONSOLE (RJ45) 5 GND 6 RXD 7 DSR 8 CTS 1 RTS 2 DTR 3 TXD 4 GND J52: FORNT 2PWR LED+ 4PWR LED- 6PWR ON- 8PWR ON+ 10LDF- 12BP B LED+ 14BP B LED- 1IDE LED+ 3IDE LED- 5RESET- 7RESET+ 9LDF+ 11BP A LED+ 13BP A LED- J9: ATX 12V POWER CONNECTOR 1 +12V 2 Ground 3 Ground 4 5V 2.12 Install a Different Processor To install a CPU 1. Local the CPU socket on the motherboard NAR-5510 SeriesUser s Manual 13

15 NAR-5510 CPU socket Press the load lever with your thumb (A), then move it to left (B) until it is released from the retention tab 3. Lift the load lever in the direction of the arrow to a 135 angle 4. Lift the load plate with your thumb and forefinger to a 100 angle (A), then push the PnP cap from the load plate window to remove (B) NAR-5510 SeriesUser s Manual 14

16 5. Position the CPU over the socket, making sure that the gold triangle is on the bottom-left corner of the socket. The socket alignment key should fit into the CPU notch 6. Close the load plate (A), then push the load lever (B) until it snaps into the retention tab Configure Processor Speed The system was designed to self-detect its CPU speed. So it does not require any system adjustment Use a Client Computer NAR-5510 SeriesUser s Manual 15

17 Connection Using Hyper Terminal If users use a headless NAR-5510 system, which has no mouse/keyboard and VGA output connected to it, the console may be used to communicate with NAR To access NAR-5510 via the console, Hyper Terminal is one of many choices. Follow the steps below for the setup: Note: Terminal software may need to update for correct console output. 1. Execute HyperTerminal under C:\Program Files\Accessories\HyperTerminal 2. Enter a name to create new dial 3. For the connection settings, make it Direct to Com1. NAR-5510 SeriesUser s Manual 16

18 4. Please make the port settings to Baud rate 19200, Parity None, Data bits 8, Stop bits 1 5. Turn on the power of NAR-5500 system, after following screen was shown: 6. You can then see the boot up information of NAR NAR-5510 SeriesUser s Manual 17

19 7. When message Hit <DEL> if you want to run Setup appear during POST, after turning on or rebooting the computer, press <Tab> key immediately to enter BIOS setup program. This is the end of this section. If the terminal did not port correctly, please check the previous steps BIOS Setup Information NAR-5510 series is equipped with the Award BIOS within Flash ROM. The BIOS has a built-in setup program that allows users to modify the basic system configuration easily. This type of information is stored in CMOS RAM so that it still retains during power-off periods. When system is turned on, NAR-5510 communicates with peripheral devices and checks its hardware resources against the configuration information stored in the CMOS memory. Whenever an error is detected, or the CMOS parameters need to be initially defined, the diagnostic program will prompt the user to enter the Setup program. Some errors are significant enough to abort the start-up. Entering Setup When message Hit <DEL> if you want to run Setup appear during POST, after turning on or rebooting the computer, press <Del> key immediately to enter BIOS setup program. To enter Setup but fail to respond before the message disappears, please restart the system either by first turning it off and followed by turning it on (COLD START) or simply press the "RESET" buton. WARM START (press <Ctrl>, <Alt>, and <Delete> keys simultaneously) will do as well. When no setting is stored in BIOS or the setting is missing, a message Press <F1> to run Setup will appear. Then press <F1> to run Setup or resume HIFLEX BIOS Setup. User can use the keyboard to choose among options or modify the system parameters to match the options with your system. The table shown on next page will navigate through all of keystroke functions in BIOS Setup. Keys to navigate within Setup menu Key Up ( ) Down ( ) Left ( ) Right ( ) Enter PgUp PgDn Move to the previous item Move to the next item Move to the item on the left (menu bar) Move to the item on the right (menu bar) Enter the item you desired Function Increase the numeric value or make changes Decrease the numeric value or make changes Increase the numeric value or make changes Decrease the numeric value or make changes NAR-5510 SeriesUser s Manual 18

20 Esc F1 F5 F6 F7 F10 Main Menu: Quit and not save changes into CMOS Status Page Setup Menu and Option Page Setup Menu: Exit current page and return to Main Menu General help on SETUP navigation keys Load previous values from CMOS Load the fail-safe defaults from BIOS default table Load the optimized defaults Save all the CMOS changes and exit Main Menu Within NAR-5510 Award BIOS CMOS Setup utility, user should start with the Main Menu. The Main Menu allows to select from eleven setup functions and two exit choices. Use arrow keys to switch among items and press <Enter> to accept or bring up the sub-menu. Phoenix Award BIOS CMOS Setup Utility CMOS Setup Utility Standard CMOS Features Advanced BIOS Features Advanced Chipset Features Integrated Peripherals Power Management Setup PnP/PCI Configurations PC Health Status ESC: Quit F10: Save & Exit Setup Frequency /Voltage Control Load Fail/Safe Defaults Load Optimized Defaults Set Supervisor Password Set User Password Save & Exit Setup Exit Without Saving : Select Item Time, Date, Hard Disk Type... NOTE: It is strongly recommended to reload the optimized default setting if CMOS is lost or BIOS is updated. NAR-5510 SeriesUser s Manual 19

21 Standard CMOS Setup Menu This setup page includes all the items within standard compatible BIOS. Use the arrow keys to highlight the item and then use the <PgUp>/<PgDn> or <+>/<-> keys to select the value or number you want in each item and press <Enter> to certify it. Follow command keys in CMOS Setup table to change Date, Time, Drive type and Boot Sector Virus Protection Status. Screen Shot: Phoenix Award BIOS CMOS Setup Utility Phoenix - AwardBIOS COMS Setup Utility Standard CMOS Feature Date (mm:dd:yy) Time (hh:mm:ss) Wed, Jan : 51 : 13 Menu Level Item Help IDE Channel 0 Master IDE Channel 0 Slave IDE Channel 1 Master IDE Channel 1 Slave Video: Halt On: Base Memory: Extended Memory: Total Memory: 65536K [None] [None] [None] [None] [EGA/VGA] [All, but Keyboard] 640K K K Change the day, month, year and century :Move Enter:Select + / - /PU/PD:Value F10:Save ESC: Exit F1:General Help F5: Previous Value F6: Fail-safe defaults F7: Optimized Defaults Menu Selections Item Options Description Date Date Set the system date. Note date Time HH : MM : SS Set the system time IDE Channel 0 Master Options are in its sub menu (described in Table 3) Press <Enter> to enter the sub menu of detailed options Options are in its sub IDE Channel 0 Slave menu (described in Table 3) Press <Enter> to enter the sub menu of detailed options IDE Channel 1 Master IDE Channel 1 Slave Options are in its sub menu (described in Table 3) Options are in its sub menu (described in Table 3) Press <Enter> to enter the sub menu of detailed options Press <Enter> to enter the sub menu of detailed options EGA/VGA Video CGA 40 Select the default video device CGA 80 NAR-5510 SeriesUser s Manual 20

22 Halt On Base Memory Extended Memory MONO All Errors No Errors All, but Keyboard N/A N/A Select the situation in which you want the BIOS to stop the POST process and notify you Display the amount of conventional memory detected during boot up Display the amount of extended memory detected during boot-up Total Memory N/A Display the total memory available in the system BIOS Features Setup This section allows you to configure your system for basic operation. You are able to select the system s default speed, boot-up sequence, keyboard operation, shadowing and security. Screen Shot: Phoenix Award BIOS CMOS Setup Utility Phoenix - AwardBIOS COMS Setup Utility Advanced BIOS Features X X X X CPU Feature Hard Disk Boot Priority Virus Warning CPU L1 & L2 Cache Hyper-Threading Technology Quick Power On Self Test Disabled First Boot device Second Boot device Third Boot device Floppy Boot other device Disabled Boot Up NumLock Status Gate A20 Option Typematic Rate Setting Typematic Rate (Chars/Sec) Typematic Delay (Msec) Security Option Setup APIC Mode MPS Version Control For OS OS Select For DRAM > 64MB Console Redirection Baud Rate Agent Connect via Agent Wait time(min) Agent after boot Small Logo(EPA) Show [Press Enter] [Press Enter] [Disabled] [Enabled] [Enabled] [Enabled] [USB-FDD] [Hard Disk] [USB-ZIP] [Enable] [On] [Fast] [Disable] [Setup] [Enable] [1.4] [Non-OS2] [Enable] [NULL] [1] [Enabled] [Disabled] Item Help Menu Level :Move Enter:Select + / - /PU/PD:Value F10:Save ESC: Exit F1:General Help F5: Previous Value F6: Fail-safe defaults F7: Optimized Defaults NAR-5510 SeriesUser s Manual 21

23 Console Redirection Set the UNIX Console redirect to the terminal from COM1. The choice: Enabled/Disabled. Baud Rate Set the RS-232 baud rate speed. The choice: 9600, 19200, 38400, and Cache Setup CPU L1 & L2 Cache ( Enabled or Disabled CPU L1 and L2 cache ) Enabled Disabled Enable cache Disable cache CPU L2 Cache ECC Checking ( Enabled or Disabled CPU L2 cache ECC checking ) Enabled Disabled Enable checking Disable checking Hard Disk Boot Priority Use < > or < > to select a device, then press <+> to move it up, or <-> to move it down the list. Press <Esc> to exit this menu. Virus Warning Allows you to choose the VIRUS warning feature for IDE Hard Disk boot sector protection. Enabled Disabled Enable VIRUS warning Disabled VIRUS warning Hyper-Threading Technology For WindowsXP and Linux 2.4.x ( OS optimized for Hyper Threading Technology ) Enabled Disabled Enable Hyper Threading Technology Disabled Hyper Threading Technology NAR-5510 SeriesUser s Manual 22

24 Quick Power On Self Test This category speeds up Power On Self Test (POST) after you power up the computer. If it is set to Enable, BIOS will shorten or skip some check items during POST. Enabled Disabled Enable quick POST Normal POST Boot Up NumLock Status Select power on state for NumLock. The choice: Enabled/Disabled. Typematic Rate Setting Keystrokes repeat at a rate determined by the keyboard controller. When enabled, the typematic rate and typematic delay can be selected. The choice: Enabled/Disabled. Typematic Rate (Chars/Sec) Set the how many number of times a second to repeat a keystroke when you hold the key down. The choice: 6, 8, 10, 12, 15, 20, 24 and 30. Typematic Delay (Msec) Set the delay time after the key is held down before it begins to repeat the keystroke. The choice: 250, 500, 750 and Security Option Select whether the password is required every time the system boots or only when entering setup. System Setup The system will not boot and access to Setup will be denied if the correct password is not entered at the prompt. The system will boot and access to Setup will be denied if the correct password is not entered at the prompt. NAR-5510 SeriesUser s Manual 23

25 OS Select for DRAM > 64MB Select the operating system that is running with more than 64MB of RAM on the system. The choice: Non-OS2, OS2. Integrated Peripherals OnCHip IDE Device Onboard Device SuperIO Device Phoenix - AwardBIOS COMS Setup Utility Integrated Peripherals [Press Enter] [Press Enter] [Press Enter] Menu Level Item Help :Move Enter:Select + / - /PU/PD:Value F10:Save ESC: Exit F1:General Help F5: Previous Value F6: Fail-safe defaults F7: Optimized Defaults OnChip IDE Device Allow you can change IDE setting and SATA setting Onboard Device Allow you to enable or disable USB Controller, USB 2.0 Controller, USB Keyboard and USB Mouse Support SuperIO Device Allow you to change SuperIO setting in this sub menu NAR-5510 SeriesUser s Manual 24

26 OnChip IDE Device IDE HDD Block Mode IDE DMA transfer access On-Chip Primary PCI IDE IDE Primary Master PIO IDE Primary Slave PIO IDE Primary Master UDMA IDE Primary Slave UDMA On-Chip Secondary PCI IDE IDE Primary Master PIO IDE Primary Slave PIO IDE Primary Master UDMA IDE Primary Slave UDMA Phoenix - AwardBIOS COMS Setup Utility OnChip IDE Device [Enabled] [Enabled] [Enabled] [Auto] [Auto] [Auto] [Auto] [Enabled] [Auto] [Auto] [Auto] [Auto] Menu Level Item Help If your IDE hard drive supports block mode select Enabled for automatic detection of the optimal number if block read/writes per sector the drive can support *** On-Chip Serial ATA Setting *** x SATA Mode On-Chip Serial ATA IDE [Disabled] x PATA IDE Mode SATA Port Primary P1, P3 is Secondary :Move Enter:Select + /-/PU/PD:Value F10:Save ESC: Exit F1:General Help F5: Previous Value F6: Fail-safe defaults F7: Optimized Defaults Allow you to disable or enable Pri. /Sec. IDE, of course, you can set the IDE PIO mode and UltraDMA mode here. On-Chip Serial ATA setting can let you change Serial ATA mode, you can find option Disalbe, Auto, Combined Mode, Enhanced Mode, SATA only, If you need to use RAID function, you must change SATA Mode to RAID here Reset to Default Information Reset to default status can be read from ICH6_GPI6. ; After Power On reset, GPI6 = low ( 0 ) ; If Reset to Default (RST2DF) Button pressed (Triggered) ;, then GPI6 will be latch to high ( 1 ). ;; RST2DF register can be cleared by ICH6_GPO19. ; Write a pulse timing (High1_low_high2) to clear RST2DF to 0. ; High1: output GPO19 high, and keep 10 us. ; Low : output GPO19 low, and keep 10 us. ; High2 : output GPo19 high again, and keep high always. ; NAR-5510 SeriesUser s Manual 25

27 ; Programming Guide : ; PG_Step1 : Enable ACPI IO port assignment and get PMBASE, then save to ; EBX_Bit[31..16] ;; First : GPI_ROUT bit[13,12] P [0,0] : Let GPI6 not evoke SCI. ; Write GPI_Rout bit[13,12] to [0,0] for no effect on GPI6 ; ( B0:D31:F0:Offset_B8h-Bit[13,12]P[0,0], no SCI event evoked) ;; Second: Enabe ACPI IO port by setting ACPI_EN bit7 ; B0:D31:F0:Offset_44h_bit7P1 ; Third : Get PMBASE ( ACPI I/O port BAR ) and ; save to EBX_bit[31..16]. ; PMBASE=:B0:D31:F0:Offset[40..43h] ; Let Bit0 = 0.( PCI_BAR bit0 returns 1 for a IO_BAR ) ;; PG_Step2 : Enable GPIO IO function and get GPIOBASE, then save to ; ECX_Bit[31..16] ; ; How to program GPIO19 ( Output only, i.e. GPO19 ) ; ; Get GPIOBASE =: B0:D31:F0:Offset[48..4Bh] ;(and let bit0 = 0 ) ; GPIO_CNTL =: B0:D31:F0:Offset_4Ch_bit4P1 ;Enable ICH6 GPIO ; ; GPIO19 ; GP_LVL (=:(GPIOBASE + 0Ch))_bit19P[0/1]; Write value 0/1 ; ; ; How to read GPI6 ; ====================================================== ; GPI6 status MUST NOT be inverted First. ; GPI_INV (=GPIOBASE+2Ch)-bit6P0. ( GPI6 not inverted ) ; NAR-5510 SeriesUser s Manual 26

28 ; Get GPI6 status from GPE0_STS (=PMBASE+28h)-bit22 ; 0 = low, 1= high level ; ======================================================.MODEL small ; tiny.386.stack 200h.data PROMP1 DB'PORTWELL PPAP-3751,3716RSTD.exe, V ,All rights reserved.$' PROMP1_1 DB ' For PPAP-3751 Reset-to-Default test.',13,10,'$' PROMP_2_CR_LF db 0Dh, 0Ah,0Dh, 0Ah, '$' PROMP_Str1 db ' Reset-To-Default status latched by a F/F. ',0dh,0ah,'$' PROMP_Str2 db ' This status bit = 0 ---> Normal. ',0dh,0ah,'$' PROMP_Str3 db ' pressed.',0dh,0ah,'$' PROMP_Str4 db ' This status bit = 1 ---> RST2DF button has been This status bit can be read by ICH6_GPI6, ',0dh,0ah,'$' PROMP_Str5 db ' and can be cleared by an ICH6_GPO19 High1-Low-High2 pulse.',0dh,0ah,'$' PROMP_Str6 db ' ',0dh,0ah,'$' PROMP_Str7 db ' High1 = 30us High level ',0dh,0ah,'$' PROMP_Str8 db ' Low = 30us Low level ',0dh,0ah,'$' PROMP_Str9 db ' High2 = High level again and no level change from now on.',0dh,0ah,'$' PROMP_StrA db ' ',0dh,0ah,'$' PROMP_rst2df db 0dh,0ah,' Press the Reset-to-Default button and then release it for the test NOW!$' PROMP_anykey db 0dh,0ah,' Ready? If yes, then Press any key to start test... $' PROMP_err1 db 0dh,0ah,' ***** "Reset-to-Default F/F Initialization" Failed. *****',0dh,0ah,'$' NAR-5510 SeriesUser s Manual 27

29 PROMP_err1_1 db ' ( This may be a H/W error or Reset-to-Default button has ever been pressed! )',0dh,0ah,'$' PROMP_err2 db 0dh,0ah,' ***** "Reset-to-Default event latched by F/F " *****',0dh,0ah,'$' Failed. PROMP_err3 db 0dh,0ah,' ***** "Clear Reset-to-Default F/F status " Failed. *****',0dh,0ah,'$' PROMP_TEST_OK db ' <<... PPAP-3751 RESET-TO-DEFAULT test OK...>>',0dh,0ah,'$' PROMP_TEST_fail db ' <<***** PPAP-3751 RESET-TO-DEFAULT test FAIL *****>>',0dh,0ah,'$' PROMP_Qkey db 0dh,0ah,'Press "Q" key to stop test and return to DOS; or other key to go on next test.$' GP_INV_OFFSET GPE0_STS_OFFSET GP_LVL_OFFSET db 2Ch ; The offset value from GPIOBASE db 28h ; The offset value from PMBASE db 0Ch ; The offset value from GPIOBASE GPO_BLINK_OFFSET db 18h ; The offset value from GPIOBASE ( Bit19P0 for GPO19 no blink ) ; EBX_bit[31..16] save PMBASE ( B0:D31:F0:Offset[40..43h]) ; ECX_bit[31..16] save GPIOBASE ( B0:D31:F0:Offset[48..4Bh] ).code programstart: mov ax,@data mov ds,ax lea dx,promp_2_cr_lf mov ah,09h int 21h lea dx,promp1 mov ah,09h int 21h lea dx,promp_2_cr_lf mov ah,09h int 21h NAR-5510 SeriesUser s Manual 28

30 lea dx,promp1_1 mov ah,09h int 21h lea dx,promp_2_cr_lf mov ah,09h int 21h lea dx,promp_str1 mov ah,09h int 21h lea dx,promp_str2 mov ah,09h int 21h lea dx,promp_str3 mov ah,09h int 21h lea dx,promp_str4 mov ah,09h int 21h lea dx,promp_str5 mov ah,09h int 21h lea dx,promp_str6 mov ah,09h int 21h lea dx,promp_str7 mov ah,09h int 21h lea dx,promp_str8 mov ah,09h NAR-5510 SeriesUser s Manual 29

31 int 21h lea dx,promp_str9 mov ah,09h int 21h lea dx,promp_stra mov ah,09h int 21h mov edx, h ; Error flag in EDX_BIT[16..18], 0=ok, 1=failed ; PG_Step1 : Enable ACPI IO port assignment and get PMBASE, then save to ; EBX_Bit[31..16] ; ; First : GPI_ROUT bit[13,12] P [0,0] : Let GPI6 not evoke SCI. ; Write GPI_Rout bit[13,12] to [0,0] for no effect on GPI6 ; ( B0:D31:F0:Offset_B8h-Bit[13,12]P[0,0], no SCI event evoked) ; ; Second: Enabe ACPI IO port by setting ACPI_CNTL bit4 ; B0:D31:F0:Offset_44h_bit7P1 ; Third : Get PMBASE ( ACPI I/O port BAR ) and ; save to EBX_bit[31..16]. ; PMBASE=:B0:D31:F0:Offset[40..43h] ; Let Bit0 = 0.( PCI_BAR bit0 returns 1 for a IO_BAR ) ; ; _start ; Get PMBASE and save to EBX_bit[31..16] ; Let GPI6 GPI_ROUT to [0,0], i.e. not evoke SCI in S0. mov dx,0cf8h ; PCI Config Read mov eax,8000f8b8h ; B0:D31:F0:Offset_B8h out dx,eax mov dx,0cfch NAR-5510 SeriesUser s Manual 30

32 in eax,dx and ah,0cfh out dx,eax mov dx,0cf8h ; bit[13,12] set to [0,0] to let GPI6 not ; evoke SCI event ; PCI Config Read mov eax,8000f844h ; B0:D31:F0:Offset_44h out dx,eax mov dx,0cfch in eax,dx or al,80h ; bit 7 set to 1 to enable PMBASE out dx,eax ; mov dx,0cf8h ; Get PMBASE mov eax,8000f840h ; B0:D31:F0:Offset_40h out dx,eax mov dx,0cfch in eax,dx and al,0feh ; bit0 cleared to 0. rol eax,10h mov ebx,eax ; Save PMBASE to EBX[31..16] ; _end ; PG_Step2 : Enable GPIO IO function and get GPIOBASE, then save to ; ECX_Bit[31..16] ;; How to program GPO19 ; ; Get GPIOBASE =: B0:D31:F0:Offset[48..4Bh] ;(and let bit0 = 0 ) ; GPIO_CNTL =: B0:D31:F0:Offset_4Ch_bit4P1 ;Enable ICH6 GPIO ; ; GPO19 ; GP_LVL (=:(GPIOBASE + 0Ch))_bit19P[0/1]; Write value 0/1 ; NAR-5510 SeriesUser s Manual 31

33 ; ; How to read GPI6 ; ====================================================== ; GPI6 status must NOT be inverted First. ; GPI_INV (=GPIOBASE+2Ch)-bit6P0. ( GPI6 not inverted ) ; ; Get GPI6 status from GPE0_STS (=PMBASE+28h)-bit22 ; 0 = low, 1= high level ; ====================================================== ; ==================================================== 2_start ; Get GPIOBASE Base Address, and save to ECX_bit[31..16] mov dx,0cf8h mov eax,8000f84ch ; B0:D31:F0:Offset_4Ch out dx,eax mov dx,0cfch in eax,dx or al,10h ; 5Ch_Bit4P1 to Enable GPIO out dx,eax mov dx,0cf8h ; Get GPIOBASE mov eax,8000f848h ; B0:D31:F0:Offset_48h out dx,eax mov dx,0cfch in eax,dx and al,0feh ; bit 0 cleared to 0. rol eax,10h mov ecx,eax ; Save GPIOBASE to ECX[31..16] ; Get GPIOBASE Base Address, and save to ECX_bit[31..16] ; Testing way : NAR-5510 SeriesUser s Manual 32

34 ; --- t1 ; Read GPI6 first, GPI6=0? if yes,pass ; if no, failed ; ; --- t2 ; RST2DF button pressed and released, read GPI6,GPI6 = 1? if yes, pass ; if no, failed ; ; --- t3 ; Clear RST2DF status to 0,read GPI6,GPI6 = 0? if yes, pass ; if no, failed ; t_start rol ecx,10h ; Restore GPIOBASE from ECX[31..16] to ECX[15..0] ; make sure GPO19 = 1 start ( RST2DF F/F no cleared by GPO19 ) xor bx,bx mov bl,gp_lvl_offset ; Write GPO19 1 mov dx,cx ; add dx,bx ; add dx,02h in al,dx ; point to GPIO[16..23] register ; read first call IODELAY ; io delay or al,08h ; bit3 ---> GPO19 out dx,al ; output GPO19 1 ; make sure GPO19 = 1 end ; make sure GPIO19 BLINK Disable xor bx,bx mov bl,gpo_blink_offset ; mov dx,cx ; add dx,bx ; add dx,02h in al,dx ; point to GPIO[16..23] register ; read first NAR-5510 SeriesUser s Manual 33

35 call IODELAY ; io delay and al,0f7h out dx,al ; bit3 ---> GPO19 ; output 0 to disable GPIO19 blink ; make sure GPO19 Blink Disable ; ============================ MUST DO ==========================Start ; GP_INV bit6 MUST Program 0 for GPI6 state not inverted. start xor bx,bx mov bl,gp_inv_offset ; Not invert GPI6 status mov dx,cx ; add dx,bx in al,dx ; bit6 ---> GPI6 ; read first call IODELAY ; io delay and al,0bfh ; mask bit6 and write 0 out dx,al ; GP_INV bit6 MUST Program 0 for GPI6 state not inverted. end ; ============================ MUST DO ==========================End ; ---- t1 start ; GPI6, read its status, initialization will be 0. ; ; How to read GPI6 ; ; PMBASE has been stored in EBX[31..16]. ; Get GPI6 status from GPE0_STS (=PMBASE+28h)-bit22 ; 0 = low, 1= high level ; NAR-5510 SeriesUser s Manual 34

36 call READ_GPI6_TO_AL and al,40h ; mask bit6 cmp al,00h je next_test1 ; okay, go on test ; jz next_test1 ; okay, go on test ; no, error message display lea dx,promp_err1 mov ah,09h int 21h lea dx,promp_err1_1 mov ah,09h int 21h ror edx,10h ; error falg EDX_Bit16, 1 --> Error happened or dl,01h rol edx,10h call KB_Wait ; ---- t1 end next_test1 : ; ---- t2 start lea dx,promp_rst2df mov ah,09h int 21h lea dx,promp_anykey mov ah,09h int 21h xor al,al ; halt for ready? Any key pressed to go on. WAIT_KB_0: mov ah,1 int 21h NAR-5510 SeriesUser s Manual 35

37 cmp al,0 je WAIT_KB_0 lea dx,promp_2_cr_lf mov ah,09h int 21h ; test RST2DF button pressed call READ_GPI6_TO_AL and al,40h ; mask bit6 cmp al,40h je next_test2 ; okay, go on test ; no, error message display lea dx,promp_err2 mov ah,09h int 21h ror edx,10h ; error falg EDX_Bit17, 1 --> Error happened or dl,02h rol edx,10h call KB_Wait ; ---- t2 end next_test2 : ; ---- t3 start,clear RST2DF F/F ; GPO19 write 1,0,1 ; ; ========= Write GPO start xor bx,bx mov bl,gp_lvl_offset ; Write GPO19 1 mov dx,cx ; add dx,bx ; NAR-5510 SeriesUser s Manual 36

38 add dx,02h in al,dx ; point to GPIO[16..23] register ; read first call IODELAY ; io delay or al,08h ; out dx,al call FIXDELAY in al,dx ; output GPO19 1 first ; 30 us delay ; output GPO19 0 then call IODELAY and al,0f7h out dx,al call FIXDELAY in al,dx ; 30 us delay ; output GPO19 high finally call IODELAY or al,08h out dx,al ; ========= Write GPO end call READ_GPI6_TO_AL ; check RST2DF F/F and al,40h ; mask Bit6 cmp al,00h je test_end ; okay, then end ; jz test_end ; okay, then end ; no, error message display lea dx,promp_err3 mov ah,09h int 21h ror edx,10h ; error falg EDX_Bit18, 1 --> Error happened or dl,04h rol edx,10h NAR-5510 SeriesUser s Manual 37

39 ; ---- t3 end test_end : ror edx,10h ; check error flag cmp dl,00h je test_ok test_fail : lea dx,promp_2_cr_lf mov ah,09h int 21h lea dx,promp_test_fail mov ah,09h int 21h jmp return_to_dos test_ok : lea dx,promp_test_ok mov ah,09h int 21h ror ecx,10h ; ECX[15..0] to ECX[31..16] ; Restore GPIOBASE to ECX[31..16] return_to_dos : mov ah,4ch ; Return to DOS int 21h ; t_end ; ==================================================== 2_end IODELAY PROC near push ax push dx NAR-5510 SeriesUser s Manual 38

40 mov dx,0edh in al,dx jmp $+2 mov dx,0edh in al,dx pop dx pop ax ret IODELAY ENDP KB_wait PROC near push ax push bx push cx push dx lea dx,promp_qkey mov ah,9 ; Display "Q" key prompt int 21h xor al,al WAIT_KB: mov ah,1 int 21h cmp al,0 je WAIT_KB cmp al,51h ; "Q" pressed? je test_fail cmp al,71h ; "q" pressed? jne call_return jmp test_fail ; NAR-5510 SeriesUser s Manual 39

41 call_return : lea dx,promp_2_cr_lf mov ah,09h int 21h pop dx pop cx pop bx pop ax ret KB_wait ENDP ; ; ; READ_GPI6_TO_AL ; ; ; ; Input : NONE ; ; STACK PRESENT ; ; Output: AL, Bit6 = GPI6 ; ; ; ; Destroy : AL ; ; ; READ_GPI6_TO_AL PROC near push bx push dx xor bx,bx rol ebx,10h ; restore PMBASE from EBX_bit[31..16] to EBX_bit[15..0] mov dx,bx NAR-5510 SeriesUser s Manual 40

42 ror ebx,10h ; save PMBASE to EBX_Bit[31..16] mov bl,gpe0_sts_offset add bl,02h ; Point to Bit22 add dx,bx in al,dx call IODELAY ; io delay ; MUST to do write 1 to clear GPE0_STS_bit6 to 0 FIRST due to the ; access ( 0/1 ). This register is R/WC, and will be set ; at any time when GPI signal is high. ; and al,40h ; mask bit6 or al,40h ; WC out dx,al ; Write bit6 to 0 first. call IODELAY ; io delay in al,dx ; read GPI6 again pop dx pop bx ret READ_GPI6_TO_AL ENDP ; ; ; FIXED_DELAY ; ; ; ; Input : (CX) count of 15 microseconds to wait ; ; STACK PRESENT ; ; Output: NONE ; ; CX=2, 15us x 2 = 30 us ; ; ; ; This routine is called to wait for 15 microseconds * count in ; NAR-5510 SeriesUser s Manual 41

43 ; (CX), then return. Gives a programmed software delay. ; ; ; FIXDELAY PROC near push cx push dx push ax pushf mov cx,02h mov dx,61h in al,dx ; jmp $+2 jmp $+2 and al, b ; mov ah,al ; fixed_delay_1: in al,dx ; jmp $+2 jmp $+2 and al, b ; cmp al,ah ; jz short fixed_delay_1 ; mov ah,al ; loop short fixed_delay_1 ; popf pop ax ; pop dx pop cx ret FIXDELAY ENDP NAR-5510 SeriesUser s Manual 42

44 END programstart 2.16 ByPass & WDT Programming Guide Block Diagram Figure 1. Block Diagram * PCR := PCI Configuration Register * B#:D#:F# :R# := Bus Number: Device Number: Function Number: Register Offset, e.g.:b0:d28:f0:r10h * BP := By Pass * BP_WDT := The Watch Dog Timer for By Pass function * Intel VID = 8086h, Marvell VID = 11ABh * PN1 :=PCI e x1 Port Number 1, there are 4 PCI e x1 ports in ICH6. * Exclusively population: (Manufacturing options) U48 and U49 are exclusively populated on board. U55 and U75 are exclusively populated on board. U59 and U49 are exclusively populated on board. NAR-5510 SeriesUser s Manual 43

45 U58 and U75 are exclusively populated on board. That is, If U48,and U55 populated on board, then U49 and U75 must not exist on board. If U59,and U58 populated on board, then U49 and U75 must not exist on board. If U49,and U75 populated on board, then U48,U55,U59 and U58 must not exist on board. There are two By_Pass groups on NAR BP_Group_A is composed of J34 and J35, BP_Group_B is composed of J43 and J44. The four PCI-e Bridges in ICH6 control the 4 PCI-e port (PN1 ~ PN4). The PCI bus number can be read by accessing the PCR of B0:D28:F0/F1/F2/F3. PCI-e x1 from ICH6 B#:D#:F# DID Table 1: PCI-e Ports BNUM ( PCR_Offset[18..1Ah] ), Bus Number (PCR_offset[02~03h]) Register SBBN(bit[23..16]) SCBN(bit[15..8]) PBN(bit[7..0]) PN1 B0:D28:F 2660h Assigned by Assigned by 00h 0 BIOS BIOS PN2 B0:D28:F 2662h Assigned by Assigned by 00h 1 BIOS BIOS PN3 B0:D28:F 2664h Assigned by Assigned by 00h 2 BIOS BIOS PN4 B0:D28:F h Assigned by BIOS Assigned by BIOS 00h SBBN: Subordinate Bus Number: Indicate the highest PCI Bus Number below the bridge. SCBN: Secondary Bus Number: Indicate the Bus Number of this Port. PBN: Primary Bus Number: Indicate the Bus Number of the backbone. * PCI BUS number of the PCI-e port can be read from PCR_BNUM. * The PCI bus number of the PCI-e device is the SCBN of the related PCI-e Port. * The PCI bus number for PCI_32 is (the last SCBN of PCI-e) + 1. For example, if ( the last SCBN of PCI-e ) is 4, then the bus number of PCI_32 is 5. * The device number of the PCI-e device will be 00h. * The device number of U48 on PCI_32 is 01h. * The device number of U55 on PCI_32 is 02h. * Marvell 8053 is a single function (Function Number = 00h) PCI-e device. The physical BP ports, RJ45 connectors, are BP_Group_A (J34, J35), and BP_Group_B( J43,J44 ). BP_Group_A has 2 Ethernet MAC configurations. Either from PCI-e Ethernet MAC or from PCI_32 Ethernet MAC How to program BP controller BP controller uses 20 GPIO pins from the SuperIO, W83627HF, and one CPLD decoder. The main software commands for BP and BP_WDT will have: Set_to_Normal : issuing this command will force BP ports to work at Normal mode. Set_to_BP : issuing this command will force BP ports to work at By Pass mode. Read_BP_Status : One status bit to indicate the current mode. ( 0: Normal mode ; 1: By pass mode ) NAR-5510 SeriesUser s Manual 44

46 En_BP_WDT : Enable or Refresh BP_WDT. Once this command issued, then the BP group will at Normal mode. If BP_WDT expires without any refresh in time, then the BP group will change to BP mode. Dis_BP_WDT : Disable BP_WDT. Will disable BP_WDT counting and stay at the current mode. Read_BP_WDT_Status : Read the BP_WDT_Status bit. ( 1 : Normal state; 0 : Time out state ) BP_WDT_status bit can be set to 1 by AC power on or Clear_BP_WDT_Status command. If BP_WDT expires, then this bit will change its state from 1 to 0 and always keep 0 until nextpower off-on or a Clear_BP_WDT_Status command. Clear_BP_WDT_Status : the BP_WDT Status bit will be set to 1, Normal state. SuperIO ( W83627THF ) Logical Device 7 ( LD7 ), LD8,and LD9 control the GPIO direction, inversed or not, and the data port. Multiplex pins must be declared first to assign GPIO functions from these pins. Table 2 : Init Multiplex pin to GPIO function GPIO pin from SIO Program the Related bits in SIO Configuration Register ( CR ). SGP10 ~ 17 CR29h_Bit[7,6]P[0,1] SGP20 CR29h_Bit[1,0]P[0,1] SGP21 CR2Ah_Bit[7,6]P[0,1] SGP22 CR2Ah_Bit5P0 SGP23 CR2Ah_Bit4P0 SGP24 CR2Ah_Bit3P0 SGP25 CR2Ah_Bit2P0 SGP26 CR2Ah_Bit1P0 SGP34 CR2Bh_Bit[5,4]P[0,1] SGP35 CR2Bh_Bit6P0 SGP SGP40 CR2Dh_Bit0P0 SGP45 CR2Dh_Bit5P0 Notes: CR2Dh_Bit5P0 means Program Bit5 of Config Register Index 2Dh of SuperIO ( SIO ) to 0. CR29h_Bit[7,6]P[0,1] : Write 0 to Bit7, and 1 to Bit6 of CR29h of SIO. GPIO Definition LD of SIO SGP10 LOADJ_A SGP11 LOADJ_B SGP12 WDT0 SGP13 WDT1 SGP14 WDT2 SGP15 WDT3 SGP16 WDT4 SGP17 WDT5 SGP20 BP_STS_B SGP21 BP_STS_A SGP22 BP_WDT_STS_B SGP23 BP_WDT_STS_A SGP24 SET_NORM_A SGP25 SET_BP_A SGP26 SET_NORM_B SGP34 SET_BP_B Table 3 : GPIO Pin ( or Bit ) Map Enable LD Direction Bit Bit 1=Input 1= Enable, 0=Output 0=Disable Inverse Bit 1= Inverse 0=Not inverse Data Bit Needs to be initialized to LD7 CR30h_Bit0 CRF0h_Bit0 CRF2h_Bit0 CRF1h_Bit0 En_Out_NI_1 LD7 CR30h_Bit0 CRF0h_Bit1 CRF2h_Bit1 CRF1h_Bit1 En_Out_NI_1 LD7 CR30h_Bit0 CRF0h_Bit2 CRF2h_Bit2 CRF1h_Bit2 En_Out_NI_1 LD7 CR30h_Bit0 CRF0h_Bit3 CRF2h_Bit3 CRF1h_Bit3 En_Out_NI_1 LD7 CR30h_Bit0 CRF0h_Bit4 CRF2h_Bit4 CRF1h_Bit4 En_Out_NI_1 LD7 CR30h_Bit0 CRF0h_Bit5 CRF2h_Bit5 CRF1h_Bit5 En_Out_NI_1 LD7 CR30h_Bit0 CRF0h_Bit6 CRF2h_Bit6 CRF1h_Bit6 En_Out_NI_1 LD7 CR30h_Bit0 CRF0h_Bit7 CRF2h_Bit7 CRF1h_Bit7 En_Out_NI_1 LD8 CR30h_Bit0 CRF0h_Bit0 CRF2h_Bit0 CRF1h_Bit0 En_In_NI LD8 CR30h_Bit0 CRF0h_Bit1 CRF2h_Bit1 CRF1h_Bit1 En_In_NI LD8 CR30h_Bit0 CRF0h_Bit2 CRF2h_Bit2 CRF1h_Bit2 En_In_NI LD8 CR30h_Bit0 CRF0h_Bit3 CRF2h_Bit3 CRF1h_Bit3 En_In_NI LD8 CR30h_Bit0 CRF0h_Bit4 CRF2h_Bit4 CRF1h_Bit4 En_Out_NI_1 LD8 CR30h_Bit0 CRF0h_Bit5 CRF2h_Bit5 CRF1h_Bit5 En_Out_NI_1 LD8 CR30h_Bit0 CRF0h_Bit6 CRF2h_Bit6 CRF1h_Bit6 En_Out_NI_1 LD9 CR30h_Bit0 CRF0h_Bit4 CRF2h_Bit4 CRF1h_Bit4 En_Out_NI_1 NAR-5510 SeriesUser s Manual 45

47 SGP35 DIS_BP_WDT_A LD9 CR30h_Bit0 CRF0h_Bit5 CRF2h_Bit5 CRF1h_Bit5 En_Out_NI_1 SGP36 DIS_BP_WDT_B LD9 CR30h_Bit0 CRF0h_Bit6 CRF2h_Bit6 CRF1h_Bit6 En_Out_NI_1 SGP40 CLR_WDT_STS_B LD9 CR30h_Bit1 CRF4h_Bit0 CRF6h_Bit0 CRF5h_Bit0 En_Out_NI_1 SGP45 CLR_WDT_STS_A LD9 CR30h_Bit1 CRF4h_Bit5 CRF6h_Bit5 CRF5h_Bit5 En_Out_NI_1 Notes: (1) LD : Logical Device of SIO. There are 10 LDs in W83627THF SIO. CR00~2Fh : Global control registers. ( All LDs share these CRs ) CR07h : LD selection. CR30~FFh : Each LD has its own CRs. (2) Direction Bit: Viewed from SIO. (3)Al Inversed bits need to be programmed to 0,i.e. Not Inversed. (4) En_Out_NI_1: Enable LD, Set to Output direction, Data bit will be Not Inversed and initialized to 1. (5) En_In_NI : Enable LD, Set to Input direction, and Not Inverse the data bit. (6) The data bit will be automatically turned around when set as Output bit. i.e. you can read the data back when you output the data on the output pins Programming Guide ( PG ) PG_1 : << How to access SIO configuration Register >> EFIR : Index Port to access SIO CR, 002eh EFDR : Data Port to access SIO CR, 002fh Enter 83627THF extended mode to access CR mov dx,2eh ; Must Enter the extended mode first to access SIO CR. mov al,87h out dx,al jmp $+2 out dx,al Exit 83627THF extended mode to access CR mov dx,2eh ; Once the program ends, Exit the extended mode of SIO. mov al,0aah out dx,al 83627THF_CR : Index 07h : This register contains the Logical Device ( LD ) number, and allows users to select the LD. Index 00~2Fh : Global (common) registers Index 30~FFh : Every LD has its own definition. To access CR30~FFh, you must point the LD number first. PG_2 : << Init every multiplex pin to GPIO function>> NAR-5510 SeriesUser s Manual 46

48 CR29h_Bit[7,6]P[0,1] ; Write data [0,1] to CR29h_Bit[7,6] CR29h_Bit[1,0]P[0,1] CR2Ah_Bit[7,6]P[0,1] CR2Ah_Bit5P0 CR2Ah_Bit4P0 CR2Ah_Bit3P0 CR2Ah_Bit2P0 CR2Ah_Bit1P0 CR2Bh_Bit[5,4]P[0,1] CR2Bh_Bit6P0 CR2Dh_Bit0P0 CR2Dh_Bit5P0 PG_3 : << Enable GPIO and Set every GPIO pin direction and as non-inversed, and Init every output pin to 1 >> LD7_CR30_Bit0P1 LD7_CRF0h_P00h LD7_CRF2h_P00h LD7_CRF1h_P00h LD8_CR30_Bit0P1 LD8_CRF0h_P0Fh LD8_CRF2h_P00h LD8_CRF1h_Bit[6,5,4]P[1,1,1] LD9_CR30_Bit[1,0]P[1,1] LD9_CRF0h_P00h LD9_CRF2h_P00h LD9_CRF1h_Bit[6,5,4]P[1,1,1]h LD9_CRF4h_P00h LD9_CRF6h_P00h LD9_CRF5h_Bit[5,0]P[1,1] ; PG_4 : << How to Set to Normal Mode >> Set to Normal Mode to BP_Group_A (J34,J35): Make a H-L-H pulse on SET_NORM_A ( LD8_CRF1h_Bit4 ) bit. H-L-H pusle ( H : Write 1 to this bit, L : Write 0 to this bit ) LD8_CRF1h_Bit4P1 ; For First High duration, 15us at least. Retain 15us at least LD8_CRF1h_Bit4P0 ; For low duration, 15us at least. Retain 15us at least LD8_CRF1h_Bit4P1 ; For second High duration, it needs to retain high Retain 4 ms at least ; at least 4 ms to operate the mechanical relay contacts. Set to Normal Mode to BP_Group_B (J43,J44) Make a H-L-H pulse on SET_NORM_B ( LD8_CRF1h_Bit6 ) bit. The retention timing of this data bit will be same with SET_NORM_A. NAR-5510 SeriesUser s Manual 47

49 PG_5 : << How to Set to Bypass Mode >> Set to Bypass Mode to BP_Group_A (J34,J35): Make a H-L-H pulse on SET_BP_A ( LD8_CRF1h_Bit5 ) bit. LD8_CRF1h_Bit5P1 ; For First High duration, 15us at least. Retain 15us at least LD8_CRF1h_Bit5P0 ; For low duration, 15us at least. Retain 15us at least LD8_CRF1h_Bit5P1 ; For second High duration, it needs at least 4 ms to release Retain 4 ms at least ; the mechanical relay contacts. Set to Bypass Mode to BP_Group_B (J43,J44) Make a H-L-H pulse on SET_BP_B ( LD9_CRF1h_Bit4 ) bit. The retention timing of this data bit will be same with SET_BP_A PG_6 : << How to Read BP mode ( Status ) >> BP status bit : 0 Normal mode 1 BP mode Table 4 : BP Status map BP_Group_A ( J34,J35 ) BP_Group_B ( J43,J44 ) BP_STS_A BP_STS_B ( LD8_CRF1h_Bit1 ) ( LD8_CRF1h_Bit0 ) Enable/Refresh and Disable BP_WDT PG_7 : << How to Enable/Refresh BP_WDT >> WDT[5..0] are common data for BP_Group_A and BP_Group_B. To enable or refresh WDT, Need to write the WDT[5..0] first, Then execute the load command ( make a H-L-H pulse on LOADJ_A/B bit) Enable/Refresh WDT for BP_Group_A (J34,J35): First step : Set Twd ( WDT time out period ) LD7_CRF1h_P[xxxxxx11] ; Twd = LD7_CRF1h_Bit[7..2], ~ b ( 1 ~ 63 options available, Time unit = 1 second. ) Bit7 maps to WDT5,., Bit2 maps to WDT0. If Twd = b, then BP_WDT will not be enabled/refreshed. Retain 15us at least. Second step : Make a H-L-H pulse on LOADJ_A ( LD7_CRF1h_Bit0) bit. LD7_CRF1h_Bit0P1 ; Retain 15us at least LD7_CRF1h_Bit0P0 Retain 15us at least LD7_CRF1h_Bit0P1 Retain 15us at least Once BP_WDT has been enabled, please refresh BP_WDT before it expires. Consider 5% tolerance when you refresh BP_WDT. For example, if BP_WDT enabled ( or refreshed ) with 1 second Twd, then refresh BP_WDT earlier than 0.95 second passed since last enabled ( or refreshed ) action. NAR-5510 SeriesUser s Manual 48

50 Enable/Refresh WDT for BP_Group_B (J43,J44) : Same algorithm and retention timing with BP_Group_A. First step : Set Twd: LD7_CRF1h_P[xxxxxx11] ; Second step: Make a H-L-H pulse on LOADJ_B ( LD7_CRF1h_Bit1 ) bit. PG_8 : << How to Disable BP_WDT >> Make a H-L-H pulse with 15us retention timing ( same as LOADJ_A ) for disabling BP_WDT. Table 5 : Disable BP_WDT BP_Group_A BP_Group_B DIS_BP_WDT_A ( LD9_CRF1h_Bit5 ) DIS_BP_WDT_B ( LD9_CRF1h_bit6 ) PG_9: << How to Read BP_WDT status and clear BP_WDT timeout status >> Read BP_WDT status bit. Normal ( WDT not expired ), this bit returns "1". If WDT expires, then this bit will be changed to "0". ( Once WDT expires, this bit will keep "0". When a power off_on or writing to WDT_clear bit H-L-H pulse with 15us then BP_WDT will be set to "1" again. ) BP_WDT status bit BP_WDT clear bit Table 6 : BP_WDT status BP_Group_A ( J34, J35 ) BP_WDT_STS_A ( LD8_CRF1h_Bit3 ) CLR_WDT_STS_A ( LD9_CRF5h_Bit5 ) BP_Group_B ( J43.J44) BP_WDT_STS_B ( LD8_CRF1h_bit2 ) CLR_WDT_STS_B ( LD9_CRF5h_Bit0 ) Sample code to enable BP_WDT_A and _B Assume these 20 GPIO bits are initialized completely. ; WDT_enable ( Enable or Refresh WDT ) ; Input : TWD ; the Time-out period 1 ---> 3Fh, Byte ; Bit7 : WDT5 ; 6 : WDT4 ; 5 : WDT3 ; 4 : WDT2 ; 3 : WDT1 ; 2 : WDT0 ; 1 : LOADJ_B ; 0 : LOADJ_A ; ; Return : None ; WDT_enable PROC near NAR-5510 SeriesUser s Manual 49

51 push si push bx push dx push ax mov si,offset TWD lodsb ; Get Twd mov ah,al ; Keep Twd in ah first mov bx,efir_port mov dx,bx mov al,07h out dx,al inc dx ; EFDR mov al,07h out dx,al ; Point to LD7 dec dx ; EFIR mov al,0f1h out dx,al inc dx ; EFDR mov al,ah ; Program Twd or al,03h ; LoadJ bits keep high first out dx,al ; Write Twd call fixdelay_15us ; delay 15uS dec dx ; EFIR ; output loadj High mov al,0f1h out dx,al inc dx ; EFDR in al,dx mov ah,al dec dx ; EFIR ; mov al,0f1h out dx,al inc dx ; EFDR mov al,ah or al,03h out dx,al call fixdelay_15us ; delay 15uS dec dx ; EFIR ; output loadj low mov al,0f1h out dx,al inc dx ; EFDR in al,dx mov ah,al dec dx ; EFIR ; NAR-5510 SeriesUser s Manual 50

52 mov al,0f1h out dx,al inc dx ; EFDR mov al,ah and al,0fch out dx,al call fixdelay_15us ; delay 15uS dec dx ; EFIR ; output loadj High again mov al,0f1h out dx,al inc dx ; EFDR in al,dx mov ah,al dec dx ; EFIR ; mov al,0f1h out dx,al inc dx ; EFDR mov al,ah or al,03h out dx,al call fixdelay_15us ; delay 15uS pop ax pop dx pop bx pop si ret WDT_enable ENDP NAR-5510 SeriesUser s Manual 51

53 2.17 About EZIO-100 Proprietary keypad and LCD display interfaces are implemented in traditional computing system design, but they are usually different from system to system. The main purpose to roll this module out is to provide an easier human-machine interface for those computing systems regarding application friendly operation as a must. The design goals of this interface are: A single interface for those applications where both LCD display and keypad are required. This interface should be available in every computing system. The communication implementation should be OS independent. Our solution is to use Serial port as the interface for both LCD display and keypad. A simple protocol is further defined so that applications can directly communicate with this module no matter what the Operating System is. WARNING! THE LCD DRIVER ICS ARE MADE OF CMOS PROCESS, DAMAGED BY STATIC CHARGE VERY EASILY. MAKE SURE THE USER IS GROUNDED WHEN HANDLING THE LCD Features Ideal user interface for communication appliance No driver required; OS independent Alphanumeric characters display support Four key pads can be customized for different applications Easy system installation and operation Clearly display system status Single interface to SBC or M/B Technical Support Information For further support, users may also contact Portwel sheadquarter in Taipei or your local distributors. Taipei Office Phone Number: NAR-5510 SeriesUser s Manual 52

54 Mechanical Specification Module Size (mm): Display Format: Character Size: 101.6(W) x 26.0(H) x 30.6(D) (max.) 16 characters x 2 lines 3.0 x 5.23 mm General Specification General Specification Display Resolution: Dimensional Outline (mm): Function Key: Display Icon: Interface: 16 characters x 2 lines 101.6(W) x 26.0(H) x 30.6(D) (max.) Four operation keys (up, down, enter and ESC) Eight self-defined icons RS-232 Absolute Maximum Rating Normal Temperature Item Operating Storage Max. Min. Max. Min. Ambient Temperature 0ºC +50ºC -20ºC +70ºC Humidity (w/o condensation) Note 2, 4 Note 3, Product Outlook NAR-5510 SeriesUser s Manual 53

55 Interface Pin Assignment There are only two connectors in this module, as shown in Figure C.2-1: power connector and Serial Port connector. The power source into this module is 5 volt only. There are only three pins used in the Serial Port interface (Figure C.2-2). Power Connector Serial Port Connector Pin 2: TxD Pin 3 : RxD Pin 5 : Ground Fig. C.2-1 Power connector and serial port connector of EZIO-100 Fig. C.2-2 Pin assignment In other words, the Serial Port is defined as DCE. Therefore, we can use a straight-through cable to connect it to the Serial Port of most of the computers, defined as DTE. (1) Interface Pin Assignment PIN NO. PIN OUT Description 1 NC No connector 2 RXD RS232 Data 3 TXD RS232 Data 4 NC No connector 5 V SS Ground 6 NC No connector 7 NC No connector 8 NC No connector 9 NC No connector 9 NC No connector (2) Power PIN NO. PIN OUT Description 1 NC No connector 2 GND Power GND 3 GND Power GND 4 +5V Power VCC (+5V) NAR-5510 SeriesUser s Manual 54

56 Hardware installation The installation steps are: Connect the power connector to the power connector of this module. Connect the straight-through cable between Serial Port of this module and computer EZIO Function Command First, all versions (00A, 01A, 02A) of EZIO can use those commands. Only the 02A version of EZIO firmware that adds FE 28 & FE 37 command can control start of HEX &End of HEX. EZIO is an intelligent device, which will display those data received from RS-232 port and reply key pressing status to polling command from RS-232 port. Both commands and data go thru RS-232 ports. To distinguish between data and commands, the LCD/key-pad module recognizes a command prefix, 254 (Hex 0FE). The byte folowing 254 wil be processed as a command. For example, to clear the screen, send the command prefix (254) followed by the LCD clear-screen code (1). The valid data range is shown as the following table: Valid data range Displayed characters 0-7 Customized icon (30-39 Hex) (41-5A Hex) A-Z (61-7A Hex) a-z To get the key pressing status, a read key command can be issued to this module, which will check the key-pressing status and reply accordingly. The following are the commands and corresponding Decimal/Hex values: Functions/commands Decimal/Hex Comment 1. Start Of HEX 40/28 Only for 02A 2. End Of HEX 55/37 Only for 02A 3. Clear screen 1/01 4. Home cursor 2/02 5. Read key 6/06 See note 1 6. Blank display (retaining data) 8/08 7. Hide cursor & display blanked characters 12/0C 8. Turn on (blinking block cursor) 13/0D 9. Show underline cursor 14/0E 10. Move cursor 1 character left 16/ Move cursor 1 character right 20/ Scroll 1 character left 24/ Scroll 1 character right 28/1C NAR-5510 SeriesUser s Manual 55

57 14. Set display address (position the cursor) location 128 (Hex080)+ Location See note Set character-generator address 64 (Hex 040)+ address See note 3 Note 1:Upon receiving the read key command from host computer, the LCD/keypad module will check the status of every key and reply with status command accordingly. The replied message from LCD/key-pad module consists of a header and a status byte. The header byte is 253 (Hex0FD). The high nibble (with the most significant bit) of the status byte is always 4 and the low nibble (with the least significant bit) of the status byte is used to indicate key pressing status of the keypad module. This nibble wil be F (of four 1s), if no key pressed while the read key received. 0 wil be used to indicate key pressing status of corresponding key. There are four keys in this module upper arrow, down arrow, enter (ENT), and escape (ESC). The relationship between the function key, corresponding status bit and status byte is shown as the table below. Function key Corresponding status bit Status byte Escape The fourth bit of lower nibble (the least significant bit) 4E (H) (1110) Up arrow The third bit of lower nibble (1101) 4D (H) Enter The second bit of lower nibble (1011) 4B (H) Down arrow The first bit of lower nibble (0111) 47 (H) More than one key can be pressed at the same time so that there may be more than one 0 s in the low nibble of status byte. For example, if Up and Down arrow keys are pressed at the same time while read key command received, the replied status wil be Hex045. Note 2: This command can be used to place the cursor at any location. The corresponding address for each character on the screen is as follows: For 16 2 Display Address Character Location A 0B 0C 0D 0E 0F (Address) A 4B 4C 4D 4E 4F The addresses of characters at the same row are continuous, so moving cursor commands can be applied to shift the cursor position back and forth. However, the addresses of characters between upper and lower row are discontinuous. To change cursor position between upper row and lower row, this command will be applied. Note 3: This command can be used to create customized icon. The starting address is 64 and every character will take 8 bytes to create a 5(W) x 7(H) resolution picture, as shown below: NAR-5510 SeriesUser s Manual 56

58 CG RAM MAPPING CG RAM Address Character Patterns (CG RAM data) High Low High Low * * * Character Pattern Cursor Character * * * Pattern Cursor * * * Character Pattern Cursor To show the customized icon, simplysend the data between 0 to 7 to this module. For example, this module will display the customized icon at location 64 to 71 upon receiving data 0 ; white it will display the customized icon at location 72 to 79 upon receiving data 1. Watchdog timer is also built in the module. This module will reset itself and send out reset packet (0FDH, 0EH) thereafter. The input must be a standard RS-232 or inverted TTL signal. The RS-232 setting should be: Baud rate: 2400 bps Parity: None Data bits: 8 Stop bit: 1 What follows is the default setup after LCD module initiated: 2-line display mode; every character is 5 x 8 dots. NAR-5510 SeriesUser s Manual 57

59 Display on; cursor off; cursor blink off. Display will be cleared. Shift right for entry mode. Set address counter to 00 (cursor positionto 0) In entry mode Character Generator ROM (CGROM) NAR-5510 SeriesUser s Manual 58

60 Sample Codes /* ************************************* * EZIO RS232 LCD Control Sample Program * ************************************* * ************************************************************************* * Company: Portwell Inc. * Date: 4/16/2003 * Program: 02A.c * Version: 1.02 * Compile: Linux GNU C * Purpose: Direct access to EZIO LCD, the program will display * messages according to the control button. The current * version only has the following function: * * 1: display welcome message * 2: display UP message if "scroll up" button is pressed * 3: display ENTER message if "ENTER" button is pressed * 4: display ESC message if "ESC" button is pressed * 5: display DOWN message if "scroll down" button is pressed * * Program Overview: * * - Parameters: * fd : a file name for open() method, here represents the com port * Cmd : command prefix * cls : clear command * init : initialize command * blank : display blank screen * stopsend : stop input/output * home : move cursor to initial position * readkey : set to read from EZIO * hide : hide cursor & display blanked characters * movel : move cursor one character left * mover : move cursor one character right * turn : turn on blinking-block cursor * show : turn on underline cursor * scl : scroll cursor one character left * scr : scroll cursor one character right * setdis : set character-generator address * * - Procedure: * 1. The program sets up the environment, i.e. com port settings. * 2. The main function MUST call init() twice to initialize EZIO * before any communication. * 3. For executing any command, the command prefix, Cmd, MUST be * called be command. So all command contains two parts, eg. * to initialize the sequence of HEX number is 0xFE, 0x25. * 4. After clear screen and display welcome message, ReadKey() * method must be call to advise EZIO for reading data. * 5. A pooling method is implemented to get input from EZIO while * any button is pressed. * * - NOTE: This program is a sample program provided " AS IS" with NO * warranty. * * Copyright (c) Portwell, Inc. All Rights Reserved. * * ************************************************************************/ NAR-5510 SeriesUser s Manual 59

61 #include <sys/stat.h> #include <fcntl.h> #include <unistd.h> #include <stdlib.h> static int fd; void SetEnvironment () { system("stty ispeed 2400 < /dev/ttys1"); system("stty raw < /dev/ttys1"); int Cmd = 254; /* EZIO Command */ int cls = 1; /* Clear screen */ void Cls () { write(fd,&cmd,1); write(fd,&cls,1); int init = 0x28; void Init () { write(fd,&cmd,1); write(fd,&init,1); int stopsend = 0x37; void StopSend () { write(fd,&cmd,1); write(fd,&init,1); int home = 2 ; /* Home cursor */ void Home () { write(fd,&cmd,1); write(fd,&home,1); int readkey = 6 ; /* Read key */ void ReadKey () { write(fd,&cmd,1); write(fd,&readkey,1); int blank = 8 ; /* Blank display */ void Blank () { write(fd,&cmd,1); write(fd,&blank,1); int hide = 12 ; /* Hide cursor & display blanked characters */ void Hide () { write(fd,&cmd,1); write(fd,&hide,1); int turn = 13 ; /* Turn On (blinking block cursor) */ void TurnOn () { write(fd,&cmd,1); write(fd,&turn,1); int show = 14; /* Show underline cursor */ void Show () { write(fd,&cmd,1); write(fd,&show,1); NAR-5510 SeriesUser s Manual 60

62 int movel = 16 ; /* Move cursor 1 character left */ void MoveL () { write(fd,&cmd,1); write(fd,&movel,1); int mover = 20 ; /* Move cursor 1 character right */ void MoveR () { write(fd,&cmd,1); write(fd,&mover,1); int scl = 24; /* Scroll cursor 1 character left */ void ScrollL(){ write(fd,&cmd,1); write(fd,&scl,1); int scr = 28; /* Scroll cursor 1 character right */ void ScrollR(){ write(fd,&cmd,1); write(fd,&scr,1); int setdis = 64;/* Command */ void SetDis(){ write(fd,&cmd,1); write(fd,&setdis,1); /* Add or Change Show Message here */ char mes1[] = "Portwell EZIO"; char mes2[] = "*************"; char mes3[] = "Up is selected"; char mes4[] = "Down is selected"; char mes5[] = "Enter is selected"; char mes6[] = "ESC is selected"; char nul[] = " "; int a,b; void ShowMessage (char *str1, char *str2) { a = strlen(str1); b = 40 - a; write(fd,str1,a); write(fd,nul,b); write(fd,str2,strlen(str2)); int main () { SetEnvironment(); /* Set RAW mode */ fd = open("/dev/ttys1",o_rdwr);/** Open Serial port (COM2) */ Init(); /* Initialize EZIO twice */ Init(); Cls(); /* Clear screen */ ShowMessage(mes1,mes2); NAR-5510 SeriesUser s Manual 61

63 while (1) { int res; char buf[255]; SetDis(); ReadKey(); /* sub-routine to send "read key" command */ res = read(fd,buf,255); /* read response from EZIO */ switch(buf[1]) { /* Switch the Read command */ case 0x4D : /* Up Botton was received */ Cls(); ShowMessage(mes1,mes3); /** display "Portwell EZIO" */ break; /** display "Up is selected */ case 0x47 : /** Down Botton was received */ Cls(); ShowMessage(mes1,mes4); /** display "Portwell EZIO" */ break; /** display "Down is selected" */ case 0x4B : /** Enter Botton was received */ Cls(); ShowMessage(mes1,mes5); /** display "Portwell EZIO" */ break; /** display "Enter is selected" */ case 0x4E : /** Escape Botton was received */ Cls(); ShowMessage(mes1,mes6); /** display "Portwell EZIO" */ break; /** display "Escape is selected */ NAR-5510 SeriesUser s Manual 62

64 2.18 GPIO Sample Code /* This Program is to test PPAP-3751 GPIO Port */ /* Programer: John Ma */ #include <stdio.h> #include <conio.h> #include <dos.h> #define GPIO_Base0x480 int main() { union REGS regs; unsigned char i,j; printf("\n PPAP-3751 GPIO TEST PROGRAM R1.00"); /* Initial GPIO Pin, GPO21,23,24,27; GPI34,33,32,28 */ outportb(gpio_base+7, 0xf6); outportb(gpio_base+0x30, 0x07); outportb(gpio_base+0x34, 0x07); /* Test each GPIO */ outportb(gpio_base+0x0e, 0x20); /* GPO21 hi, other Low */ outportb(gpio_base+0x0f, 0x00); i = inportb(gpio_base+0x0f) & 0x10; j = inportb(gpio_base+0x38) & 0x07; if (i!= 0x10 j!= 0x03) { printf("\ngpo21-gpi34 Fail!!!"); exit(1); outportb(gpio_base+0x0e, 0x80); /* GPO23 hi, other Low */ outportb(gpio_base+0x0f, 0x00); i = inportb(gpio_base+0x0f) & 0x10; j = inportb(gpio_base+0x38) & 0x07; if (i!= 0x10 j!= 0x05) { printf("\ngpo23-gpi33 Fail!!!"); exit(1); outportb(gpio_base+0x0e, 0x00); /* GPO24 hi, other Low */ outportb(gpio_base+0x0f, 0x01); i = inportb(gpio_base+0x0f) & 0x10; j = inportb(gpio_base+0x38) & 0x07; if (i!= 0x10 j!= 0x06) { printf("\ngpo24-gpi32 Fail!!!"); exit(1); NAR-5510 SeriesUser s Manual 63

65 outportb(gpio_base+0x0e, 0x00); /* GPO27 hi, other Low */ outportb(gpio_base+0x0f, 0x08); i = inportb(gpio_base+0x0f) & 0x10; j = inportb(gpio_base+0x38) & 0x07; if (i!= 0x00 j!= 0x07) { printf("\ngpo27-gpi28 Fail!!!"); exit(1); printf("\ngpio TEST OK!"); return(0); NAR-5510 SeriesUser s Manual 64

66 Chapter 3 Operation Guide 3.1 Brief Guide of NAR-5510 System Board NAR-5510 System Board is a Communication Appliance computing board based on Intel 915GV chipsets technology. NAR-5510 System Board provides up to eight on-board LAN ports to serve communication applications, such as Firewall, which needs eight Ethernet ports to connect external network (internet), demilitarized zone and internal network. Different I/O management policies can be applied respectively to individual network to achieve the highest security level. The target market segment is communication appliance including Virtual Private Network, Load Balancing, Quality of Service, Intrusion Detection, Virus Detection, Firewall and Voice Over IP. This NAR-5510 system board is utilized with Intel LGA775 Celeron and Intel LGA775 Pentium 4 processors, and 184-pin DIMM up to 2 GB DRAM. The enhanced on-board IDE interface support 2 drives up to PIO mode 4 timing and Ultra DMA/100 synchronous mode feature. The on-board Intel ICH6R chipset integrates two serial ports driven by two high performance 16C550-compatible UARTs to provide 16-byte send/receive FIFOs. In addition, the two Universal Serial Bus ports provide high-speed data communication between peripherals and PC. The on-board flash ROM is used to make the BIOS update easier. The high precision Real Time Clock/Calendar is built to support Y2K for accurate scheduling and storing configuration information. All of these features make NAR-5510 System Board excellent in stand-alone applications. If any of these items is damaged or missing, please contact your vendor and save all packing materials for future replacement and maintenance. Figure 3-1 NAR-5510 System Board NAR-5510 SeriesUser s Manual 65

67 3.2 System Architecture The following illustration of block diagram illustrated basic design reference of NAR-5510, a highly integrated system solution. The most up-to-date system architecture of NAR-5510 includes two main VLSI chips. It contains 915GV and ICH6/ICH6R to support LGA775 Celeron/Pentium 4 processor, DIMM, PCI bus interface, USB port, SMBus communication, Ultra DMA 100 IDE and SATA hard disk. The on-board ICH6R chip supports two UARTs, and hardware monitoring. NAR-5510 System Board has built-in Socket 775 to support Intel LAG775 Celeron/Pentium 4 processor (533 or 800MHz FSB) for cost-effective and high performance application. The 915GV provides a completely integrated solution for the system controller and data path components in a Celeron/Pentium 4 processor system. It provides DDR SDRAM interface with one 184 pin 2.5V DIMM. The ICH6/ICH6R provides a highly integrated multifunction for the best industry applications. It supports Serial ATA controller for four ports, 2-channel dedicated Ultra ATA/33/66/100 IDE master interface, Universal Serial Bus (USB) controllers and PCI-Express v1.0a interfaces. All detailed operating relations are shown in Fig. 3-2 (NAR-5500 System Block Diagram). Super I/O Firmware USB 2.0 SATA LGA775 Socket for P4 / Celeron CPU 915GV GMCH Dual Channel DDR333/400, up to 2GB Optional Cavium CN bit PCI-slot 2x 2.5 HDD w/ RAID0/1 ICH6R Bypass x1 PCI-E Bypass x1 PCI-E x1 PCI-E x1 PCI-E 32b-GbE Intel 82541PI 32b-GbE Intel 82541PI PCI-e GbE Intel 82573L PCI-e GbE Intel 82573L PCI-e GbE Intel 82573L PCI-e GbE Intel 82573L Figure 3-2 NAR-5500 Block Diagram NAR-5510 SeriesUser s Manual 66

68 Appendixes A NAR-5510 Series CPLD Upgrade Procedure 1. Rework equipment 1.1 Host PC with WIN2K O.S. and parallel (printer) port. 1.2 Lattice isplever 4.2 CD 1.3 ISP Downloader, which includes: One parallel port D-sub connector pin Flat cable with two female 8-pin connectors. 2. Software installation: Install ispvm only 3. ISP Downloader set up 3.1 Connect ISP downloader with the host PC via parallel port. To parallel (printer) port on host PC Pin Connect 8-pin connector to JP5 on system board of NAR-5510 series. Note that the red wire shall align with pin-1 of JP5. Pin-1 JP5 4. Upgrade CPLD 4.1 Execute software ispvm 4.2 PPAP-3751 power on 4.3 Click to scan device NAR-5510 SeriesUser s Manual 67

69 4.4 Double click device 4.5 Load p3751bp.jed 4.6 Click Ctr+G or to program NAR-5510 SeriesUser s Manual 68

70 4.7 Program 4.8 Program successful NAR-5510 SeriesUser s Manual 69

71 4.9 Jumper setting checking: ensure JP6 and JP7 are in right position. JP6 JP7 JP6 JP6: LAN BP(Bypass) Power On default mode setting 1-2(default): A normal, LED ON 2-3: A bypass, LED OFF J43/J44 bypass 4-5(default): B normal, LED ON 5-6: B bypass, LED OFF J34/J35 bypass JP7: BP(Bypass) Enable/Disable 1-2: BP A disable 2-3: BP A enable (default) 4-5: BP B disable 5-6: BP B enable (default) 4.10 Sign red point on CPLD 4.11 Modify PCBA revision. NAR-5510 SeriesUser s Manual 70