COMP 181. Prelude. Intermediate representations. Today. Types of IRs. High-level IR. Intermediate representations and code generation

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1 Prelude COMP 181 Intermediate representations and ode generation November, 009 What is this devie? Large Hadron Collider What is a hadron? Subatomi partile made up of quarks bound by the strong fore What is the premier LHC experiment? Finding the Higgs boson First, what is a boson? Elementary partile that arries fore What is the Higgs boson Interats with Higgs field Gives partiles mass Tufts University Computer Siene Today Intermediate representations and ode generation Sanner Parser Intermediate ode generation Semanti heker Bak end Low-level IR High-level IR Intermediate representations IR design affets ompiler speed and apabilities Some important IR properties Ease of generation, manipulation, optimization Size of the representation Level of abstration: level of detail in the IR How lose is IR to soure ode? To the mahine? What kinds of operations are represented? Often, different IRs for different jobs Typially: High-level IR: lose to the soure language Low-level IR: lose to the mahine assembly ode Tufts University Computer Siene 3 Tufts University Computer Siene 4 Types of IRs Three major ategories Strutural s: Trees, DAGs Graph oriented Heavily used in IDEs, language translators Tend to be large Linear Pseudo-ode for an abstrat mahine Level of abstration varies Simple, ompat data strutures Easier to rearrange Hybrid Combination of graphs and linear ode s: 3 address ode Stak mahine ode : Control-flow graph Tufts University Computer Siene 5 High-level IR High-level language onstruts Array aesses, field aesses Complex ontrol flow Loops, onditionals, swith, break, ontinue Proedures: allers and allees Arithmeti and logi operators Inluding things like short-iruit && and Often: tree strutured Arbitrary nesting of expressions and statements Tufts University Computer Siene 6 1

2 Abstrat Syntax Tree AST: parse tree with some intermediate nodes removed x * y What is this representation good for? Interpreters We an reonstrut original soure Program understanding tools Language translators x - * y Direted Ayli Graph A direted ayli graph (DAG) AST with a unique node for eah value z - w / x Why do this? y More ompat (sharing) Enodes redundany * z x - * y w x / Same expression twie means that the ompiler might arrange to evaluate it just one! Tufts University Computer Siene 7 Tufts University Computer Siene 8 Low-level IR Linear stream of abstrat instrutions Instrution: single operation and assignment Must break down high-level onstruts x y op z x y op z op x, y, z : Introdue temps as neessary: alled virtual registers Simple ontrol-flow Label and goto z x * y label1: goto label1 if_goto x, label1 t * y z x - t Jump to label1 if x has non-zero value Tufts University Computer Siene 9 Memory model What kind of storage do variables represent? x y op z Possibilities: Values on the stak Values in global variables Temporaries introdued during lowering Expliit loads and stores We must ompute addresses t1 *p t1 load p move t1, [p] *p t store [p] t move [p], t Tufts University Computer Siene 10 Memory model z x * y Memory operations Often added later, by bak-end Expliitly represent variables t1 * y z x t1 IA3 (Intel x86) %name a register $val a onstant %esp stak pointer 4 (%esp) indiret + offset move -4(%esp), %eax // load y mul $, %eax move -8(%esp), %edx // load x sub %edx, %eax, %ebx // t1 is ebx move %eax, -1(%esp) // store in z Tufts University Computer Siene 11 Stak mahines Originally for stak-based omputers Now, Java VM push x Post-fix notation x * y push push y multiply subtrat What are advantages? Introdued names are impliit, not expliit Simple to generate and exeute ode Compat form who ares about ode size? Embedded systems Systems where ode is transmitted (the Net) Tufts University Computer Siene 1

3 IR Trade-offs for (i0; in; i++) A[i] i; Loop iterations are independent A [ ] i i for i0;in;i++ Loop invariant Strength redue to temp + 4 loop: temp1 &A temp i * 4 temp3 temp1 + temp store [temp3] i... goto loop IR Summary Intermediate representations High-level Rih struture, lose to soure Good for soure-level tools, IDEs : abstrat syntax tree Low-level Linear sequene, lose to the mahine Good for optimization : abstrat mahine ode, byteode Essene of ompilation: Translating from the high-level IR to low-level IR Tufts University Computer Siene 13 Tufts University Computer Siene 14 Towards ode generation if ( 0) { ( 0) { + ; else n * n + ; t1 0 if_goto t1, lab1 t n * n t + goto end lab1: t3 > 0 if_goto t3, end + goto lab1 end: generation Convert from high-level IR to low-level IR HIR is omplex, with nested strutures LIR is low-level, with everything expliit Often alled lowering or linearizing the ode Result is a sequene of LIR instrutions Need a systemati algorithm Idea: Define translation for eah AST node, assuming we an get ode to implement hildren Come up with a sheme to stith them together Reursively desend the AST Tufts University Computer Siene 15 Tufts University Computer Siene 16 Lowering sheme : add expression General sheme template for eah AST node Captures key semantis of eah onstrut Has holes for the hildren of the node Implemented in a funtion alled generate To fill in the template: Call generate funtion reursively on hildren Plug ode into the holes How to stith ode together? Generate returns a temporary that holds the result Emit ode that ombines the results Soure: expr1 + expr + template: AST: expr1 expr ode for expr1> ode for expr> result> expr1> + expr> Flow hart: to ompute expr1 to ompute expr Add results Tufts University Computer Siene 17 Tufts University Computer Siene 18 3

4 : loop Soure: AST: Flow hart: (ond) body; template: ond body top_label: ode for ondition> ifnot_goto ond>, end_label ode for body> goto top_label end_label: to ompute ond Is ond true? for body Exit Tufts University Computer Siene 19 Generation sheme Two problems: Getting the order right How to pass values between the piees of ode Solution: order Append eah instrution to a global buffer Emit instrutions in the desired order Solution: passing values Request a new (unique) temporary variable name Generate ode that omputes value into the temp Return the name of the temp to higher-level generate all Tufts University Computer Siene 0 While loop Compiler: generate(whilenode w) { E new_label() T new_label() emit( $T: ) t generate(w.condition) emit( ifnot_goto $t, $E ) generate(w.body) emit( goto $T ) emit( $E: ) template: top: ode for ondition> ifnot_goto ond>, end ode for body> goto top end: Tufts University Computer Siene 1 Tufts University Computer Siene Lowering expressions Arithmeti operations expr1 op expr expr1 t1 generate(expr1) t generate(expr) r new_temp() emit( r t1 op t ) Return the register to generate all above Tufts University Computer Siene 3 op expr Generate ode for left and right hildren, get the registers holding the results Obtain a fresh register name Emit ode for this operation Lowering sheme Emit funtion Appends low-level abstrat instrutions to a global buffer Order of alls to emit is important! Sheme works for: Binary arithmeti Unary operations Logi operations What about && and? In C and Java, they are shortiruiting Need ontrol flow expr1 expr r t1 op t Tufts University Computer Siene 4 4

5 Short-iruiting Details If expr1 is true, don t eval expr expr1 expr E new_label() r new_temp() t1 generate(expr1) emit( r t1 ) emit( if_goto t1, E ) t generate(expr) emit( r t ) expr1 expr E new_label() r new_temp() t1 generate(expr1) emit( r t1 ) emit( if_goto t1, E ) t generate(expr) emit( r t ) t1 expr1 r t1 if_goto t1, E t expr r t E: t3 L: ifgoto t1 Tufts University Computer Siene 5 Tufts University Computer Siene 6 Helper funtions Short-iruiting && emit() The only funtion that generates instrutions Adds instrutions to end of buffer At the end, buffer ontains ode new_label() Generate a unique label name Does not update ode new_temp() Generate a unique temporary name May require type information (from where?) expr1 && expr && expr1 expr N new_label() E new_label() r new_temp() t1 generate(expr1) emit( r t1 ) emit( if_goto t1, N ) emit( goto E ) emit( N: ) t generate(expr) emit( r t ) Tufts University Computer Siene 7 Tufts University Computer Siene 8 Short-iruiting && Can we do better? Array aess Depends on abstration expr1 && expr && expr1 expr E new_label() r new_temp() t1 generate(expr1) emit( r t1 ) emit( ifnot_goto t1, E ) t generate(expr) emit( r t ) expr1 [ expr ] OR: Emit array op Lower later r new_temp() a generate(expr1) o generate(expr) emit( o o * size ) emit( a a + o ) emit( r load a ) Tufts University Computer Siene 9 Type information from the symbol table Tufts University Computer Siene 30 5

6 Statements Simple sequenes statement1; statement; statementn; Conditionals if (expr) statement; generate(statement1) generate(statementn) E new_label() t generate(expr) Loops Emit label for top of loop Generate ondition and loop body (expr) statement; E new_label() T new_label() t generate(expr) Tufts University Computer Siene 31 Tufts University Computer Siene 3 Funtion all Different alling onventions x f(expr1, expr, ); Why all generate here? a generate(f) foreah expr-i ti generate(expri) emit( push ti ) For loop How does for work? for (expr1; expr; expr3) statement emit( all_jump a ) emit( x get_result ) Tufts University Computer Siene 33 Tufts University Computer Siene 34 Assignment How should we generate x y? Problem Differene between right-side and left-side Right-side: a value r-value Left-side: a loation l-value Speial generate Define speial generate for l-values lgenerate() returns register ontaining address Use lgenerate() for left-side Return r-value for nested assignment : array assignment A[i] B[j] expr1 expr; r generate(expr) l lgenerate(expr1) emit( store *l r ) Store to this loation Load from this loation Tufts University Computer Siene 35 Tufts University Computer Siene 36 6

7 : arrays At leaves : A[i] B[j] Depends on level of abstration Two versions of generate: r new_temp() a generate(arr) o generate(index) emit( o o * size ) emit( a a + o ) emit( r load a ) r-value ase a generate(arr) o generate(index) emit( o o * size ) emit( a a + o ) return a l-value ase generate(v) for variables All virtual registers: return v Strit register mahine: emit( r load &v ) Note: may introdues many temporaries Later: where is storage for v? More speifially: how the does the ompiler set aside spae for v and ompute its address? generate() for onstants Speial ases to avoid r # Tufts University Computer Siene 37 Tufts University Computer Siene 38 Generation: Big piture Reg generate(astnode node) { Reg r; swith (node.getkind()) { ase BIN: t1 generate(node.getleft()); t generate(node.getright()); r new_temp(); emit( r t1 op t ); break; ase NUM: r new_temp(); emit( r node.getvalue() ); break; ase ID: r new_temp(); o symtab.getoffset(node.getid()); emit( r load address of o> ); break; if ( 0) { ( 0) { + ; else n * n + ; if * n n Tufts University Computer Siene 39 Tufts University Computer Siene 40 E new_label() L0 T new_label() L1 t generate(expr) E new_label() L0 T new_label() L1 t generate(expr) Tufts University Computer Siene 41 Tufts University Computer Siene 4 7

8 E new_label() L0 T new_label() L1 t generate(expr) E new_label() L0 T new_label() L1 t generate(expr) R0 load 0 + t1 generate(expr1) t generate(expr) r new_temp() emit( r t1 op t ) 0 + t1 generate(expr1) t generate(expr) r new_temp() emit( r t1 op t ) r new_temp() R0 emit( r load v ) Tufts University Computer Siene 43 Tufts University Computer Siene E new_label() L0 T new_label() L1 t generate(expr) t1 generate(expr1)r0 t generate(expr) r new_temp() emit( r t1 op t ) R0 load 0 + E new_label() L0 T new_label() L1 t generate(expr) t1 generate(expr1)r0 t generate(expr) r new_temp() emit( r t1 op t ) R0 load R1 0 r new_temp() R1 emit( r 0 ) Tufts University Computer Siene 45 Tufts University Computer Siene E new_label() L0 T new_label() L1 t generate(expr) t1 generate(expr1)r0 t generate(expr)r1 r new_temp() R emit( r t1 op t ) R0 load R1 0 R R0 R1 0 + E new_label() L0 T new_label() L1 t generate(expr)r R0 load R1 0 R R0 R1 not_goto R,L0 Tufts University Computer Siene 47 Tufts University Computer Siene 48 8

9 0 + E new_label() L0 T new_label() L1 t generate(expr)r r generate(expr) l lgenerate(expr) emit( store *l r ) R0 load R1 0 R R0 R1 not_goto R,L0 0 + E new_label() L0 T new_label() L1 t generate(expr)r r generate(expr) l lgenerate(expr) emit( store *l r ) t1 generate(expr1)r3 t generate(expr)r4 r new_temp() R5 emit( r t1 op t ) R0 load R1 0 R R0 R1 not_goto R,L0 R3 load R4 R5 R3 + R Tufts University Computer Siene 49 Tufts University Computer Siene E new_label() L0 T new_label() L1 t generate(expr)r r generate(expr)r5 l lgenerate(expr) emit( store *l r ) R0 load R1 0 R R0 R1 not_goto R,L0 R3 load R4 R5 R3 + R 0 + E new_label() L0 T new_label() L1 t generate(expr)r r generate(expr)r5 l lgenerate(expr) emit( store *l r ) r new_temp() R6 emit( r & v ) R0 load R1 0 R R0 R1 not_goto R,L0 R3 load R4 R5 R3 + R R6 & Something like: R6 base + offset Tufts University Computer Siene 51 Tufts University Computer Siene E new_label() L0 T new_label() L1 t generate(expr)r r generate(expr)r5 l lgenerate(expr)r6 emit( store *l r ) R0 load R1 0 R R0 R1 not_goto R,L0 R3 load R4 R5 R3 + R R6 & store [R6]R5 0 + E new_label() L0 T new_label() L1 t generate(expr)r R0 load R1 0 R R0 R1 not_goto R,L0 R3 load R4 R5 R3 + R R6 & store [R6]R5 goto L1 L0: Tufts University Computer Siene 53 Tufts University Computer Siene 54 9

10 if * n n R7 load R8 0 R9 R7 R8 not_goto R9,L3 R0 load R1 0 R R0 R1 not_goto R,L0 R3 load R4 R5 R3 + R R6 & store [R6]R5 goto L1 L0: goto L4 L3: L4: Nesting (0) R7 load R8 0 R9 R7 R8 not_goto R9,L3 R0 load R1 0 R R0 R1 not_goto R,L0 R3 load R4 R5 R3 + R R6 & store [R6]R5 goto L1 L0: goto L4 L3: L4: Tufts University Computer Siene 55 Tufts University Computer Siene 56 quality Are there ways to make this ode better? Many CPUs have a fast 0 test Can use aumulators: + Label leads to another goto; may have multiple labels R7 R8 0 R9 R7 R8 not_goto R9,L3 R0 R1 0 R R0 R1 not_goto R,L0 R3 R4 R5 R3 + R R5 goto L1 L0: goto L4 L3: L4: Effiient lowering Redue number of temporary registers Don t opy variable values unneessarily Aumulate values, when possible Reuse temporaries, where possible Generate more effiient labels Don t generate multiple adjaent labels Avoid goto-label-goto Typially done later, as a separate ontrol-flow optimization Tufts University Computer Siene 57 Tufts University Computer Siene 58 Registers only RISC-like low-level IR In pratie: Assume all variables are in registers Add loads and stores later as part of register alloation R9 0 R7 load R8 0 R9 R7 R8 not_goto R9,L3 R0 load R1 0 R R0 R1 not_goto R,L0 R3 load R4 R5 R3 + R R6 & store [R6]R5 goto L1 L0: goto L4 L3: L4: Avoiding extra opies Basi algorithm Reursive generation traverses to leaves At leaves, generate: R v or R Improvement Stop reursion one level early Chek to see if hildren are leaves Don t all generate reursively on variables, onstants Tufts University Computer Siene 59 Tufts University Computer Siene 60 10

11 Avoiding opies expr1 op expr op v expr1 if (expr1 is-a Var) t1 (Var) expr1 else t1 generate(expr1) if (expr is-a Var) t (Var) expr else t generate(expr) r new_temp() emit( r t1 op t ) Expr1 is (a+b) Not a leaf Reursively generate ode Return temp Expr is Return Emit ( R0 * ) ( a + b ) * R0 a + b R1 R0 * Tufts University Computer Siene 61 Tufts University Computer Siene 6 Use aumulation Idea: We only need registers to evaluate expr1 op expr Reuse temp assigned to one of the subexpressions if (expr1 is var) t1 (Var) expr1 else t1 generate(expr1) if (expr is var) t (Var) expr else t generate(expr) emit( t1 t1 op t ) return t1 Combined: Remove opies Aumulate value Only need one register How many would the original sheme have used? ( a + b ) * R0 a + b R0 R0 * Tufts University Computer Siene 63 Tufts University Computer Siene 64 Reuse of temporaries Reuse of temporaries Idea: Can generate(expr1) and generate(expr) share temporaries? expr1 op expr t1 generate(expr1) t generate(expr) r new_temp() emit( r t1 op t ) Yes, exept for t1 and t Observation: temporaries have a limited lifetime Lifetime onfined to a subtree Subtrees an share registers Algorithm: Use a stak of registers Start at # 0 Eah all to generate: Push next number Use any register > # When done, pop bak up R n-1 op R n R n+ R n+ expr1 expr R# expr1 R# R# op expr Tufts University Computer Siene 65 Tufts University Computer Siene 66 11

12 Misellaneous shape Consider expression x + y + z : t1 x + y t t1 + z What if x 3 and y What if y+z evaluated earlier in ode? Ordering for performane t1 x + z t t1 + y t1 y + z t t1 + x Using assoiativity and ommutativity very hard Operands op1 must be preserved op is omputed Emit ode for more intensive one first Generation Tree-walk algorithm Notie: generates ode for hildren first Effetively, a bottom up algorithm So that means. Right! Use syntax direted translation Can emit LIR ode in produtions Pass register names in $$, $1, $, et. Can generate assembly: one-pass ompiler Triky part: assignment Tufts University Computer Siene 67 Tufts University Computer Siene 68 One-pass ode generation Goal:: Expr:e {: RES e : Expr:: Expr:e + Term:t {: r new_temp(); emit( r e + t ); RES r; : Expr:e Term:t {: r new_temp(); emit( r e - t ); RES r; : Term:: Term:t * Fat:f {: r new_temp(); emit( r t * f ); RES r; : Term:t / Fat:f {: r new_temp(); emit( r t / f ); RES r; : Next time Study the IRs of your ompiler Implementing proedures and methods New programming assignment Fat:: ID:i {: r new_temp(); o symtab.getoffset(i); emit( r load address of o> ); RES r; : NUM:n {: r new_temp(); emit( r $n ); RES r; : Tufts University Computer Siene 69 Tufts University Computer Siene 70 1