Multiple Assignments

Transcription

1 Two Outputs Conneted Together Multiple Assignments Two Outputs Conneted Together if (En1) Q<=D1; xz if (En2) Q<=D2; Multiple Assignment Mutually exlusive means that Q<=D1 and Q<=D2 ould never happen together. If they were both in one if-else statement the ompiler would know they ould never happen together. Here both EN1 and EN2 might be true together. Possible Simulation Results The simulator will hoose one to do first. No one knows whih. The lasting result will be the final one. Possible Synthesis Results The ompiler hooses one result. The ompiler generates two flip-flops and ANDs the result. All outputs my be disonneted. Slide 44 Modified; January 13, 2001 John Knight Vrlg p. 85 Multiple Assignments If both statements are in the same proedure, the En2 would replae the En1 result in zero time. In synthesis this would mean the En2 result would take priority over En1. if (En1) Q=D1; if (En2) Q=D2; Bloking was used for flip flops, to ensures Q=D2 is done after Q=D1 and hene replaes Q=D1. Multiple Assignments If delays are put on the statements simulation ould give a glith. Synthesis would not. It would generate a iruit whih would give EN2 priority. if (En1) #2 Q<=D1; D1 D2 1D Q if (En2) #3 Q<=D2; EN1 C1 EN2 Clk 20. PROBLEM What happens here? if (En1) Q=D1; if (~En1) Q=D1; EN2 has priority over EN1 Comment on Slide 43 Modified; January 13, 2001 John Knight Vrlg p. 86

2 Demux Inferene from ase Using Case Statements Demux Inferene from ase wire [2,0] in; reg [7:0] Y; ase(in) 3 d0: Y=8 b ; 3 d1: Y=8 b ; 3 d2: Y=8 b ; 3 d3: Y=8 b ; 3 d4: Y=8 b ; 3 d5: Y=8 b ; 3 d6: Y=8 b ; 3 d7: Y=8 b ; ase Full Case All ases are overed. It avoids lathes Parallel Case (Mutually Exlusive) No two ases an be ative at one. It an be implemented as a mux. No undefined or parallel ases The ompiler an statially determine that all possible ases are overed. The ompiler an statially determine that no two ases are ative at one. in G DEMU Y [7:0] Comment Slide 45 on Slide 1 Modified; January 13, 2001 John Knight Vrlg p. 87 Multiple Assignment Rae (ont from previous page) Multiple Assignment Rae (ont from 21. PROBLEM What ommon simulation problem might be aused by this ode? wire lok, x, y; reg m,q; lok) : storage q <= m; or x or y) : mux if (lok) m = x; else m = y; ; x y lok 1 0 1D C1 This is a subtle simulation rae. Both the mux and the flip flop respond to lok. The flip flop, as per the rule uses nonbloking assigns. The mux, as per the rule uses bloking assigns. However on posedge lok the simulator might hoose the mux first. Then the mux ode would blok the flip flop until the mux had swithed. The atual iruit would apture the mux value before the lok swithed it. m m q Using Case There are several problems that an happen with ase statement synthesis. 1. If the ase is known to over all the possibilities the input ondition an assume it is said to be a full ase. Unfortunately the synthesizer will not know this unless ase overs all 2 N possibilities for an N bit ondition. If the synthesizer does not know it is a full ase, it will insert lathes. 2. If two different onditions may happen at one, they will ativate two different outputs at the same time. This is alled a nonparallel ase. Comment on Slide 44 Modified; January 13, 2001 John Knight Vrlg p. 88

3 Lath Inferene in Case Lath Inferene in Case Not Obvious Full-Case, Case with a restrited input reg [6:1] Y; or b or ) // if a,b, = 1,1,1 make 1=0 1 = (a&b&)? 0 : ase({a,b,1}) 3 d0: Y=000000; 3 d1: Y=000001; 3 d2: Y=000010; 3 d3: Y=000100; 3 d4: Y=001000; 3 d5: Y=010000; 3 d6: Y=100000; ase Apparent undefined ases 3 d7: Y=000000; a,b, = 1,1,1 annot our. Synthesis does not know that. Thus synthesis will infer 7 lathes. To avoid lathes Put in default d5: Y=010000; 3 d6: Y=100000; default: Y=000000; Better default A better default is: default: Y=xxxxxx; It gives the synthesizer more hoie. Slide 46 Modified; January 13, 2001 John Knight Vrlg p. 89 Not Obvious Full-Case If a ase ontains all 2 n ases no lathes will be generated. Not Obvious Full-Case If it ontains less than 2 n ases, lathes will be generated unless it is very obvious all ases are overed. Synthesizers do not look bak very far to determine if all ases are overed. Use Default The default statement does no harm if it is used and not needed. Always put in a default, whether you need it or not, unless you want the lathes. Plae xxxx as a the Default Output If you know the default will never be seleted by the ase, then you an put in anything you want. The logi that is easiest to minimize is x (don t are). Requiring the default to take some partiular value, like zero, an greatly inrease the size of the iruit. Comment on Slide 45 Modified; January 13, 2001 John Knight Vrlg p. 90

4 Nonparallel Case Nonparallel Case NOT Mutually Exlusive or y or z) ase(1 b1) x: Y=2 b01; y: Y=2 b10; z: Y=2 b11; default: Y=2 bxx; ase FORCE Mutually Exlusive (Parallel) or y or z) ase({x,y,z}) 3'b100: Y=2 b01; 3'b010: Y=2 b10; 3'b100: Y=2 b11; default: Y=2 bxx; ase Not Mutually Exlusive (nonparallel) Case Two ases an be ative at one. Priority enoder generated. x y z Synopsys Compiler Diretive Simulater treats as omments Tells Synopsys x, y and z an never happen at the same time. Designer must enfore this! Fore Parallel Case HPRI / BIN Y[1] Y[0] // synopsys parallel_ase avoids reating a priority enoder ase(1 b1) // synopsys parallel_ase x: Y=2 b01; y: Y=2 b10; z: Y=2 b11; default: Y=2 bxx; ase Not Reommed Slide 47 Modified; January 13, 2001 John Knight Vrlg p. 91 Parallel-Case Parallel-Case Whenever two or more lines of the ase statement may be seleted at one, the simulation exeutes the first line enountered in the listing. This is like a priority enoder. In a parallel ase, the synthesizer assumes some other iruit keeps two lines from being seleted at one. //synopsis diretives an be used to tell the synthesizer to fore a parallel-ase but one an also write the ode to expliitly say what is desired. This latter method is synthesizer indepent and keeps the simultation and synthesis in agreement. Suh ode may require the asex (or asez) ommand desribed on the next slide. Coding for full deoding, priority enoder, or parallel ase Y[1] Y[2] Y[3] Y[1] Y[2] Y[3] Y[1] Y[2] Y[3] or y or z) ase({x,y,z}) 3 b100 : Y=3 b100; 3 b010 : Y=3 b010; 3 b001 : Y=3 b001; default: Y=3 b000; ase Full deoding: Assumes more than one of x, y, z an be 1 and removes those ases. or y or z) asex({x,y,z}) 3 b1xx : Y=3 b001; 3 b01x : Y=3 b010; 3 b001 : Y=3 b001; default: Y=3 b000; ase Priority deoder Assumes more than one of x, y, z an be 1 but takes the first one as orret or y or z) asex({x,y,z}) 3 b1xx : Y=2 b100; 3 bx1x : Y=2 b010; 3 bxx1 : Y=2 b001; default: Y=2 bxxx; ase Parallel ase Assumes only one of x, y, z an be 1 at a time. Deps on some other iruit to enfore this. Comment on Slide 46 Modified; January 13, 2001 John Knight Vrlg p. 92

5 Using asez Using asez Allows Don t Cares In Case-items wire [3,1] in; reg [1:0] Y; always (in) asez(in) //or asex (in) 3 bxx1: Y=2 b01; 3 bx10: Y=2 b10; 3 b100: Y=2 b11; default Y=2 b00; ase Generates a priority enoder xx1 has the highest priority. Default Covers only 3 b000. in[1] in[2] 1n[3] HPRI / BIN Y[1] Y[0] Don t Cares In Right-Hand Side or y or z) ase({x,y,z}) 3 b001: Y=2 b01; 3 b010: Y=2 b10; 3 b100: Y=2 b11; default Y=2 bxx; ase Don t Cares Can Simplify Logi Don t fore the defaults to zero if you don t are. It makes the logi larger. Casez not neessary for output don t ares. asez slightly prefered over asex. Slide 48 Modified; January 13, 2001 John Knight Vrlg p. 93 Casex/asez For simulation Case treats a bit in a variable as having four possible values {0, 1, x, z}, thus x only mathes x, not 1 or 0. Casex treats x, z or? as a don t are whih an math 0, 1, x or z. Casez treats z or? as a don t are whih an math 0, 1, x or z, but x annot math 0 or 1. ase asex asez ase \data 0 1 x z ase \data 0 1 x z ase \data 0 1 x z x x x z,? z,? z,? For example: Given- aa = 3b'1x0; ase (aa) 3 b110:...// No math beause 1 does not math x with a ase statement. 3 b1x0:... // Mathes asex (aa) 3 b110:... // Mathes aa beause 1 does math x with a asex statement. 3 bx10:...// Mathes aa. asez (aa) 3 bxx0:... // x does not math 1 with a asez statement, although x mathes x. 3 bzz0:...// Mathes aa. Casex/asez For synthesis No x values ever propagate in synthesis. However x values in the simulation ause an unex peted math with asex. Using asez will avoid those problems. Don t ares in the outputs are fine for ase, asez or asex. Comment on Slide 47 Modified; January 13, 2001 John Knight Vrlg p. 94

6 Confusion Between Reg and Integer Confusion Between Reg and Integer Integers are 2 s Complement Negative Numbers Integers delarations default to a 32-bit 2 s omplement number. The ompiler will eventually deide how many bits are needed. Reg numbers are nonzero integers The length of registered numbers is given in the delaration. integer B,C; reg [4:0] ; = -5'd7; B = 10; C = B + ; Value of will hold a 5-bit {-7 in 2's omplement} Reg numbers are never negative, Hene is taken as 25. B will hold (32 or less bits) B + = = Did you want 35 or 3? Slide 49 Modified; January 13, 2001 John Knight Vrlg p. 95 Negative Numbers Two s Complement To hange a binary number to its two s omplement Change the exhange the ones and zeros, then add 1, ignore any off- arries from the add {-10 in 2's omplement} Sign Extension All two s ompliment numbers of different lengths must be sign exted when added. Thus: reg [4:0] x ; reg [5:0] y, z; z = {x[4], x} +y ; // sign ext x to 5 bits. If the bits represent unsigned numbers, then do not sign ext. Negative Numbers Comment on Slide 48 Modified; January 13, 2001 John Knight Vrlg p. 96

7 Confusion Between Reg and Integer Using For Loops For Building Iterative Hardware Build an 5-bit ripple-arry adder. reg [4:0] A, B, S; reg, _out; wire _in; // S is the sum, the arry or A or B) = _in; for(i=0; i <=4; i=i+1) {, S[i]} = A[i] + B[i] + ; _out = ; // Conatenate the outputs into a 2-bit vetor. A 4 B 4 A 3 B 3 A 2 B 2 A 1 B 1 A 0 B 0 _out _in S 4 S 3 S 2 S 1 S 0 Slide 50 Modified; January 13, 2001 John Knight Vrlg p. 97 Hardware Loops 1 Loops give multiple opies of a basi instane. The ode in the loop will be synthesized, a different instane for eah iteration. Output leads from one blok, with the same name as an input lead, will onnet between iterations. See the variable in the program. Hardware Loops While loops are partially supported for synthesis. They represent a onditional branh. All while loops must be broken by lok) statement. Thus:- lok) while ( b >9 (posedge lok); // break the zero delay loop b <= b+2; 2 b Add Σ CLK b Register 9 Compare < 1. Palnitakar, Verilog, Prentie Hall, 1998, p..285 Comment on Slide 49 Modified; January 13, 2001 John Knight Vrlg p. 98

8 Confusion Between Reg and Integer An Iterative Comparator Hardware Build an 5-bit omparator from bloks. reg [4:0] A, B; reg x, y; // S is the sum, the arry or B) x=0; y=0; // Above the highest order bit, the two are equal for(i=0; i <=4; i=i+1) x=(a[i] > B[i]) x; // A is larger at this bit or at a higher order bit. y=(b[i] > A[i]) y; // B is larger at this bit or at a higher order bit. 0 0 Y A 4 B 4 = = A 3 B 3 A 2 B 2 A 1 B 1 A 0 B 0 = = = = = = = = Y Y Y Y Y Y Y Y Y S 4 S 3 S 2 S 1 S 0 At the output: x,y = 0,0 means A=B, x,y = 1, 0 means A > B, x,y = 0,1 means A < B, Slide 51 Modified; January 13, 2001 John Knight Vrlg p. 99 Loops to Generate Iterative Ciruits This is an iterative omparator used as a lab in the Swithing Ciruits ourse at Carleton. Loops to Generate Iterative Ciruits It only ompares non-negative integers, where the number with the leftmost 1 is the largest. 22. PROBLEMS a. Write a for loop to alulate the parity of a 6-bit number. It should inludeif (data[i]) OddPar= ~OddPar; b. One way to hange a binary number to its two s omplement is: Start at the right hand side. Leave all bits unhanged until after the first 1 is found. Invert all bits to the left of the initial 1. Thus: 1001_1000 has omplement 0110_1000 Write a loop to generate suh a iruit. Comment on Slide 50n Modified; January 13, 2001 John Knight Vrlg p. 100

9 Confusion Between Reg and Integer Tell The Synthesizer What To Do Complier Diretives Written like omments // synopsys... The simulator will ignore them Direts synthesis. Simplifies some language problems. However it is nearly always possible to avoid them by proper oding. Thus simulation will agree with synthesis only if it was oded properly. Limits you to one ompiler. Makes formal verifiation diffiult. There are many of these ompiler diretives. Chek the Synopsys Manual Example Fore Asynhronous Reset module lath(q,d,c,r); input D,C,R; output Q; reg Q; // synopsys asynh_set_reset R or R) : if (R) Q = 0; else if (C) Q = D; Slide 52 Modified; January 13, 2001 John Knight Vrlg p. 101 Compiler Diretives Other Compiler Diretives // synopsys asyn_set_reset // synopsys syn_set_reset //synopsys asyn_set_reset_loal //synopsys one_hot applies diretive to speified signals in a named blok indiates only one of a list of signals is true at a time. Useful to show set and rest are never both applied at one. Compiler Diretives One of the more useful ompiler diretives is used to fore a partiular library module for arithmeti operations (next slide). Formal verifiation This is where the logi of a program is ompared weith the logi of another program. This is often done after inserting speial strutures only used for testing, or after had optimizations on a ompiled iruit. The verifiation programs have trouble with ompilier assertions. Comment on Slide 51 Modified; January 13, 2001 John Knight Vrlg p. 102

10 Foring Speifi Synopsys Designware Foring Speifi Synopsys Designware Synopsys uses designware to implement ounters, adders, omparators, et. Control the type of funtion used by inserting ompiler diretives into your ode. Example: Library DWO1 has two inrements, ripple arry rpl and arry look-ahead la. Fore the named blok bill to use a arry look-ahead inrementer. : bill //named proedure /* synopsys resoure billspeial: map_to_module = "DW01_in", implementation = "la", ops = "greasedinr"; */ ount = ount + 1; //synopsys label greasedinr Must insert only in a nonloked, named proedure or funtion. i.e not billspeial will be the name given this instantiation. "DW01_in" and "la" are from the Synopsys library DW01 The label applies to the most reently parsed funtion. ount = ount + 1 // synopsys label greasedinr Slide 53 Modified; January 13, 2001 John Knight Vrlg p. 103 Mapping to a Speifi Library Module Named Proedures Mapping to a Speifi Library Module peifially map an operation it must be inside a named proedure. named by writing the name after. or... : bill... Meanings of the mapping labels // synopsys label greasedinr labels the + operation with name greasedinr. This label is bound to the instantiation named billspeial by the ops = greasedin ; statement. The resoure is module DW01_in, in the designware library DW01 The speifi implementation in the library is la. Libraries are fairly automati The simulator will automatially hoose an implementation for your riteria. Experiene with Adders The DW01 library has (1999) had five adders. For a 4 to 7 bit adds in a Viterbi deoder, a Carleton graduate student, Youxing Zhao found: The onditional sum adder (sa) was the fastest 1. The ripple arry adder (rpl) was seond and signifiantly slower. The fast arry look-ahead (lf) was third. The Brent-Kung (bk) and the arry look-ahead adder (la) were last and about the same. 1. A. Bellaouar and M Elmasary, Low-powered Digital VLSI Design Ciruits and Systems, Kluwer 1995, p.424 has a good summary of the sa. Eah full adder alulates (S1,C1) and (S0, C0) whih are the sum and arry for a arry-in of 1 and 0 respetively. Then muxs are used to selet the appropriate answer. Comment on Slide 52 Modified; January 13, 2001 John Knight Vrlg p. 104

11 Guidelies: Guidelies: Summary Partition FSMs into next-state al, outputs and registers. Use <= in the register proedure; use = in the others. In proedures: Feed all right-hand side variables through the trigger list (unless also on the left side.) Make all branhes evaluate all left-hand side variables. If you are using negative numbers, add/sub only registers of equal length, and do sign extensions. Do not have the same left-hand side variable stored in two different proedures. For ase statements: Always use a default at the. Use asez if there are don t ares in the ontrol. Use x for don t are outputs to minimize logi. Flip-flops proedures must lk ) lk or...edge reset) Slide 54 Modified; January 13, 2001 John Knight Vrlg p. 105 Mapping to a Speifi Library Module Comment on Slide 53 Modified; January 13, 2001 John Knight Vrlg p. 106