Getting started. Roel Jordans

Size: px
Start display at page:

Download "Getting started. Roel Jordans"

Transcription

1 Getting started Roel Jordans

2 Goal Translate a program from a high level language into something the processor can execute efficiently So before we start we need to know how this processor executes a program 2

3 Processor architecture by example: AVR

4 AVR CPU core Separate instruction and Data memories All 32 General purpose registers connected to ALU 4 IO Modules connected to Data Bus and accessible via Special Function Registers

5 Memory organization One general purpose register file Two memories Program memory Data memory And some peripherals Memory mapped e.g. IO ports, timers, EEPROM,... 5

6 General purpose registers 32x8-bit registers 16-bit registers formed using pairs of 8 bit registers X, Y, and Z 16-bit registers Can be used for indirect addressing Operation input/output schemes: One 8-bit operand, 8-bit result Two 8-bit operands, 8-bit result Two 8-bit operands, 16-bit result One 16-bit operand, 16-bit result Hardware stack pointer 6

7 Program memory On chip, in system programmable 32K bytes, in 16K 2 byte instructions Accessible via special instructions (LPM,SPM) Bootloader support from boot flash section Contains interrupt vector table Program starts with reset (IRQ0) 7

8 Data memory Registers mapped in SRAM memory space 32 GPR 64 SFR SFR's accessed through in/out instructions (IO registers) 2KB of internal SRAM from address 0x060 Holds the stack! Required for call instruction Stack grows down from the top of memory 8

9 Important information The AVR datasheet Only 448 pages long! Also includes info on the available peripherals Focus on the following sections 6 & 7 for the architecture and memory organization 31 for the instruction-set overview 30 for the special function register Provided on the oncourse website 9

10 Compilation stages

11 Compilation flow overview User-created files Makefile Make Utility C/C++ Source and Header Files Assembly Assembly Source Source Files Files Shared Object File 11 Object Files Archive Utility Library Files Linker Script File Linkable Image File Executable Image File Link Map File

12 12

13 Preprocessor Adds some really useful extra features #include #define #ifdef Also useful for other languages Like the 13

14 The Compilation in three steps AST, IR, Code generation 14

15 An example from C int foo(int a, int b) { return a + b; } 15

16 int foo(int a, int b) { return a + b; } Abstract Syntax Tree (AST) $ clang Xclang ast dump fsyntax only f.c TranslationUnitDecl... TypedefDecl... ` FunctionDecl... <f.c:1:1, line:3:1> line:1:5 foo 'int(int,int)' ParmVarDecl... <col:9, col:13> col:13 used a 'int' ParmVarDecl... <col:16, col:20> col:20 used b 'int' ` CompoundStmt... <col:23, line:3:1> ` ReturnStmt... <line:2:2, col:11> ` BinaryOperator... 'int' '+' ImplicitCastExpr... 'int' <LValueToRValue> ` DeclRefExpr... 'int' lvalue ParmVar... 'a' 'int' ` ImplicitCastExpr... 'int' <LValueToRValue> ` DeclRefExpr... 'int' lvalue ParmVar... 'b' 'int' 16

17 AST Tools Direct translation back to C Code formatting with clang-format AST analysis clang-check Buffer checking C code clang-tidy Cleans up common programming mistakes Transforming AST Source-to-source transformations clang-modernize Update code to use newer language features 17

18 int foo(int a, int b) { return a + b; } Intermediate Representation (IR) $ clang target=avr emit llvm S f.c ; ModuleID = 'f.c' target datalayout = "..." target triple = "avr unknown unknown" ; Function Attrs: nounwind define %a, i16 %b) #0 { %1 = alloca i16, align 2 %2 = alloca i16, align 2 store i16 %a, i16* %1, align 2 store i16 %b, i16* %2, align 2 %3 = load i16* %1, align 2 %4 = load i16* %2, align 2 %5 = add nsw i16 %3, %4 ret i16 %5 } 18

19 IR optimizations Code simplification Dead-code elimination (DCE) Common sub-expression elimination (CSE) Code analysis Alias analysis Control-flow analysis Code transformation Loop transformation Auto vectorization 19

20 int foo(int a, int b) { return a + b; } Enabling IR optimizations $ opt S O1 f.ll o f.opt.ll ; ModuleID = 'f.ll' target datalayout = "..." target triple = "avr unknown unknown" ; Function Attrs: nounwind define %a, i16 %b) #0 { %add = add nsw i16 %a, %b ret i16 %add } 20

21 int foo(int a, int b) { return a + b; } CodeGen $ llc f.opt.ll.text.file.globl.align.type "f.opt.ll" foo 2 foo,@function foo: ; BB#0: add adc ret.lfunc_end0:.size ; %entry r24, r22 r25, r23 foo,.lfunc_end0 foo 21

22 The From human readable to executable Produces object files Usually in ELF or COFF format 22

23 Executable and Linkable Format Contains the binary data for the processor Code & Data Optionally contains extra information Debug information Symbol tables Relocation information 23

24 Linux Executable ELF files The Executable ELF files produced by the Linux linker are configured for execution in a private virtual address space, whereby every program gets loaded at the identical virtual memory-address 24

25 Executable versus Linkable ELF Header ELF Header Program-Header Table (optional) Program-Header Table Section 1 Data Segment 1 Data Section 2 Data Segment 2 Data Section 3 Data Segment 3 Data Section n Data Segment n Data Section-Header Table Section-Header Table (optional) Linkable File Executable File 25

26 Role of the Linker ELF Header ELF Header Section 1 Data Section 2 Data Program-Header Table Section n Data Segment 1 Data Section-Header Table Segment 2 Data Linkable File ELF Header Segment n Data Section 1 Data Section 2 Data Executable File Section n Data Section-Header Table Linkable File 26

27 The linker Controllable by a linker script Default provided for simple architectures Required when the mapping of sections to memories becomes more complex Multiple data memories Moving code around at runtime Fat binaries: supporting multiple architectures Encrypted binaries 27

28 C runtime Initializing the processor What happens before and after main Setting up the stack Calling main Stopping execution 28

29 To summarize User-created files Makefile Make Utility C/C++ Source and Header Files Assembly Assembly Source Source Files Files Archive Utility Library Files Shared Object File 29 Linker Script File Object Files Linkable Executable The driver Image File Image File Link Map File

30 The driver Many different tools in the compilation process Mostly useful when debugging the Needs simple interface The frontend program (clang) can actually call the right programs for you! 30

31 PCP Assignment 1: AVR backend

32 The application

33 Overview Practice makes perfect Assignments on the ES group servers 33 Login information can be found on oncourse.tue.nl Password distributed in My grades Start with Tool setup Download and follow the assignment instructions Answer the Assignment 1.A quiz questions on oncourse

34 Bonus exercise 1 Make (or Makefiles) As mentioned earlier in this lecture Manages compilation steps Very useful to know (Ab)used for many other purposes Also available on oncourse Take home exercise with questions online Try to automate the build process of assignment 1

35

36 Acknowledgements These slides were partially based on the following:

Compilation process. How a program is born

Compilation process. How a program is born Compilation process How a program is born CocoaHeads Berlin, 2015 > whoami Twitter: @1101_debian Github: @AlexDenisov Freenode: AlexDenisov Outline Compilation process LLVM/Clang Q & A Compilation Process

More information

Lecture 3 Overview of the LLVM Compiler

Lecture 3 Overview of the LLVM Compiler Lecture 3 Overview of the LLVM Compiler Jonathan Burket Special thanks to Deby Katz, Gennady Pekhimenko, Olatunji Ruwase, Chris Lattner, Vikram Adve, and David Koes for their slides The LLVM Compiler Infrastructure

More information

Lecture 2 Overview of the LLVM Compiler

Lecture 2 Overview of the LLVM Compiler Lecture 2 Overview of the LLVM Compiler Abhilasha Jain Thanks to: VikramAdve, Jonathan Burket, DebyKatz, David Koes, Chris Lattner, Gennady Pekhimenko, and Olatunji Ruwase, for their slides The LLVM Compiler

More information

Magic Behind Xcode. Compilation

Magic Behind Xcode. Compilation Magic Behind Xcode Compilation Mobile Warsaw, 2015 > whoami Twitter: @1101_debian Github: @AlexDenisov Freenode: AlexDenisov Blog: http://lowlevelbits.org Outline Compilation process LLVM/Clang Q & A Compilation

More information

A VA R I A B I L I T Y- AWA R E F E AT U R E - R E G I O N A N A LY Z E R I N L LV M. florian sattler

A VA R I A B I L I T Y- AWA R E F E AT U R E - R E G I O N A N A LY Z E R I N L LV M. florian sattler A VA R I A B I L I T Y- AWA R E F E AT U R E - R E G I O N A N A LY Z E R I N L LV M florian sattler Master Thesis Chair of Software Engineering Department of Informatics and Mathematics University of

More information

15-411: LLVM. Jan Hoffmann. Substantial portions courtesy of Deby Katz

15-411: LLVM. Jan Hoffmann. Substantial portions courtesy of Deby Katz 15-411: LLVM Jan Hoffmann Substantial portions courtesy of Deby Katz and Gennady Pekhimenko, Olatunji Ruwase,Chris Lattner, Vikram Adve, and David Koes Carnegie What is LLVM? A collection of modular and

More information

Introduction to LLVM. UG3 Compiling Techniques Autumn 2018

Introduction to LLVM. UG3 Compiling Techniques Autumn 2018 Introduction to LLVM UG3 Compiling Techniques Autumn 2018 Contact Information Instructor: Aaron Smith Email: aaron.l.smith@ed.ac.uk Office: IF 1.29 TA for LLVM: Andrej Ivanis Email: andrej.ivanis@ed.ac.uk

More information

Laboratory: Introduction to Mechatronics. Instructor TA: Edgar Martinez Soberanes Lab 2. PIC and Programming

Laboratory: Introduction to Mechatronics. Instructor TA: Edgar Martinez Soberanes Lab 2. PIC and Programming Laboratory: Introduction to Mechatronics Instructor TA: Edgar Martinez Soberanes (eem370@mail.usask.ca) 2015-01-12 Lab 2. PIC and Programming Lab Sessions Lab 1. Introduction Read manual and become familiar

More information

Assignment 1c: Compiler organization and backend programming

Assignment 1c: Compiler organization and backend programming Assignment 1c: Compiler organization and backend programming Roel Jordans 2016 Organization Welcome to the third and final part of assignment 1. This time we will try to further improve the code generation

More information

2012 LLVM Euro - Michael Spencer. lld. Friday, April 13, The LLVM Linker

2012 LLVM Euro - Michael Spencer. lld. Friday, April 13, The LLVM Linker lld Friday, April 13, 2012 The LLVM Linker What is lld? A system linker Produce final libraries and executables, no other tools or runtime required Understands platform ABI What is lld? A system linker

More information

ME 475 Lab2 Introduction of PIC and Programming. Instructor: Zhen Wang

ME 475 Lab2 Introduction of PIC and Programming. Instructor: Zhen Wang ME 475 Lab2 Introduction of PIC and Programming Instructor: Zhen Wang 2013.1.25 Outline Lecture Introduction of PIC microcontroller Programming cycle Read CH5 Programming guidelines Read CH6 Sample program

More information

LLVM and IR Construction

LLVM and IR Construction LLVM and IR Construction Fabian Ritter based on slides by Christoph Mallon and Johannes Doerfert http://compilers.cs.uni-saarland.de Compiler Design Lab Saarland University 1 Project Progress source code

More information

e-pg Pathshala Subject : Computer Science Paper: Embedded System Module: Embedded Software Development Tools Module No: CS/ES/36 Quadrant 1 e-text

e-pg Pathshala Subject : Computer Science Paper: Embedded System Module: Embedded Software Development Tools Module No: CS/ES/36 Quadrant 1 e-text e-pg Pathshala Subject : Computer Science Paper: Embedded System Module: Embedded Software Development Tools Module No: CS/ES/36 Quadrant 1 e-text In this module, we will discuss about the host and target

More information

Skip the FFI! Embedding Clang for C Interoperability. Jordan Rose Compiler Engineer, Apple. John McCall Compiler Engineer, Apple

Skip the FFI! Embedding Clang for C Interoperability. Jordan Rose Compiler Engineer, Apple. John McCall Compiler Engineer, Apple Skip the FFI! Embedding Clang for C Interoperability Jordan Rose Compiler Engineer, Apple John McCall Compiler Engineer, Apple Problem Problem Languages don t exist in a vacuum Problem Languages don t

More information

Static Analysis for C++ with Phasar

Static Analysis for C++ with Phasar Static Analysis for C++ with Phasar Philipp Schubert philipp.schubert@upb.de Ben Hermann ben.hermann@upb.de Eric Bodden eric.bodden@upb.de Who are we? Philipp Schubert Chief Developer of PHASAR Teaches

More information

MICROPROCESSOR BASED SYSTEM DESIGN

MICROPROCESSOR BASED SYSTEM DESIGN MICROPROCESSOR BASED SYSTEM DESIGN Lecture 5 Xmega 128 B1: Architecture MUHAMMAD AMIR YOUSAF VON NEUMAN ARCHITECTURE CPU Memory Execution unit ALU Registers Both data and instructions at the same system

More information

Better signal handling with Clang. Alpha Abdoulaye. Introduction. Issues. Clang. EPITA Systems/Security Laboratory (LSE) November 14, 2017

Better signal handling with Clang. Alpha Abdoulaye. Introduction. Issues. Clang. EPITA Systems/Security Laboratory (LSE) November 14, 2017 EPITA Systems/Security Laboratory (LSE) November 14, 2017 1 / 19 2 / 19 Signals 101 (1/4) static void handler(int signum) { char test[] = "TEST\n"; write(stdout_fileno, test, sizeof(test)); int main(void)

More information

Tutorial: Building a backend in 24 hours. Anton Korobeynikov

Tutorial: Building a backend in 24 hours. Anton Korobeynikov Tutorial: Building a backend in 24 hours Anton Korobeynikov anton@korobeynikov.info Outline 1. From IR to assembler: codegen pipeline 2. MC 3. Parts of a backend 4. Example step-by-step The Pipeline LLVM

More information

Microcontroller systems Lec 2 PIC18LF8722 Microcontroller s s core

Microcontroller systems Lec 2 PIC18LF8722 Microcontroller s s core TKT-3500 Microcontroller systems Lec 2 PIC18LF8722 Microcontroller s s core Erno Salminen Copyright notice Some figures by Robert Reese, from supplementary CD of the course book from PIC18F8722 Family

More information

Assembler. Lecture 8 CS301

Assembler. Lecture 8 CS301 Assembler Lecture 8 CS301 Discussion Given the following function header, int foo(int a, int b); what will be on the stack before any of the calculations in foo are performed? Assume foo() calls some other

More information

AVR Microcontrollers Architecture

AVR Microcontrollers Architecture ก ก There are two fundamental architectures to access memory 1. Von Neumann Architecture 2. Harvard Architecture 2 1 Harvard Architecture The term originated from the Harvard Mark 1 relay-based computer,

More information

naïve GPU kernels generation from Fortran source code Dmitry Mikushin

naïve GPU kernels generation from Fortran source code Dmitry Mikushin KernelGen naïve GPU kernels generation from Fortran source code Dmitry Mikushin Contents Motivation and target Assembling our own toolchain: schemes and details Toolchain usecase: sincos example Development

More information

Low-Level Essentials for Understanding Security Problems Aurélien Francillon

Low-Level Essentials for Understanding Security Problems Aurélien Francillon Low-Level Essentials for Understanding Security Problems Aurélien Francillon francill@eurecom.fr Computer Architecture The modern computer architecture is based on Von Neumann Two main parts: CPU (Central

More information

Lecture 3 Overview of the LLVM Compiler

Lecture 3 Overview of the LLVM Compiler LLVM Compiler System Lecture 3 Overview of the LLVM Compiler The LLVM Compiler Infrastructure - Provides reusable components for building compilers - Reduce the time/cost to build a new compiler - Build

More information

ECE 471 Embedded Systems Lecture 6

ECE 471 Embedded Systems Lecture 6 ECE 471 Embedded Systems Lecture 6 Vince Weaver http://web.eece.maine.edu/~vweaver vincent.weaver@maine.edu 17 September 2018 Announcements HW#2 was posted, it is due Friday 1 Homework #1 Review Characteristics

More information

CS399 New Beginnings. Jonathan Walpole

CS399 New Beginnings. Jonathan Walpole CS399 New Beginnings Jonathan Walpole Memory Management Memory Management Memory a linear array of bytes - Holds O.S. and programs (processes) - Each cell (byte) is named by a unique memory address Recall,

More information

Porting OpenVMS to x Update

Porting OpenVMS to x Update Porting OpenVMS to x86-64 Update October 16, 2015 Porting OpenVMS to x86-64 Update This information contains forward looking statements and is provided solely for your convenience. While the information

More information

Getting started with LLVM using Swift. Alex Denisov,

Getting started with LLVM using Swift. Alex Denisov, Getting started with LLVM using Swift Alex Denisov, http://lowlevelbits.org whoami ios Apps Developer Compiler Hobbyist Internet User: https://twitter.com/1101_debian https://github.com/alexdenisov http://lowlevelbits.org

More information

Intel x86 instruction set architecture

Intel x86 instruction set architecture Intel x86 instruction set architecture Graded assignment: hand-written resolution of exercise II 2) The exercises on this tutorial are targeted for the as86 assembler. This program is available in the

More information

EE 308: Microcontrollers

EE 308: Microcontrollers EE 308: Microcontrollers Introduction Aly El-Osery Electrical Engineering Department New Mexico Institute of Mining and Technology Socorro, New Mexico, USA January 6, 2018 Aly El-Osery (NMT) EE 308: Microcontrollers

More information

LLVM & LLVM Bitcode Introduction

LLVM & LLVM Bitcode Introduction LLVM & LLVM Bitcode Introduction What is LLVM? (1/2) LLVM (Low Level Virtual Machine) is a compiler infrastructure Written by C++ & STL History The LLVM project started in 2000 at the University of Illinois

More information

Lec 13: Linking and Memory. Kavita Bala CS 3410, Fall 2008 Computer Science Cornell University. Announcements

Lec 13: Linking and Memory. Kavita Bala CS 3410, Fall 2008 Computer Science Cornell University. Announcements Lec 13: Linking and Memory Kavita Bala CS 3410, Fall 2008 Computer Science Cornell University PA 2 is out Due on Oct 22 nd Announcements Prelim Oct 23 rd, 7:30-9:30/10:00 All content up to Lecture on Oct

More information

CSE 401/M501 Compilers

CSE 401/M501 Compilers CSE 401/M501 Compilers x86-64, Running MiniJava, Basic Code Generation and Bootstrapping Hal Perkins Autumn 2018 UW CSE 401/M501 Autumn 2018 M-1 Running MiniJava Programs To run a MiniJava program Space

More information

Exercise Session 7 Computer Architecture and Systems Programming

Exercise Session 7 Computer Architecture and Systems Programming Systems Group Department of Computer Science ETH Zürich Exercise Session 7 Computer Architecture and Systems Programming Herbstsemester 2014 Review of last week s excersice structs / arrays in Assembler

More information

Lab Work Playing with Dot 1

Lab Work Playing with Dot 1 Lab Work Playing with Dot 1 Name: ID: 1. This question refers to the program below 2 : char* s = "My string"; if (argc % 2) { s[0] = m ; printf("[%s]\n", s); Assuming the program is stored in a file file1.c,

More information

W4118: PC Hardware and x86. Junfeng Yang

W4118: PC Hardware and x86. Junfeng Yang W4118: PC Hardware and x86 Junfeng Yang A PC How to make it do something useful? 2 Outline PC organization x86 instruction set gcc calling conventions PC emulation 3 PC board 4 PC organization One or more

More information

C compiler. Memory map. Program in RAM

C compiler. Memory map. Program in RAM C compiler. Memory map. Program in RAM Sections:.text: Program code. Read only 0x40001fff stack.rodata: constants (constmodifier) and strings. Read only.data: Initialized global and static variables (startup

More information

Chapter. Overview. Tornado BSP Training Workshop Copyright Wind River Systems 1-1 Wind River Systems

Chapter. Overview. Tornado BSP Training Workshop Copyright Wind River Systems 1-1 Wind River Systems Chapter 1 Overview Tornado BSP Training Workshop Copyright 1-1 Overview 1.1 Integration Issues VxWorks Boot Sequence Tornado Directory Structure Conventions and Validation Tornado BSP Training Workshop

More information

6.035 Project 3: Unoptimized Code Generation. Jason Ansel MIT - CSAIL

6.035 Project 3: Unoptimized Code Generation. Jason Ansel MIT - CSAIL 6.035 Project 3: Unoptimized Code Generation Jason Ansel MIT - CSAIL Quiz Monday 50 minute quiz Monday Covers everything up to yesterdays lecture Lexical Analysis (REs, DFAs, NFAs) Syntax Analysis (CFGs,

More information

ECE 598 Advanced Operating Systems Lecture 2

ECE 598 Advanced Operating Systems Lecture 2 ECE 598 Advanced Operating Systems Lecture 2 Vince Weaver http://www.eece.maine.edu/~vweaver vincent.weaver@maine.edu 15 January 2015 Announcements Update on room situation (shouldn t be locked anymore,

More information

ECE 471 Embedded Systems Lecture 5

ECE 471 Embedded Systems Lecture 5 ECE 471 Embedded Systems Lecture 5 Vince Weaver http://web.eece.maine.edu/~vweaver vincent.weaver@maine.edu 13 September 2016 HW#2 is due Thursday It is going OK? Announcements 1 Homework #1 Review Characteristics

More information

LLVM IR Code Generations Inside YACC. Li-Wei Kuo

LLVM IR Code Generations Inside YACC. Li-Wei Kuo LLVM IR Code Generations Inside YACC Li-Wei Kuo LLVM IR LLVM code representation In memory compiler IR (Intermediate Representation) On-disk bitcode representation (*.bc) Human readable assembly language

More information

CSE 410. Operating Systems

CSE 410. Operating Systems CSE 410 Operating Systems Handout: syllabus 1 Today s Lecture Course organization Computing environment Overview of course topics 2 Course Organization Course website http://www.cse.msu.edu/~cse410/ Syllabus

More information

Building Binary Optimizer with LLVM

Building Binary Optimizer with LLVM Building Binary Optimizer with LLVM Maksim Panchenko maks@fb.com BOLT Binary Optimization and Layout Tool Built in less than 6 months x64 Linux ELF Runs on large binary (HHVM, non-jitted part) Improves

More information

Compilers Crash Course

Compilers Crash Course Compilers Crash Course Prof. Michael Clarkson CSci 6907.85 Spring 2014 Slides Acknowledgment: Prof. Andrew Myers (Cornell) What are Compilers? Translators from one representation of program code to another

More information

Summer 2003 Lecture 14 07/02/03

Summer 2003 Lecture 14 07/02/03 Summer 2003 Lecture 14 07/02/03 LAB 6 Lab 6 involves interfacing to the IBM PC parallel port Use the material on wwwbeyondlogicorg for reference This lab requires the use of a Digilab board Everyone should

More information

Computer Hardware Requirements for ERTSs: Microprocessors & Microcontrollers

Computer Hardware Requirements for ERTSs: Microprocessors & Microcontrollers Lecture (4) Computer Hardware Requirements for ERTSs: Microprocessors & Microcontrollers Prof. Kasim M. Al-Aubidy Philadelphia University-Jordan DERTS-MSc, 2015 Prof. Kasim Al-Aubidy 1 Lecture Outline:

More information

Generation. representation to the machine

Generation. representation to the machine Unoptimized i Code Generation From the intermediate representation to the machine code 5 Outline Introduction Machine Language Overview of a modern processor Memory Layout Procedure Abstraction Procedure

More information

ELC4438: Embedded System Design ARM Cortex-M Architecture II

ELC4438: Embedded System Design ARM Cortex-M Architecture II ELC4438: Embedded System Design ARM Cortex-M Architecture II Liang Dong Electrical and Computer Engineering Baylor University Memory system The memory systems in microcontrollers often contain two or more

More information

Plan for Today. Concepts. Next Time. Some slides are from Calvin Lin s grad compiler slides. CS553 Lecture 2 Optimizations and LLVM 1

Plan for Today. Concepts. Next Time. Some slides are from Calvin Lin s grad compiler slides. CS553 Lecture 2 Optimizations and LLVM 1 Plan for Today Quiz 2 How to automate the process of performance optimization LLVM: Intro to Intermediate Representation Loops as iteration spaces Data-flow Analysis Intro Control-flow graph terminology

More information

Outline: System Development and Programming with the ADSP-TS101 (TigerSHARC)

Outline: System Development and Programming with the ADSP-TS101 (TigerSHARC) Course Name: Course Number: Course Description: Goals/Objectives: Pre-requisites: Target Audience: Target Duration: System Development and Programming with the ADSP-TS101 (TigerSHARC) This is a practical

More information

TKT-3500 Microcontroller systems

TKT-3500 Microcontroller systems TKT-3500 Microcontroller systems Lec 2 PIC18LF8722 Microcontroller s core Teemu Laukkarinen Department of Computer Systems Tampere University of Technology Fall 2011 Copyright Tampere University of Technology

More information

The Instruction Set. Chapter 5

The Instruction Set. Chapter 5 The Instruction Set Architecture Level(ISA) Chapter 5 1 ISA Level The ISA level l is the interface between the compilers and the hardware. (ISA level code is what a compiler outputs) 2 Memory Models An

More information

Here to take you beyond. ECEP Course syllabus. Emertxe Information Technologies ECEP course syllabus

Here to take you beyond. ECEP Course syllabus. Emertxe Information Technologies ECEP course syllabus Here to take you beyond ECEP Course syllabus Module: 1/6 Module name: Linux Systems To get familiar with Linux Operating system Commands, tools and editors Enable you to write Shell scripts To understand

More information

Microprocessors. Microprocessors and rpeanut. Memory. Eric McCreath

Microprocessors. Microprocessors and rpeanut. Memory. Eric McCreath Microprocessors Microprocessors and rpeanut Eric McCreath There are many well known microprocessors: Intel x86 series, Pentium, Celeron, Xeon, etc. AMD Opteron, Intel Itanium, Motorola 680xx series, PowerPC,

More information

Microprocessors and rpeanut. Eric McCreath

Microprocessors and rpeanut. Eric McCreath Microprocessors and rpeanut Eric McCreath Microprocessors There are many well known microprocessors: Intel x86 series, Pentium, Celeron, Xeon, etc. AMD Opteron, Intel Itanium, Motorola 680xx series, PowerPC,

More information

REFLECTIONS ON TRUSTING BITCODE

REFLECTIONS ON TRUSTING BITCODE ITSECX - @FREDERICJACOBS REFLECTIONS ON TRUSTING BITCODE 2 INTRO ~ WHOIS FREDERIC icepa Signal Both Open-Source Software INTRO 3 Talk based on blog post HTTPS://MEDIUM.COM/@FREDERICJACOBS/WHY-I-M-NOT-ENABLING-BITCODE-F35CD8FBFCC5

More information

EE 354 Fall 2015 Lecture 1 Architecture and Introduction

EE 354 Fall 2015 Lecture 1 Architecture and Introduction EE 354 Fall 2015 Lecture 1 Architecture and Introduction Note: Much of these notes are taken from the book: The definitive Guide to ARM Cortex M3 and Cortex M4 Processors by Joseph Yiu, third edition,

More information

ARM Processors for Embedded Applications

ARM Processors for Embedded Applications ARM Processors for Embedded Applications Roadmap for ARM Processors ARM Architecture Basics ARM Families AMBA Architecture 1 Current ARM Core Families ARM7: Hard cores and Soft cores Cache with MPU or

More information

An Overview to Compiler Design. 2008/2/14 \course\cpeg421-08s\topic-1a.ppt 1

An Overview to Compiler Design. 2008/2/14 \course\cpeg421-08s\topic-1a.ppt 1 An Overview to Compiler Design 2008/2/14 \course\cpeg421-08s\topic-1a.ppt 1 Outline An Overview of Compiler Structure Front End Middle End Back End 2008/2/14 \course\cpeg421-08s\topic-1a.ppt 2 Reading

More information

Adventures in Fuzzing Instruction Selection. 1 EuroLLVM 2017 Justin Bogner

Adventures in Fuzzing Instruction Selection. 1 EuroLLVM 2017 Justin Bogner Adventures in Fuzzing Instruction Selection 1 EuroLLVM 2017 Justin Bogner Overview Hardening instruction selection using fuzzers Motivated by Global ISel Leveraging libfuzzer to find backend bugs Techniques

More information

ebpf-based tracing tools under 32 bit architectures

ebpf-based tracing tools under 32 bit architectures Linux Plumbers Conference 2018 ebpf-based tracing tools under 32 bit architectures Maciej Słodczyk Adrian Szyndela Samsung R&D Institute Poland

More information

CS 107 Lecture 18: GCC and Make

CS 107 Lecture 18: GCC and Make S 107 Lecture 18: G and Make Monday, March 12, 2018 omputer Systems Winter 2018 Stanford University omputer Science Department Lecturers: Gabbi Fisher and hris hute Today's Topics 1. What really happens

More information

Connecting the EDG front-end to LLVM. Renato Golin, Evzen Muller, Jim MacArthur, Al Grant ARM Ltd.

Connecting the EDG front-end to LLVM. Renato Golin, Evzen Muller, Jim MacArthur, Al Grant ARM Ltd. Connecting the EDG front-end to LLVM Renato Golin, Evzen Muller, Jim MacArthur, Al Grant ARM Ltd. 1 Outline Why EDG Producing IR ARM support 2 EDG Front-End LLVM already has two good C++ front-ends, why

More information

LDC: The LLVM-based D Compiler

LDC: The LLVM-based D Compiler LDC: The LLVM-based D Compiler Using LLVM as backend for a D compiler Kai Nacke 02/02/14 LLVM devroom @ FOSDEM 14 Agenda Brief introduction to D Internals of the LDC compiler Used LLVM features Possible

More information

Please refer to the turn-in procedure document on the website for instructions on the turn-in procedure.

Please refer to the turn-in procedure document on the website for instructions on the turn-in procedure. 1 CSE 131 Winter 2013 Compiler Project #2 -- Code Generation Due Date: Friday, March 15 th 2013 @ 11:59pm Disclaimer This handout is not perfect; corrections may be made. Updates and major clarifications

More information

ECE 471 Embedded Systems Lecture 16

ECE 471 Embedded Systems Lecture 16 ECE 471 Embedded Systems Lecture 16 Vince Weaver http://web.eece.maine.edu/~vweaver vincent.weaver@maine.edu 6 October 2017 Midterm will be graded Don t forget HW#5 Announcements MEMSYS wrapup. Academia,

More information

AVR ISA & AVR Programming (I) Lecturer: Sri Parameswaran Notes by: Annie Guo

AVR ISA & AVR Programming (I) Lecturer: Sri Parameswaran Notes by: Annie Guo AVR ISA & AVR Programming (I) Lecturer: Sri Parameswaran Notes by: Annie Guo 1 Lecture Overview AVR ISA AVR Instructions & Programming (I) Basic construct implementation 2 Atmel AVR 8-bit RISC architecture

More information

Chapter 2 Sections 1 8 Dr. Iyad Jafar

Chapter 2 Sections 1 8 Dr. Iyad Jafar Introducing the PIC 16 Series and the 16F84A Chapter 2 Sections 1 8 Dr. Iyad Jafar Outline Overview of the PIC 16 Series An Architecture Overview of the 16F84A The 16F84A Memory Organization Memory Addressing

More information

EE 308: Microcontrollers

EE 308: Microcontrollers EE 308: Microcontrollers AVR Architecture Aly El-Osery Electrical Engineering Department New Mexico Institute of Mining and Technology Socorro, New Mexico, USA January 23, 2018 Aly El-Osery (NMT) EE 308:

More information

FIFTH SEMESTER DIPLOMA EXAMINATION IN ENGINEERING/ TECHNOLOGY-MARCH 2014 EMBEDDED SYSTEMS (Common for CT,CM) [Time: 3 hours] (Maximum marks : 100)

FIFTH SEMESTER DIPLOMA EXAMINATION IN ENGINEERING/ TECHNOLOGY-MARCH 2014 EMBEDDED SYSTEMS (Common for CT,CM) [Time: 3 hours] (Maximum marks : 100) (Revision-10) FIFTH SEMESTER DIPLOMA EXAMINATION IN ENGINEERING/ TECHNOLOGY-MARCH 2014 EMBEDDED SYSTEMS (Common for CT,CM) [Time: 3 hours] (Maximum marks : 100) PART-A (Maximum marks : 10) I. Answer all

More information

Baggy bounds with LLVM

Baggy bounds with LLVM Baggy bounds with LLVM Anton Anastasov Chirantan Ekbote Travis Hance 6.858 Project Final Report 1 Introduction Buffer overflows are a well-known security problem; a simple buffer-overflow bug can often

More information

Development Tools. 8-Bit Development Tools. Development Tools. AVR Development Tools

Development Tools. 8-Bit Development Tools. Development Tools. AVR Development Tools Development Tools AVR Development Tools This section describes some of the development tools that are available for the 8-bit AVR family. Atmel AVR Assembler Atmel AVR Simulator IAR ANSI C-Compiler, Assembler,

More information

L2 - C language for Embedded MCUs

L2 - C language for Embedded MCUs Formation C language for Embedded MCUs: Learning how to program a Microcontroller (especially the Cortex-M based ones) - Programmation: Langages L2 - C language for Embedded MCUs Learning how to program

More information

McSema: Static Translation of X86 Instructions to LLVM

McSema: Static Translation of X86 Instructions to LLVM McSema: Static Translation of X86 Instructions to LLVM ARTEM DINABURG, ARTEM@TRAILOFBITS.COM ANDREW RUEF, ANDREW@TRAILOFBITS.COM About Us Artem Security Researcher blog.dinaburg.org Andrew PhD Student,

More information

Embedded Systems. Software Development & Education Center. (Design & Development with Various µc)

Embedded Systems. Software Development & Education Center. (Design & Development with Various µc) Software Development & Education Center Embedded Systems (Design & Development with Various µc) Module 1: Embedded C Programming INTRODUCTION TO EMBEDDED SYSTEM History & need of Embedded System Basic

More information

COS 318: Operating Systems

COS 318: Operating Systems COS 318: Operating Systems Overview Kai Li Computer Science Department Princeton University (http://www.cs.princeton.edu/courses/cos318/) Important Times Lectures 9/20 Lecture is here Other lectures in

More information

Wed. Aug 23 Announcements

Wed. Aug 23 Announcements Wed. Aug 23 Announcements Professor Office Hours 1:30 to 2:30 Wed/Fri EE 326A You should all be signed up for piazza Most labs done individually (if not called out in the doc) Make sure to register your

More information

COMP3221: Microprocessors and. and Embedded Systems. Instruction Set Architecture (ISA) What makes an ISA? #1: Memory Models. What makes an ISA?

COMP3221: Microprocessors and. and Embedded Systems. Instruction Set Architecture (ISA) What makes an ISA? #1: Memory Models. What makes an ISA? COMP3221: Microprocessors and Embedded Systems Lecture 2: Instruction Set Architecture (ISA) http://www.cse.unsw.edu.au/~cs3221 Lecturer: Hui Wu Session 2, 2005 Instruction Set Architecture (ISA) ISA is

More information

esi-risc Development Suite Getting Started Guide

esi-risc Development Suite Getting Started Guide 1 Contents 1 Contents 2 2 Overview 3 3 Starting the Integrated Development Environment 4 4 Hello World Tutorial 5 5 Next Steps 8 6 Support 10 Version 2.5 2 of 10 2011 EnSilica Ltd, All Rights Reserved

More information

ECE 598 Advanced Operating Systems Lecture 10

ECE 598 Advanced Operating Systems Lecture 10 ECE 598 Advanced Operating Systems Lecture 10 Vince Weaver http://web.eece.maine.edu/~vweaver vincent.weaver@maine.edu 22 February 2018 Announcements Homework #5 will be posted 1 Blocking vs Nonblocking

More information

Course Introduction. Purpose: Objectives: Content: 27 pages 4 questions. Learning Time: 20 minutes

Course Introduction. Purpose: Objectives: Content: 27 pages 4 questions. Learning Time: 20 minutes Course Introduction Purpose: This course provides an overview of the Direct Memory Access Controller and the Interrupt Controller on the SH-2 and SH-2A families of 32-bit RISC microcontrollers, which are

More information

A Brief Introduction to Using LLVM. Nick Sumner

A Brief Introduction to Using LLVM. Nick Sumner A Brief Introduction to Using LLVM Nick Sumner What is LLVM? A compiler? (clang) What is LLVM? A compiler? (clang) A set of formats, libraries, and tools. What is LLVM? A compiler? (clang) A set of formats,

More information

Introduction to Microcontrollers

Introduction to Microcontrollers CSE391: Embedded Systems and Interfacing Introduction to Microcontrollers Nazmus Saquib Lecturer Department of Computer Science and Engineering Bangladesh University of Engineering and Technology April

More information

,$5$SSOLFDWLRQ1RWH$95 (IILFLHQWSURJUDPPLQJRI$WPHO V $95 PLFURFRQWUROOHUV

,$5$SSOLFDWLRQ1RWH$95 (IILFLHQWSURJUDPPLQJRI$WPHO V $95 PLFURFRQWUROOHUV ,$5$SSOLFDWLRQ1RWH$95 (IILFLHQWSURJUDPPLQJRI$WPHO V $95 PLFURFRQWUROOHUV 6XPPDU\ This application note provides some useful hints on how to program the Atmel AVR microcontrollers using the IAR Compiler.

More information

Chapter 2 A Quick Tour

Chapter 2 A Quick Tour Chapter 2 A Quick Tour 2.1 The Compiler Toolchain A compiler is one component in a toolchain of programs used to create executables from source code. Typically, when you invoke a single command to compile

More information

Compiler, Assembler, and Linker

Compiler, Assembler, and Linker Compiler, Assembler, and Linker Minsoo Ryu Department of Computer Science and Engineering Hanyang University msryu@hanyang.ac.kr What is a Compilation? Preprocessor Compiler Assembler Linker Loader Contents

More information

AVR ISA & AVR Programming (I) Lecturer: Sri Parameswaran Notes by: Annie Guo

AVR ISA & AVR Programming (I) Lecturer: Sri Parameswaran Notes by: Annie Guo AVR ISA & AVR Programming (I) Lecturer: Sri Parameswaran Notes by: Annie Guo 1 Lecture Overview AVR ISA AVR Instructions & Programming (I) Basic construct implementation 2 Atmel AVR 8-bit RISC architecture

More information

Microprocessors And Microcontrollers (Practical)

Microprocessors And Microcontrollers (Practical) Microprocessors And Microcontrollers (Practical) Semester : 4 th, 5 th (TL, ES) Course Code : ES256, ES313 By: Dr. Attiya Baqai Assistant Professor, Department of Electronics, MUET. 3 Introduction to Programming

More information

Advanced Operating Systems Embedded from Scratch: System boot and hardware access. Federico Terraneo

Advanced Operating Systems Embedded from Scratch: System boot and hardware access. Federico Terraneo Embedded from Scratch: System boot and hardware access federico.terraneo@polimi.it Outline 2/28 Bare metal programming HW architecture overview Linker script Boot process High level programming languages

More information

Hands-On with STM32 MCU Francesco Conti

Hands-On with STM32 MCU Francesco Conti Hands-On with STM32 MCU Francesco Conti f.conti@unibo.it Calendar (Microcontroller Section) 07.04.2017: Power consumption; Low power States; Buses, Memory, GPIOs 20.04.2017 21.04.2017 Serial Interfaces

More information

EE458 - Embedded Systems Lecture 4 Embedded Devel.

EE458 - Embedded Systems Lecture 4 Embedded Devel. EE458 - Embedded Lecture 4 Embedded Devel. Outline C File Streams References RTC: Chapter 2 File Streams man pages 1 Cross-platform Development Environment 2 Software available on the host system typically

More information

COMP2121: Microprocessors and Interfacing. Instruction Set Architecture (ISA)

COMP2121: Microprocessors and Interfacing. Instruction Set Architecture (ISA) COMP2121: Microprocessors and Interfacing Instruction Set Architecture (ISA) http://www.cse.unsw.edu.au/~cs2121 Lecturer: Hui Wu Session 2, 2017 1 Contents Memory models Registers Data types Instructions

More information

KOTLIN/NATIVE + CLANG, TRAVEL NOTES NIKOLAY IGOTTI, JETBRAINS

KOTLIN/NATIVE + CLANG, TRAVEL NOTES NIKOLAY IGOTTI, JETBRAINS KOTLIN/NATIVE + CLANG, TRAVEL NOTES NIKOLAY IGOTTI, JETBRAINS KOTLIN IS NOT JUST AN ISLAND KOTLIN LANGUAGE FP and OOP language Type inference, smart casts, nullability checks Generics (erased, with reification

More information

Compiler construction. Course info. Today. Lecture 1: Introduction and project overview. Compiler Construction Why learn to write a compiler?

Compiler construction. Course info. Today. Lecture 1: Introduction and project overview. Compiler Construction Why learn to write a compiler? Today Compiler construction Lecture 1: Introduction and project overview Course info Introduction to compiling Some examples Project description Magnus Myreen Spring 2018 Chalmers University of Technology

More information

Prefetch Cache Module

Prefetch Cache Module PIC32 TM Prefetch Cache Module 2008 Microchip Technology Incorporated. All Rights Reserved. PIC32 Prefetch Cache Module Slide 1 Hello and welcome to the PIC32 Prefetch Cache Module webinar. I am Nilesh

More information

EMBEDDED SYSTEMS: Jonathan W. Valvano INTRODUCTION TO THE MSP432 MICROCONTROLLER. Volume 1 First Edition June 2015

EMBEDDED SYSTEMS: Jonathan W. Valvano INTRODUCTION TO THE MSP432 MICROCONTROLLER. Volume 1 First Edition June 2015 EMBEDDED SYSTEMS: INTRODUCTION TO THE MSP432 MICROCONTROLLER Volume 1 First Edition June 2015 Jonathan W. Valvano ii Jonathan Valvano First edition 3 rd printing June 2015 The true engineering experience

More information

Microcontroller VU

Microcontroller VU 182.694 Microcontroller VU Martin Perner SS 2017 Featuring Today: A Deep Look into the Processor Core Getting Code onto the Microcontroller Chip Weekly Training Objective This week 1.2 Board test 2.1.1

More information

A Framework for Automatic OpenMP Code Generation

A Framework for Automatic OpenMP Code Generation 1/31 A Framework for Automatic OpenMP Code Generation Raghesh A (CS09M032) Guide: Dr. Shankar Balachandran May 2nd, 2011 Outline 2/31 The Framework An Example Necessary Background Polyhedral Model SCoP

More information

Final Exam Study Guide

Final Exam Study Guide Final Exam Study Guide Part 1 Closed book, no crib sheet Part 2 Open book, open notes, calculator (no laptops, phones, devices with screens larger than a TI-89 calculator, devices with wireless communication).

More information