Wed. Aug 23 Announcements

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1 Wed. Aug 23 Announcements Professor Office Hours 1:30 to 2:30 Wed/Fri EE 326A You should all be signed up for piazza Most labs done individually (if not called out in the doc) Make sure to register your clicker on blackboard We will have some questions Friday will count for nothing, but can you can use them to verify that everything is registered. Real labs start next week Intro to tools/assembly Start looking at HW (some formatting issues will be fixed today)

2 Module 1 Microcontroller Programming Techniques Tim Rogers 2017

3 Learning Outcome #1 An ability to program a microcontroller to perform various tasks Why? IoT Embedded systems in cars

4 Learning Outcome #1 An ability to program a microcontroller to perform various tasks How? A. Architecture and Programming Model B. Instruction Set Overview C. Assembly Control Structures D. Control Structure Applications E. Table Lookup F. Parameter Passing G. Macros and Structured Programming

5 What makes a Microcontroller? General Purpose Focus on Programmability IBM Power 8 Microprocessor Embedded Whole-System Non-UserProgrammable

6 Different Objectives General Purpose High-performance Need to run anything relatively well Less energy constrained Limitless Memory Silicon devoted to compute and caches Embedded Limited ability Inexpensive Limited memory Low-energy Silicon devoted to many peripherals (although core still consumes a lot)

7 Characteristics of general-purpose processors Virtual memory (Page Tables, TLBs) Deep cache hierarchy Large number of registers Hardware floating point Deep Pipelines/ Out of Order Exec. Complex Prediction Mechanisms Multicore Take ECE 437! Interrupts mostly get in the way

8 Characteristics of embedded processors Live and die by interrupts! Few registers (need to switch contexts fast) Circuitry devoted to analog Often rely on hand-tuned assembly code

9 Instruction Set Architectures (ISAs) Set of operations visible to the programmer ISA is the contract between the SW and HW Examples: CPU12, x86, PowerPC, ARM, SPARC, etc

10 Different Types of ISAs CISC (Complex Instruction Set Computer) RISC (Reduced Instruction Set Computer) DSPs (Digital Signal Processors) 9S12 (ECE 362) 16-bits

11 ISA defines Interaction between processor and memory??

12 Some common Architectures How to compute Z = X + Y : Accumulator LoadA X AddA Y StoreA Z Reg/Reg Load R1,X Load R2,Y Add R3,R1,R2 Store R3,Z 9S12 (ECE 362)

13 Why Freescale 68HC(s)12?? (AKA 9S12) Relatively Simple Introduces basic instruction set concepts Can easily analyze memory bus timing Actually used in the real world Comes from the automotive industry

14 You Dev Kit Boot/Run Switch BDM connector 9S12C32 Switch / LED input/output COM port Microcontroller Module D.C. power Docking Board

15 Overview of 9S12C32 15

16 Overview of 9S12C32 Several things to note.. The HCS12 CPU has the same architecture and programming model as the HC12 16

17 Overview of 9S12C32 Several things to note.. The 9S12C32 module has 2K of SRAM and 32K of Flash (no EEROM) 17

18 Overview of 9S12C32 Several things to note.. The 48-pin version of the chip on this module does not have Ports A & B padded out 18

19 Overview of 9S12C32 Several things to note.. External interrupt pins are on Port E 19

20 Overview of 9S12C32 Several things to note.. Real-time interrupt (RTI) module 20

21 Overview of 9S12C32 Several things to note.. Analog-to-digital (ATD) converter module inputs are on Port PAD 21

22 Overview of 9S12C32 Several things to note.. Timer (TIM) module I/O on Port T 22

23 Overview of 9S12C32 Several things to note.. Pulse width modulator (PWM) here, I/O shared with TIM module on Port T MODRR register setting determines whether these Port T pins are mapped to the TIM or PWM 23

24 Overview of 9S12C32 Several things to note.. Asynchronous serial communications interface (SCI) on Port S 24

25 Overview of 9S12C32 Several things to note.. Controller area network (MSCAN) on Port M 25

26 Overview of 9S12C32 Several things to note.. Synchronous peripheral interface (SPI) on Port M 26

27 Memory Uses SRAM (Static Random Access Memory) Volatile Variables Stack Buffers Test Code Flash Memory Non-Volatile App Code Static Data Vectors (reset and interrupts)

28 9S12C32 Memory Map 2K SRAM (mappable) test code, data, variables, stack Default (reset) location is 800-FFF firmware (application code) 30K Flash 8000-F7FF interrupt vectors 28

29 Overview of 68HC(S)12 Architecture 29

30 9S12 Registers 8-bits Programming Model 16-bits D 8-bits 7 A 0 7 B 0 Accumulators Arithmetic/Logic X 15 0 Y 15 0 SP 15 0 PC 16-bits 16-bits 16-bits 16-bits 15 0 Index Registers Stack Pointer Program Counter Pointers to memory Can add constant/register Auto +/- Pointer to top of stack PSH/PUL Instructions Pointer to next instruction 30

31 Condition Code Register S X H I N Z V C Condition Code Register (CCR) Carry/Borrow Flag Overflow Flag Zero Flag Negative Flag IRQ Mask Half-Carry XIRQ Mask Stop Disable

ALU Condition Codes C carry/borrow flag (carry out of the sign position for addition, complement of carry out of sign position for subtraction) V overflow flag (set if two s complement overflow has

32 ALU Condition Codes C carry/borrow flag (carry out of the sign position for addition, complement of carry out of sign position for subtraction) V overflow flag (set if two s complement overflow has occurred) Z zero flag (set if result of computation is zero) N negative flag (most significant bit (sign) of computation) H half carry flag (carry out of the lower 4-bits (nibble), only valid after ADD) 32

33 Machine Control Condition Codes I IRQ interrupt mask Ø 0 IRQ is not masked (enabled) Ø 1 IRQ is masked (disabled) X XIRQ interrupt mask Ø 0 XIRQ is not masked (enabled) Ø 1 XIRQ is masked (disabled) S STOP instruction disable Ø 0 STOP instruction is enabled Ø 1 STOP instruction is disabled 33

34 Instruction Representation Just a bunch of bits Remember? Simple Computer?

35 Instruction Formats and Data Types Example BRSET oprx16,xysp, msk8, rel8 Opcode (1B) Postbyte Offset (2B) can also be 1B Immediate (2B) can also be 1B ADDA addr DAA Opcode (1B) opcode (2B) Postbyte *There are different ways to mix/match these DEX Opcode (1B) Length: 1B to 6B 35

36 Instruction Formats and Data Types Bit Byte (8-bit) Word (16-bit) Double Word (32-bit) Packed Binary Coded Decimal Unsigned Fractions

37 Addressing Modes Purpose: Need to access memory Need an ADDRESS?? ADDA addr Memory Addr Value Value not possible

38 Addressing Modes Definition: The CPU uses an addressing mode to determine the effective address of where an operand is stored in memory Commonly used addressing modes Ø immediate (data immediately follows opcode, i.e., is part of the instruction) DOES NOT GO TO MEMORY Ø extended / absolute (absolute address of where operand is stored in memory) Ø relative (desired location is calculated relative to the current value in the PC) Ø indexed (an index register is used to point to the operand many variations with offset) Ø indirect (the operand pointer is in memory) 38

39 Illustrative Instructions LDAA addr STAA addr load accumulator A with the contents of memory location addr store the contents of accumulator A at memory location addr addr represents the effective address 39

40 LD versus Store Core Registers 77 A 56 B LDAA 1 Memory Addr 0 1 Value

Microcontrollers. Microcontroller

Microcontrollers. Microcontroller Microcontrollers Microcontroller A microprocessor on a single integrated circuit intended to operate as an embedded system. As well as a CPU, a microcontroller typically includes small amounts of RAM and