MICROPROCESSOR BASED SYSTEM DESIGN

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1 MICROPROCESSOR BASED SYSTEM DESIGN Lecture 5 Xmega 128 B1: Architecture MUHAMMAD AMIR YOUSAF

2 VON NEUMAN ARCHITECTURE CPU Memory Execution unit ALU Registers Both data and instructions at the same system bus IO units BU System bus IR PC Controller Control unit

3 AVR CPU: HARVARD ARCHITECTURE o The main function of the CPU is to execute the code and perform all calculations. othe AVR XMEGA CPU uses a Harvard architecture with separate memories and buses for program and data. o The CPU is able to access memories, perform calculations, control peripherals, and execute the program in the flash memory.

4 AVR CPU: ALU o ALU supports arithmetic and logic operations between registers or between a constant and a register. o Single-register operations can also be executed in the ALU. o Both 8- and 16-bit arithmetic is supported. othe hardware multiplier supports signed and unsigned multiplication and fractional format. Multiplication of unsigned integers Multiplication of signed integers Multiplication of a signed integer with an unsigned integer Multiplication of unsigned fractional numbers Multiplication of signed fractional numbers Multiplication of a signed fractional number with an unsigned one

5 AVR CPU: ALU o 32 fast access registers directly connected to ALU, allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. With instruction in a single clock cycle, the Atmel AVR XMEGA B devices achieve throughputs approaching one million instructions per second (MIPS) per megahertz. o Status register: After an arithmetic operation, the status register is updated to reflect information about the result of the operation.

6 CPU: REGISTER FILE The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient address calculations. The register file is located in a separate address space, and so the registers are not accessible as data memory.

7 THE X-, Y-, AND Z- REGISTERS These three address registers are called the X-register, Y-register, and Z-register. The register file supports the following input/output schemes: One 8-bit output operand and one 8-bit result input Two 8-bit output operands and one 8-bit result input Two 8-bit output operands and one 16-bit result input One 16-bit output operand and one 16-bit result input

8 STATUS REGISTER The Status Register (SREG) contains information about the result of the most recently executed arithmetic or logic instruction. This information can be used for altering program flow in order to perform conditional operations. The status register is not automatically stored when entering an interrupt routine nor restored when returning from an interrupt. This must be handled by software.

9 STATUS REGISTER The Status Register (SREG) contains information about the result of the most recently executed arithmetic or logic instruction. Bit 7 I: Global Interrupt Enable Bit 6 T: Bit Copy Storage Bit 5 H: Half Carry Flag Bit 4 S: Sign Bit, S = N V Bit 3 V: Two s Complement Overflow Flag Bit 2 N: Negative Flag Bit 1 Z: Zero Flag Bit 0 C: Carry Flag

10 STACK POINTER AND STACK The stack is used for storing return addresses after interrupts and subroutine calls. It is also be used for storing temporary data. The stack pointer (SP) register always points to the top of the stack. During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be two or three bytes, depending on program memory size of the device. It is allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM.

11 PROGRAM FLOW At reset, the CPU starts to execute instructions from the lowest address in the flash program memory 0. The program counter (PC) addresses the next instruction to be fetched. Program flow is provided by conditional and unconditional jumps and call instructions. Addressing the whole address space directly is possible. During interrupts and subroutine calls, the return address PC is stored on the stack.

12 AVR XMEGA ARCHITECTURE CPU Memory Execution unit ALU SR Registers R30 R31 BU IR IO units SP Controller PC Data bus Instruction bus Control unit

13 MEMORIES The AVR architecture has two main memory spaces, the program memory and the data memory. Executable code can reside only in the program memory, while data can be stored in the program memory and the data memory. Data Memory: The data memory includes the IO memory, internal SRAM and EEPROM for nonvolatile data storage. All I/O status and control registers reside in the lowest 4KB addresses of the data memory. It is accessed to manipulate the status and configuration registers for peripherals and modules including CPU.

14 MEMORIES Data Memory: The SRAM holds data e.g stack and stack pointers. Code execution from SRAM is not supported. Nonvolatile memory (NVM) spaces can be locked for further write and read/write operations. This prevents unrestricted access to the application software. The data memory can be accessed by the CPU using the load, store commands. All memory spaces are linear and require no memory bank switching.

15 MEMORIES Flash Program Memory: All XMEGA devices contain on-chip in-system reprogrammable flash memory for program storage. The flash memory can be accessed for read and write from an external programmer through the PDI or from application software running in the device. All AVR CPU instructions are 16 or 32 bit wide, and each flash location is 16 bits wide. The flash memory is organized in two main sections, the application section and the boot loader section.

MEMORIES The application section contains an application table section. This enables safe storage of nonvolatile data in the program memory.

16 MEMORIES The application section contains an application table section. This enables safe storage of nonvolatile data in the program memory.. Application Section The Application section is the section of the flash that is used for storing the executable application code. The protection level for the application section can be selected by the boot lock bits for this section. Boot Loader Section The boot loader software is used to write programmable flash with SPM instruction. The SPM instruction can access the entire flash, including the boot loader section itself. If this section is not used for boot loader software, application code can be stored here.

17 AVR XMEGA ARCHITECTURE CPU Data Memory 4K IO, 8K SRAM 4K EEPROM Program Memory 128K Flash IO units BU Execution unit SP ALU SR Controller Registers R30 R31 IR PC Data bus Instruction bus Control unit

18 IO PORTS IO ports provide interface for external devices to communicate data. Two major types of Inputs and Outputs are: a. Analog IOs b. Digital IOs AVR XMEGA microcontrollers have flexible general purpose IO (GPIO) ports, each having up to 8 port pins (0 to 7). Each port pin can be individually configured as Digital Input or Output with configurable driver and pull settings. Other digital data communication ports, such as USART, SPI, and timer/counters, can be mapped to selectable pin locations in order to optimize pin-out versus application needs.

19 DIGITAL IO PIN CONFIGURATION Each port has one data direction (DIR) register to configure a pin as input or output. If DIRn is written to one, pin n is configured as an output pin. If DIRn is written to zero, pin n is configured as an input pin. When direction is set as output, the OUTn bit in OUT is used to set the value of the pin. If OUTn is written to one, pin n is driven high. If OUTn is written to zero, pin n is driven low. The data input value IN register is used for reading the port pins. Most port pins have alternate pin functions in addition to being a general purpose I/O pin.

20 IO PORTS REGISTER DESCRIPTION Read-Modify-Write

21 IO PORTS REGISTER DESCRIPTION

22 IO PORTS REGISTER DESCRIPTION

23 IO MEMORY MAP 0X600 0X601 0X602 0X603 0X604 0X605 0X606 0X607 0X618 DIR DIRSET DIRCLR DIRTGL OUT OUTSET OUTCLR OUTTGL IN INTCTRL * * PIN7CTRL

24 IO MEMORY MAP Struct 0X600 0X601 0X602 0X603 0X604 0X605 0X606 0X607 0X618 DIR DIRSET DIRCLR DIRTGL OUT OUTSET OUTCLR OUTTGL IN INTCTRL * * PIN7CTRL

25 MORE PERIPHERALS USART: Universal Synchronous and Asynchronous Serial Receiver and Transmitter Fast, Flexible and Full duplex Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits. Interrupt driven communication, interrupts for both transmit and receive complete. USART port in XMEGA B can be configured to use as SPI Master.

26 MORE PERIPHERALS SPI: The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. Full-duplex, three-wire synchronous data transfer Master or slave operation. The master initiates and controls all data transactions. Eight programmable bit rates Interrupt flag at the end of transmission Wake up from idle sleep mode

27 MORE PERIPHERALS TWI: Bidirectional, two-wire communication interface Bus master and slave operation supported Slave address match can wake device from all sleep modes USB: The USB module is a USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface.

28 AVR XMEGA ARCHITECTURE CPU Data Memory 4K IO, 8K SRAM 4K EEPROM Program Memory 128K Flash Digital IOs USART SPI TWI ADCs Data bus BU Instruction bus Execution unit SP ALU SR Controller Control unit Registers R30 R31 IR PC

29 ANALOG IOS Analog To Digital converters: The ADC converts analog signals to digital values. In XMEGA B it has 12-bit resolution and is capable of converting up to 300 thousand samples per second (KSPS).

30 TIMER COUNTER Atmel AVR XMEGA devices have a set of flexible, 16-bit timer/counters (TC). Their capabilities include: Accurate measurement of program execution timing Frequency and waveform generation, Input capture with time and frequency measurement of digital signals. 16-bit Real-Time Counter: The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes, to keep track of time.

31 POWER MANAGEMENT AND SLEEP MODES Five sleep modes and clock gating are provided to meet the requirements for power consumption. Idle Power down Power save Standby Extended standby Power reduction register to disable clock and turn off unused (individual ) peripherals in active and idle modes Interrupts and reset can awake the device from sleep mode.

34 MEMORY PROGRAMMING In XMEGA controllers, the Non Volatile Memory can be programmed with Self Programming and with External Programming. Reading and writing the EEPROM and flash memory from the boot loader (application software in boot loader section) in the device is referred to as self-programming. A boot loader can both read and write the flash program memory. The boot loader can use any available interface to read the code and write (program) it into program flash memory. External programming is the method for writing code and nonvolatile data into the device from an external programmer or debugger. For external programming, the device is accessed through the PDI and PDI controller, and using either the JTAG or PDI physical connection.

35 AVR XMEGA 128B: INTRODUCTION o High-performance, low-power Atmel AVR XMEGA 8/16-bit Microcontroller o Memories: 64K - 128KBytes of in-system self-programmable flash 4K - 8KBytes boot section 2KBytes EEPROM 4K - 8KBytes internal SRAM o Three 16-bit timer/counters o Peripherals: o Two USARTs o One Serial Peripheral Interface (SPI) o One Two Wire Interface (TWI) o16-bit Real Time Counter (RTC) with separate oscillator.

36 AVR XMEGA 128B: INTRODUCTION o Four Analog Comparators. o External interrupts on all General Purpose I/O pins o Programmable watchdog timer with separate on-chip ultra low power oscillator. o QTouch library support Capacitive touch buttons, sliders and wheels o Five sleep modes o Programming and debug interfaces JTAG (IEEE Compliant) interface, including boundary scan PDI (Program and Debug Interface) Operating frequency: 0 32MHz

38 THANK YOU Muhammad Amir Yousaf 38

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