Efficiently Solving Bit-Vector Problems Using Model Checkers
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1 Efficiently Solving Bit-Vector Problems Using Model Checkers Institute for Formal Models and Verification Johannes Kepler University, Linz, Austria SMT 2013 July 8 - July 9, 2013 Helsinki, Finnland 1
2 Motivation How does the encoding of the bit-widths affect the complexity of satisfiability checking for BV logics? In practice logarithmic (e.g. binary, decimal, hexadecimal) encoding is used (in contrast with unary encoding) Example in SMT2 (set-logic QF_BV) (declare-fun x () (_ BitVec )) (declare-fun y () (_ BitVec )) (declare-fun z () (_ BitVec )) (assert (= z (bvadd x y))) (assert (= z (bvshl x (_ bv )))) (assert (distinct x y)) Using Boolector: input file of 225 bytes in SMT2 format 129 MB in AIGER format; 843 MB in DIMACS format 2
3 Motivation How does the encoding of the bit-widths affect the complexity of satisfiability checking for BV logics? In practice logarithmic (e.g. binary, decimal, hexadecimal) encoding is used (in contrast with unary encoding) Example in SMT2 (set-logic QF_BV) (declare-fun x () (_ BitVec )) (declare-fun y () (_ BitVec )) (declare-fun z () (_ BitVec )) (assert (= z (bvadd x y))) (assert (= z (bvshl x (_ bv )))) (assert (distinct x y)) Using Boolector: input file of 225 bytes in SMT2 format 129 MB in AIGER format; 843 MB in DIMACS format 3
4 Previous Work Let QF BV be the set of bit-vector formulas with binary encoding and all common bit-vector operations, e.g. bitwise operations, arithmetic operations, concatenation, slicing, shifts, relational operations,... QF BV is NExpTime-complete G. Kovásznai, A. Fröhlich, A. Biere, On the Complexity of Fixed-Size Bit-Vector Logics with Binary Encoded Bit-Width. In: Proc. SMT 12. 4
5 Previous Work How does restricting the set of operations affect the complexity? QF BV c : bitwise operations, equality, and shift by any constant QF BV c is NExpTime-complete QF BV 1 : bitwise operations, equality, and shift by only 1 QF BV 1 is PSpace-complete QF BV bw : bitwise operations and equality QF BV bw is NP-complete A. Fröhlich, G. Kovásznai, A. Biere, More on the Complexity of Quantifier-Free Fixed-Size Bit-Vector Logics with Binary Encoding. In: Proc. CSR 13. 5
6 Previous Work How does restricting the set of operations affect the complexity? QF BV c : bitwise operations, equality, and shift by any constant QF BV c is NExpTime-complete QF BV 1 : bitwise operations, equality, and shift by only 1 QF BV 1 is PSpace-complete QF BV bw : bitwise operations and equality QF BV bw is NP-complete A. Fröhlich, G. Kovásznai, A. Biere, More on the Complexity of Quantifier-Free Fixed-Size Bit-Vector Logics with Binary Encoding. In: Proc. CSR 13. PSpace-inclusion also holds for addition, indexing, multiplication by constant, relational operations,... 6
7 Complexity: QF BV 1 PSpace Existing work for non-fixed-size bit-vectors resp. quantifier-free Presburger arithmetic with bitwise operations (QFPAbit): QFPAbit polynomially Sequential Circuits A. Spielmann, V. Kuncak, Synthesis for Unbounded Bit-Vector Arithmetic. In: Proc. IJCAR 12. A flat normal form of the original formula is created: Logical combination of certain atomic expressions. For each atomic expression a direct translation into an atomic sequential circuit can be given. The result is the logical combination of the atomic circuits. Can be adopted for fixed-size bit-vectors of bit-width 2 n by introducing a n-bit counter. 7
8 Practical Implementation Bit-blasting can cause exponential growth. Translate original SMT2 input to a polynomial SMV specification. Use model checkers to solve the translated formulas. (additionally, smvflatten and smvtoaig are used to obtain inputs for model checkers that expect AIGER format) Example in SMT2 (set-logic QF_BV) (declare-fun x () (_ BitVec )) (declare-fun y () (_ BitVec )) (declare-fun z () (_ BitVec )) (assert (= z (bvadd x y))) (assert (= z (bvshl x (_ bv )))) (assert (distinct x y)) 8
9 Example (declare-fun x () (_ BitVec )) (declare-fun y () (_ BitVec )) (declare-fun z () (_ BitVec )) init(counter_bit0) := FALSE; next(counter_bit0) := counter_bit0 xor (TRUE); init(counter_bit1) := FALSE; next(counter_bit1) := counter_bit1 xor (counter_bit0);... init(counter_bit19) := FALSE; next(counter_bit19) := counter_bit19 xor (counter_bit0 &... & counter_bit18); init(counter_gte_ ) := FALSE; next(counter_gte_ ) := counter_gte_ (counter_bit0 &... &!counter_bit6 &... & counter_bit19); 9
10 Example (assert (distinct x y)) init(atom_equal) := TRUE; next(atom_equal) := case counter_gte_ : atom_equal; TRUE : atom_equal & (x <-> y); esac; 10
11 Example (assert (= z (bvadd x y))) init(atom_add) := TRUE; next(atom_add) := case counter_gte_ : atom_add; TRUE : atom_add & (z <-> (x xor y xor atom_cin)); esac; init(atom_cin) := FALSE; next(atom_cin) := case counter_gte_ : atom_cin; TRUE : (x & y) (x & atom_cin) (y & atom_cin); esac; 11
12 Example Shift is translated similar to addition. Finally, check: AG(!counter_gte_ !atom_add!atom_shift atom_equal) 12
13 Experiments: Benchmarks QF_BV/froehlichkovasznaibiere/shift1add.n: (x + y = x 1) (x = y) QF_BV/froehlichkovasznaibiere/ndist.a.n: (x < y) (x + 1 y) QF_BV/froehlichkovasznaibiere/ndist.b.n: (x + 1 y) (x < y) QF_BV/froehlichkovasznaibiere/power2sum.n: (x = 2 k y = 2 l k l) (x + y 2 m ) QF_BV/froehlichkovasznaibiere/power2bit.n: (x = 2 k x[c 1 ] = 1) (x[c 2 ] 1) QF_BV/froehlichkovasznaibiere/power2eq.n: (x = 2 k y = 2 l x[c] = 1 y[c] = 1) (x = y) 13
14 Experiments: Setting Same cluster and setup as HWMCC nodes, Intel Quad Core 2.6 GHz, 8 GB RAM - The wall clock time limit 900 seconds - Memory limit 7 GB - Each solver has full access to one node (4 cores) 3648 runs in total solvers (resp. configurations) - 6 different benchmark sets each consisting of 32 instances All our results are available on our web page together with generation scripts for all benchmarks in SMT2 format and our translation tool bv2smv. 14
15 Experiments: Results STP Boolector MathSAT5 Z3 IImc-BDD-bw NuSMV-bw IImc-BDD-fw IImc NuSMV Blimc Tip-BMC Aigbmc Tip solved sat unsat time space Table : Overall results for 13 solvers 15
16 Experimental Results: shift1add - Time Boolector STP IImc IImc-BDD-bw NuSMV NuSMV-bw Tip-BMC Time needed to solve instances of shift1add with different bit-widths time e+06 bit-width 16
17 Experimental Results: shift1add - Space 1000 Boolector STP IImc IImc-BDD-bw NuSMV NuSMV-bw Tip-BMC Space needed to solve instances of shift1add with different bit-widths space e+06 bit-width 17
18 Experimental Results: ndist.a - Time Boolector STP IImc IImc-BDD-bw NuSMV NuSMV-bw Tip-BMC Time needed to solve instances of ndista with different bit-widths time e+06 bit-width 18
19 Experimental Results: ndist.a - Space 1000 Boolector STP IImc IImc-BDD-bw NuSMV NuSMV-bw Tip-BMC Space needed to solve instances of ndista with different bit-widths space e+06 bit-width 19
20 Experimental Results: ndist.b - Time Boolector STP IImc IImc-BDD-bw NuSMV NuSMV-bw Tip-BMC Time needed to solve instances of ndistb with different bit-widths time e+06 bit-width 20
21 Experimental Results: ndist.b - Space 1000 Boolector STP IImc IImc-BDD-bw NuSMV NuSMV-bw Tip-BMC Space needed to solve instances of ndistb with different bit-widths space e+06 bit-width 21
22 Experimental Results: power2sum - Time Boolector STP IImc IImc-BDD-bw NuSMV NuSMV-bw Tip-BMC Time needed to solve instances of power2sum with different bit-widths time e+06 bit-width 22
23 Experimental Results: power2sum - Space 1000 Boolector STP IImc IImc-BDD-bw NuSMV NuSMV-bw Tip-BMC Space needed to solve instances of power2sum with different bit-widths space e+06 bit-width 23
24 Experimental Results: power2bit - Time Boolector STP IImc IImc-BDD-bw NuSMV NuSMV-bw Tip-BMC Time needed to solve instances of power2bit with different bit-widths time e+06 bit-width 24
25 Experimental Results: power2bit - Space 1000 Boolector STP IImc IImc-BDD-bw NuSMV NuSMV-bw Tip-BMC Space needed to solve instances of power2bit with different bit-widths space e+06 bit-width 25
26 Experimental Results: power2eq - Time Boolector STP IImc IImc-BDD-bw NuSMV NuSMV-bw Tip-BMC Time needed to solve instances of power2eq with different bit-widths time e+06 bit-width 26
27 Experimental Results: power2eq - Space 1000 Boolector STP IImc IImc-BDD-bw NuSMV NuSMV-bw Tip-BMC Space needed to solve instances of power2eq with different bit-widths space e+06 bit-width 27
28 Conclusion Results: Translation QF BV 1 polynomially SMV Crafted benchmarks solved efficiently by model checkers. Space requirement reduced even more significantly. Best performance by using BDD backward reachability. Future Work: Is it possible to solve industrial benchmarks more efficiently with our approach? Can SMT solvers profit from techniques used in model checkers? Is Presburger arithmetic on fixed-size bit-vectors still NP-complete? 28
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