Turbo-Charging Lemmas on Demand with Don t Care Reasoning
|
|
- Mark Garry Shepherd
- 5 years ago
- Views:
Transcription
1 Turbo-Charging Lemmas on Demand with Don t Care Reasoning Aina Niemetz, Mathias Preiner and Armin Biere Institute for Formal Models and Verification (FMV) Johannes Kepler University, Linz, Austria FMCAD 204 October 2-24, 204 Lausanne, Switzerland
2 Introduction Lemmas on Demand so-called lazy SMT approach our SMT solver Boolector implements Lemmas on Demand for the quantifier-free theory of fixed-size bit vectors arrays recently: Lemmas on Demand for Lambdas [DIFTS 3] generalization of Lemmas on Demand for Arrays [JSAT 09] arrays represented as uninterpreted functions array operations represented as lambda-terms reads represented as function applications
3 Lemmas on Demand Workflow: Original Procedure LOD LOD φ Preprocessing π consistent Refinement inconsistent Consistency Check σp(α(π) ξ) ξ = {l} ξ σ(α(π) ξ) Partial Model Extraction sat Formula Abstraction α(π) α(π) ξ DPB unsat bit vector formula abstraction (bit vector skeleton) enumeration of truth assignments (candidate models) iterative refinement with lemmas until convergence sat unsat
4 Lemmas on Demand Workflow: Original Procedure LOD LOD φ Preprocessing π consistent sat Refinement inconsistent Consistency Check σp(α(π) ξ) ξ = {l} ξ σ(α(π) ξ) Partial Model Extraction sat Full Candidate Model Formula Abstraction α(π) α(π) ξ DPB unsat unsat each candidate model is a full truth assignment of the formula abstraction full candidate model needs to be checked for consistency w.r.t. theories
5 Lemmas on Demand Workflow: Original Procedure LOD LOD φ Preprocessing π consistent Refinement inconsistent Consistency Check σp(α(π) ξ) ξ = {l} ξ σ(α(π) ξ) Partial Model Extraction sat Formula Abstraction α(π) α(π) ξ DPB unsat abstraction refinement usually the most costly part of LOD cost generally correlates with number of refinements checking the full candidate model often not required small subset responsible for satisfying formula abstraction sat unsat
6 Lemmas on Demand Workflow: Optimized Procedure LOD opt LOD φ Preprocessing π consistent Refinement inconsistent Consistency Check σp(α(π) ξ) ξ = {l} ξ σ(α(π) ξ) Partial Model Extraction sat Formula Abstraction α(π) α(π) ξ DPB Optimization unsat focus LOD on the relevant parts of the input formula exploit a posteriori observability don t cares partial model extraction prior to consistency checking subsequently reduces the cost for consistency checking sat Partial Candidate Model unsat
7 Lemmas on Demand Example: Input Formula Example. ψ i k (f(i) = e f(k) = v) v = ite(i = j, e, g(j)) and and eq eq or 2 ite 3 eq eq eq apply e apply 2 v apply 3 j i k f g
8 Lemmas on Demand Example: Formula Abstraction Example. Bit Vector Skeleton and and 2 eq eq 2 and 3 2 ite 3 eq 5 eq 4 eq 3 α(apply ) e α(apply 2) v α(apply 3) j i k
9 Lemmas on Demand Example: Formula Abstraction Example. Full Candidate Model and 0 and 2 eq eq 2 eq 5 and eq 4 2 ite 3 eq 3 α(apply ) e α(apply 2) v α(apply 3) j i k 0
10 Lemmas on Demand Example: Formula Abstraction Example. Full Candidate Model Check consistency: {apply, apply 2, apply 3} and 0 and 2 eq eq 2 eq 5 and eq 4 2 ite 3 eq 3 α(apply ) e α(apply 2) v α(apply 3) j i k 0
11 Lemmas on Demand Example: Formula Abstraction Example. Partial Candidate Model Check consistency: {apply } and 0 and 2 eq eq 2 eq 5 and X 2 ite 3 eq 4 eq 3 α(apply ) e α(apply 2) v α(apply 3) j i k 0
12 Partial Model Extraction Most intuitive: use justification-based approach Justification-based techniques in the context of SMT prune the search space of DPLL(T) [ENTCS 05, MSRTR 07] Model checking prune the search space of BMC [CAV 02] generalize proof obligations in PDR [EénFMCAD, ChoFMCAD ] generalize candidate counter examples (CEGAR) [LPAR 08]
13 Partial Model Extraction Our approach: Dual propagation-based partial model extraction exploiting the duality of a formula abstraction ψ assignments satisfying ψ (the primal channel) falsify its negation ψ (the dual channel) motivated by dual propagation techniques in QBF [AAAI 0] one solver with two channels (online approach) symmetric propagation between primal and dual channel here: offline dual propagation two solvers, one solver per channel consecutive propagation between primal and dual channel primal generates full assignment before dual enables partial model extraction based on the primal assignment
14 Partial Model Extraction Dual Propagation-Based Approach Example. Boolean Level Primal channel: ψ 2 (a b) (c d) Dual channel: ψ 2 ( a b) ( c d)
15 Partial Model Extraction Dual Propagation-Based Approach Example. Boolean Level Primal channel: ψ 2 (a b) (c d) Dual channel: ψ 2 ( a b) ( c d) Primal assignment: σ(ψ 2) {σ(a) =, σ(b) =, σ(c) =, σ(d) = }
16 Partial Model Extraction Dual Propagation-Based Approach Example. Boolean Level Primal channel: ψ 2 (a b) (c d) Dual channel: ψ 2 ( a b) ( c d) Primal assignment: σ(ψ 2) {σ(a) =, σ(b) =, σ(c) =, σ(d) = } Fix values of inputs via assumptions to the dual solver: Dual assumptions: {a=, b=, c=, d= }
17 Partial Model Extraction Dual Propagation-Based Approach Example. Boolean Level Primal channel: ψ 2 (a b) (c d) Dual channel: ψ 2 ( a b) ( c d) Primal assignment: σ(ψ 2) {σ(a) =, σ(b) =, σ(c) =, σ(d) = } Fix values of inputs via assumptions to the dual solver: Dual assumptions: {a=, b=, c=, d= } Failed assumptions: {a=, b= } sufficient to falsify ψ 2 sufficient to satisfy ψ 2
18 Partial Model Extraction Dual Propagation-Based Approach Example. Boolean Level Primal channel: ψ 2 (a b) (c d) Dual channel: ψ 2 ( a b) ( c d) Primal assignment: σ(ψ 2) {σ(a) =, σ(b) =, σ(c) =, σ(d) = } Fix values of inputs via assumptions to the dual solver: Dual assumptions: {a=, b=, c=, d= } Failed assumptions: {a=, b= } sufficient to falsify ψ 2 sufficient to satisfy ψ 2 Partial Model
19 Partial Model Extraction Dual Propagation-Based Approach structural don t care reasoning simulated via the dual solver no structural SAT solver necessary Example. (ctd) Input formula: ψ 2 (a b) (c d) Primal SAT solver: CNF(ψ 2) ( o x y) ( x o)? ( y o) ( x a) ( x b) ( a b x) ( y c) ( y d) ( c d y) Dual SAT solver: CNF( ψ 2) ( a b) ( c d) Dual assumptions: {a=, b=, c=, d= } Partial Model: {a =, b = } in contrast to partial model extraction techniques based on iterative removal of unnecessary assignments on the CNF level [FMCAD 3]
20 Partial Model Extraction Dual Propagation-Based Approach we lift this approach to the word level Primal channel: Dual channel: Γ Γ α(π) ξ α(π) l... l i one SMT solver per channel one single dual solver instance to maintain Γ over all iterations
21 Partial Model Extraction Dual Propagation-Based Approach Example. Word Level ψ i k (f(i) = e f(k) = v) v = ite(i = j, e, g(j)) α(ψ ) i k (α(apply ) = e α(apply 2) = v) v = ite(i = j, e, α(apply 3)) } Primal solver: α(ψ ) Formula abstraction and its negation Dual solver: α(ψ ) Primal assignment: σ(ψ 2) {σ(i) =, σ(j) =, σ(e) =, σ(v) =, σ(k) = 0, α(apply ) =, α(apply 2) =, α(apply 3) = } Fix values of inputs via assumptions to the dual solver: Dual assumptions: σ(ψ 2) {i =, j =, e =, v =, k = 0, α(apply ) =, α(apply 2) =, α(apply 3) = } Failed assumptions: {i =, j =, e =, v =, k = 0, α(apply ) = }
22 Partial Model Extraction Dual Propagation-Based Approach Example. Word Level ψ i k (f(i) = e f(k) = v) v = ite(i = j, e, g(j)) α(ψ ) i k (α(apply ) = e α(apply 2) = v) v = ite(i = j, e, α(apply 3)) } Primal solver: α(ψ ) Formula abstraction and its negation Dual solver: α(ψ ) Primal assignment: σ(ψ 2) {σ(i) =, σ(j) =, σ(e) =, σ(v) =, σ(k) = 0, α(apply ) =, α(apply 2) =, α(apply 3) = } Fix values of inputs via assumptions to the dual solver: Dual assumptions: σ(ψ 2) {i =, j =, e =, v =, k = 0, α(apply ) =, α(apply 2) =, α(apply 3) = } Failed assumptions: Partial Model {i =, j =, e =, v =, k = 0, α(apply ) = }
23 Partial Model Extraction Dual Propagation-Based Approach Example. Word Level ψ i k (f(i) = e f(k) = v) v = ite(i = j, e, g(j)) α(ψ ) i k (α(apply ) = e α(apply 2) = v) v = ite(i = j, e, α(apply 3)) } Primal solver: α(ψ ) Formula abstraction and its negation Dual solver: α(ψ ) Primal assignment: σ(ψ 2) {σ(i) =, σ(j) =, σ(e) =, σ(v) =, σ(k) = 0, α(apply ) =, α(apply 2) =, α(apply 3) = } Fix values of inputs via assumptions to the dual solver: Dual assumptions: σ(ψ 2) {i =, j =, e =, v =, k = 0, α(apply ) =, α(apply 2) =, α(apply 3) = } Failed assumptions: {i =, j =, e =, v =, k = 0, α(apply ) = } Consistency Check
24 Experimental Evaluation Configuration Four Configurations: Boolector sc version entering SMTCOMP 2, winner of the QF AUFBV track Boolector ba current Boolector base version (new LOD for Lambdas engine) Boolector dp with dual propagation-based partial model extraction enabled Boolector ju justification-based partial model extraction approach for comparison determine a posteriori observability don t cares skip lines that do not influence the output of an and-gate under its current assignment if both inputs of an and-gate are controlling ( ) skip either one based on a minimum cost heuristic
25 Experimental Evaluation Configuration Two Benchmark Sets: SMT 2: 49 benchmarks all non-extensional QF AUFBV benchmarks in SMTCOMP 2 Selected: 73 benchmarks all non-extensional QF AUFBV benchmarks (3696) in the SMT-LIB (pre-smtcomp 4) for which Boolector sc required at least 0 seconds 58 benchmarks shared between both sets all experiments on 2.83 GHz Intel Core 2 Quad machines with 8GB RAM running Ubuntu 2.04 time limit: 2 seconds, memory limit: 7GB
26 Experimental Evaluation Overview Overall results on sets SMT 2 and Selected. SMT 2 Selected Solver Solved (sat/unsat) TO MO Time [s] DS [s] Boolector sc 40 (83/57) Boolector ba 4 (83/58) Boolector ju 42 (84/58) Boolector dp 42 (84/58) Boolector sc 6 (72/44) Boolector ba 2 (76/45) Boolector ju 30 (85/45) Boolector dp 30 (85/45) TO... time out Time... total CPU time MO... memory out DS... dual solver overhead
27 Experimental Evaluation Overview Overall results on sets SMT 2 and Selected. SMT 2 Selected Solver Solved (sat/unsat) TO MO Time [s] DS [s] Boolector sc 40 (83/57) Boolector ba 4 (83/58) Boolector ju 42 (84/58) Boolector dp 42 (84/58) Boolector sc 6 (72/44) Boolector ba 2 (76/45) Boolector ju 30 (85/45) Boolector dp 30 (85/45) TO... time out Time... total CPU time MO... memory out DS... dual solver overhead SMT 2: additional instance (sat) Selected: 9 additional instances (all sat)
28 Experimental Evaluation Commonly Solved Instances Results for commonly solved instances on sets SMT 2 and Selected. SMT 2 Selected Solver Time [s] SAT [s] DS overhead [s] LOD Total Avg. Med. Total Avg. Med. Total Avg. Med. Total Avg. Med. Boolectorsc Boolectorba Boolectorju Boolectordp Boolectorsc Boolectorba Boolectorju Boolectordp Time... total CPU time DS overhead... dual solver overhead SAT... SAT solver runtime (primal solver) LOD... number of lemmas generated SMT 2: 39 (out of 49) benchmarks, 82 sat, 57 unsat not representative: 50% solved without a single refinement iteration Selected: 3 (out of 73) benchmarks, 70 sat, 43 unsat
29 Experimental Evaluation Commonly Solved Instances Results for commonly solved instances on sets SMT 2 and Selected. SMT 2 Selected Solver Time [s] SAT [s] DS overhead [s] LOD Total Avg. Med. Total Avg. Med. Total Avg. Med. Total Avg. Med. Boolectorsc Boolectorba Boolectorju Boolectordp Boolectorsc Boolectorba Boolectorju Boolectordp Time... total CPU time DS overhead... dual solver overhead SAT... SAT solver runtime (primal solver) LOD... number of lemmas generated Boolector sc implements old LOD engine new engine (Boolector ba ) struggles on a small set of benchmarks needs further investigation
30 Experimental Evaluation Commonly Solved Instances Results for commonly solved instances on sets SMT 2 and Selected. SMT 2 Selected Solver Time [s] SAT [s] DS overhead [s] LOD Total Avg. Med. Total Avg. Med. Total Avg. Med. Total Avg. Med. Boolectorsc Boolectorba Boolectorju Boolectordp Boolectorsc Boolectorba Boolectorju Boolectordp Time... total CPU time DS overhead... dual solver overhead SAT... SAT solver runtime (primal solver) LOD... number of lemmas generated sat solver runtime (SAT) Boolector dp most notable improvement on both sets
31 Experimental Evaluation Commonly Solved Instances Results for commonly solved instances on sets SMT 2 and Selected. SMT 2 Selected Solver Time [s] SAT [s] DS overhead [s] LOD Total Avg. Med. Total Avg. Med. Total Avg. Med. Total Avg. Med. Boolectorsc Boolectorba Boolectorju Boolectordp Boolectorsc Boolectorba Boolectorju Boolectordp Time... total CPU time DS overhead... dual solver overhead SAT... SAT solver runtime (primal solver) LOD... number of lemmas generated number of lemmas generated (LOD) SMT 2: Boolector ju least number of lemmas Boolector dp and Boolector ba approx. the same on 4 instances x more lemmas than Boolector ba Selected: Boolector dp most notable improvement
32 Experimental Evaluation Commonly Solved Instances Results for commonly solved instances on sets SMT 2 and Selected. SMT 2 Selected Solver Time [s] SAT [s] DS overhead [s] LOD Total Avg. Med. Total Avg. Med. Total Avg. Med. Total Avg. Med. Boolectorsc Boolectorba Boolectorju Boolectordp Boolectorsc Boolectorba Boolectorju Boolectordp Time... total CPU time DS overhead... dual solver overhead SAT... SAT solver runtime (primal solver) LOD... number of lemmas generated dual solver overhead 30-40% in total on 0% of the benchmarks 50-70% of the total runtime on >50% of the benchmarks <0% of the total runtime Boolector dp outperforms others disregarding DS overhead online dual propagation approach: DS overhead negligible
33 Experimental Evaluation Boolector dp vs Boolector ba 0 0 Boolector dp runtime [s] Boolector ba runtime [s] 0 0 Boolector ba runtime [s] DS overhead included DS overhead not included
34 Conclusion dual propagation-based optimization for Lemmas on Demand don t care reasoning on full candidate models improves performance our offline dual propagation-based approach competitive (in spite of introducing considerable overhead) Boolector ju won QF ABV track of SMTCOMP 4 Boolector dp came in close second Future work: online dual propagation approach, promises negligible or no dual solver overhead further improvment of overall performance by enabling partial model extraction even before a full candidate model has been generated requires interleaved execution between primal and dual solver
35 Appendix Boolector dp vs Boolector ju 0 0 Boolector dp runtime [s] Boolector ju runtime [s] 0 0 Boolector ju runtime [s] DS overhead included DS overhead not included
36 Appendix Boolector dp vs Boolector sc 0 0 Boolector dp runtime [s] Boolector sc runtime [s] 0 0 Boolector sc runtime [s] DS overhead included DS overhead not included
37 References I J. D. Bingham and A. J. Hu. Semi-formal bounded model checking. In CAV 02, volume 2404 of LNCS. Springer, 22. C. Barrett and J. Donham. Combining sat methods with non-clausal decision heuristics. ENTCS, 25(3), 25. L. de Moura and N. Bjørner. Relevancy propagation. Technical Report MSR-TR-27-40, Microsoft Research, 27. Z. S. Andraus, M. H. Liffiton, and K. A. Sakallah. Reveal: A formal verification tool for Verilog designs. In LPAR 08, volume 5330 of LNCS. Springer, 28. R. Brummayer and A. Biere. Lemmas on demand for the extensional theory of arrays. JSAT, 6(-3), 29. H. Chockler, A. Ivrii, A. Matsliah, S. Moran, and Z. Nevo. Incremental formal verification of hardware. In FMCAD. FMCAD Inc., 20. N. Eén, A. Mishchenko, and R. K. Brayton. Efficient implementation of property directed reachability. In FMCAD. FMCAD Inc., 20.
38 References II D. Déharbe, P. Fontaine, D. Le Berre and B. Mazure. Computing prime implicants. In FMCAD 3. IEEE, 203. A. Goultiaeva and F. Bacchus. Exploiting QBF duality on a circuit representation. In AAAI 0. AAAI Press, 2. M. Preiner, A. Niemetz and A. Biere. Lemmas on Demand for Lambdas. In DIFTS 3, volume 30 of CEUR Workshop Proceedings, 203.
Turbo-Charging Lemmas on Demand with Don t Care Reasoning
Turbo-Charging Lemmas on Demand with Don t Care Reasoning Aina Niemetz, Mathias Preiner, and Armin Biere Institute for Formal Models and Verification Johannes Kepler University, Linz, Austria Abstract
More informationLemmas on Demand for Lambdas
Lemmas on Demand for Lambdas Mathias Preiner, Aina Niemetz and Armin Biere Institute for Formal Models and Verification (FMV) Johannes Kepler University, Linz, Austria http://fmv.jku.at/ DIFTS Workshop
More informationImproving Local Search for Bit-Vector Logics in SMT with Path Propagation
Improving Local Search for Bit-Vector Logics in SMT with Path Propagation Aina Niemetz, Mathias Preiner, Andreas Fröhlich and Armin Biere Institute for Formal Models and Verification (FMV) Johannes Kepler
More informationCOUNTEREXAMPLE-GUIDED MODEL SYNTHESIS
COUNTEREXAMPLE-GUIDED MODEL SYNTHESIS Mathias Preiner, Aina Niemetz and Armin Biere Institute for Formal Models and Verification (FMV) Johannes Kepler University, Linz, Austria http://fmv.jku.at/ TACAS
More informationLEARNING TO INSTANTIATE QUANTIFIERS
LEARNING TO INSTANTIATE QUANTIFIERS Armin Biere 1 joint work with Mathias Preiner 1,2, Aina Niemetz 1,2 TACAS 17, SMT 17, PhD Thesis Mathias Preiner in 2017 1 Johannes Kepler University Linz 2 Stanford
More informationCOUNTEREXAMPLE-GUIDED MODEL SYNTHESIS
COUNTEREXAMPLE-GUIDED MODEL SYNTHESIS Mathias Preiner, Aina Niemetz and Armin Biere Johannes Kepler University Stanford University SMT Workshop July 22-23, 2017 Heidelberg, Germany Introduction Counterexample-Guided
More informationLemmas on Demand for the Extensional Theory of Arrays
Lemmas on Demand for the Extensional Theory of Arrays Robert Brummayer Armin Biere Institute for Formal Models and Verification Johannes Kepler University, Linz, Austria ABSTRACT Categories and Subject
More informationCOUNTEREXAMPLE-GUIDED MODEL SYNTHESIS
COUNTEREXAMPLE-GUIDED MODEL SYNTHESIS Mathias Preiner?y, Aina Niemetz?y and Armin Biere?? Johannes Kepler University y Stanford University SMT Workshop July 22-23, 2017 Heidelberg, Germany Introduction
More informationLocal Two-Level And-Inverter Graph Minimization without Blowup
Local Two-Level And-Inverter Graph Minimization without Blowup Robert Brummayer and Armin Biere Institute for Formal Models and Verification Johannes Kepler University Linz, Austria {robert.brummayer,
More informationBetter Lemmas with Lambda Extraction
Better Lemmas with Lambda Extraction Mathias Preiner, Aina Niemetz, and Armin Biere Johannes Kepler University, Linz, Austria Abstract In Satisfiability Modulo Theories (SMT), the theory of arrays provides
More informationCircuit versus CNF Reasoning for Equivalence Checking
Circuit versus CNF Reasoning for Equivalence Checking Armin Biere Institute for Formal Models and Verification Johannes Kepler University Linz, Austria Equivalence Checking Workshop 25 Madonna di Campiglio,
More informationBlocked Literals are Universal
Blocked Literals are Universal Marijn J.H. Heule 1, Martina Seidl 2, and Armin Biere 2 1 Department of Computer Science, The University of Texas at Austin, USA marijn@cs.utexas.edu 2 Institute for Formal
More informationEfficient Circuit to CNF Conversion
Efficient Circuit to CNF Conversion Panagiotis Manolios and Daron Vroon College of Computing, Georgia Institute of Technology, Atlanta, GA, 30332, USA http://www.cc.gatech.edu/home/{manolios,vroon} Abstract.
More informationNenofar: A Negation Normal Form SMT Solver
Nenofar: A Negation Normal Form SMT Solver Combining Non-Clausal SAT Approaches with Theories Philippe Suter 1, Vijay Ganesh 2, Viktor Kuncak 1 1 EPFL, Switzerland 2 MIT, USA Abstract. We describe an implementation
More informationCombinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets
ASP-DAC 2007 Yokohama Combinational Equivalence Checking Using Incremental SAT Solving, Output ing, and Resets Stefan Disch Christoph Scholl Outline Motivation Preliminaries Our Approach Output ing Heuristics
More informationddsmt: A Delta Debugger for the SMT-LIB v2 Format
ddsmt: A Delta Debugger for the SMT-LIB v2 Format Aina Niemetz and Armin Biere Institute for Formal Models and Verification Johannes Kepler University, Linz, Austria http://fmv.jku.at/ Abstract Delta debugging
More informationEfficiently Solving Bit-Vector Problems Using Model Checkers
Efficiently Solving Bit-Vector Problems Using Model Checkers Institute for Formal Models and Verification Johannes Kepler University, Linz, Austria http://fmv.jku.at SMT 2013 July 8 - July 9, 2013 Helsinki,
More informationA Toolbox for Counter-Example Analysis and Optimization
A Toolbox for Counter-Example Analysis and Optimization Alan Mishchenko Niklas Een Robert Brayton Department of EECS, University of California, Berkeley {alanmi, een, brayton}@eecs.berkeley.edu Abstract
More informationMinimum Satisfying Assignments for SMT. Işıl Dillig, Tom Dillig Ken McMillan Alex Aiken College of William & Mary Microsoft Research Stanford U.
Minimum Satisfying Assignments for SMT Işıl Dillig, Tom Dillig Ken McMillan Alex Aiken College of William & Mary Microsoft Research Stanford U. 1 / 20 Satisfiability Modulo Theories (SMT) Today, SMT solvers
More informationImproving Local Search for Bit-Vector Logics in SMT with Path Propagation
Improving Local Search for Bit-Vector Logics in SMT with Path Propagation Aina Niemetz, Mathias Preiner, Andreas Fröhlich, and Armin Biere Institute for Formal Models and Verification Johannes Kepler University,
More informationBlocked Clause Elimination
Blocked Clause Elimination Matti Järvisalo 1, Armin Biere 2, and Marijn Heule 3 1 Department of Computer Science, University of Helsinki, Finland 2 Institute for Formal Models and Verification, Johannes
More informationDeductive Methods, Bounded Model Checking
Deductive Methods, Bounded Model Checking http://d3s.mff.cuni.cz Pavel Parízek CHARLES UNIVERSITY IN PRAGUE faculty of mathematics and physics Deductive methods Pavel Parízek Deductive Methods, Bounded
More informationCAQE: A Certifying QBF Solver
CAQE: A Certifying QBF Solver Markus N. Rabe University of California, Berkeley rabe@berkeley.edu Leander Tentrup Saarland University tentrup@cs.uni-saarland.de Abstract We present a new CEGAR-based algorithm
More informationYices 2.2. Bruno Dutertre. Computer Science Laboratory, SRI International, 333 Ravenswood Avenue, Menlo Park, CA 94025, USA
Yices 2.2 Bruno Dutertre Computer Science Laboratory, SRI International, 333 Ravenswood Avenue, Menlo Park, CA 94025, USA bruno@csl.sri.com Abstract. Yices is an SMT solver developed by SRI International.
More informationResolve and Expand. Armin Biere
Resolve and Expand Armin Biere Johannes Kepler University Institute for Formal Models and Verification Altenbergerstrasse 69, A-4040 Linz, Austria biere@jku.at Abstract. We present a novel expansion based
More informationThe Barcelogic SMT Solver
The Barcelogic SMT Solver Tool Paper Miquel Bofill 1, Robert Nieuwenhuis 2, Albert Oliveras 2, Enric Rodríguez-Carbonell 2, and Albert Rubio 2 1 Universitat de Girona 2 Technical University of Catalonia,
More informationMotivation. CS389L: Automated Logical Reasoning. Lecture 17: SMT Solvers and the DPPL(T ) Framework. SMT solvers. The Basic Idea.
Motivation Lecture 17: SMT rs and the DPPL(T ) Framework şıl Dillig n previous lectures, we looked at decision procedures for conjunctive formulas in various first-order theories This lecture: How to handle
More informationBounded Model Checking with Parametric Data Structures
Bounded Model Checking with Marc Herbstritt (joint work with Erika Ábrahám, Bernd Becker, Martin Steffen) www.avacs.org August 15 2006 4th International Workshop on Bounded Model Checking Context Automated
More informationUninterpreted Function Abstraction and Refinement for Word-level Model Checking
Uninterpreted Function Abstraction and Refinement for Word-level Model Checking Yen-Sheng Ho 1, Alan Mishchenko 1, Robert Brayton 1 1 Department of EECS, University of California, Berkeley, CA, USA {ysho,
More informationSkolem Function Continuation for Quantified Boolean Formulas
Skolem Function Continuation for Quantified Boolean Formulas Katalin Fazekas 1, Marijn J. H. Heule 2, Martina Seidl 1, Armin Biere 1 1 Institute for Formal Models and Verification, JKU Linz, Austria 2
More informationLearning Support Sets in IC3 and Quip: the Good, the Bad, and the Ugly
Learning Support Sets in IC3 and Quip: the Good, the Bad, and the Ugly Ryan Berryhill Dept. of ECE University of Toronto Toronto, Canada ryan@eecg.toronto.edu Alexander Ivrii IBM Research Haifa, Israel
More informationLecture 2: Symbolic Model Checking With SAT
Lecture 2: Symbolic Model Checking With SAT Edmund M. Clarke, Jr. School of Computer Science Carnegie Mellon University Pittsburgh, PA 15213 (Joint work over several years with: A. Biere, A. Cimatti, Y.
More informationPluggable SAT-Solvers for SMT-Solvers
Pluggable SAT-Solvers for SMT-Solvers Bas Schaafsma DISI, University of Trento & Fondazione Bruno Kessler May 29, 2013 http://mathsat.fbk.eu/ 1 The SAT/SMT problem Applications of SAT/SMT-Solvers Motivation
More informationEfficiently Representing Existential Dependency Sets for Expansion-based QBF Solvers
MEMICS 2008 Efficiently Representing Existential Dependency Sets for Expansion-based QBF Solvers Florian Lonsing and Armin Biere 1 Institute for Formal Models and Verification Johannes Kepler University
More informationDPLL(Γ+T): a new style of reasoning for program checking
DPLL(Γ+T ): a new style of reasoning for program checking Dipartimento di Informatica Università degli Studi di Verona Verona, Italy June, 2011 Motivation: reasoning for program checking Program checking
More informationPreprocessing in Incremental SAT
Preprocessing in Incremental SAT Alexander Nadel 1 Vadim Rivchyn 1,2 Ofer Strichman 2 alexander.nadel@intel.com rvadim@tx.technion.ac.il ofers@ie.technion.ac.il 1 Design Technology Solutions Group, Intel
More informationCovered Clause Elimination
Covered Clause Elimination Marijn Heule TU Delft, The Netherlands Matti Järvisalo Univ. Helsinki, Finland Armin Biere JKU Linz, Austria Abstract Generalizing the novel clause elimination procedures developed
More informationCut-Based Inductive Invariant Computation
Cut-Based Inductive Invariant Computation Alan Mishchenko 1 Michael Case 1,2 Robert Brayton 1 1 Department of EECS, University of California, Berkeley, CA 2 IBM Systems and Technology Group, Austin, TX
More informationBOOSTER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstraction
BOOSTER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstraction Peer Johannsen Siemens AG, Corporate Technology, Design Automation, CT SE 4 81730 Munich, Germany peer.johannsen@mchp.siemens.de
More informationA Unified Proof System for QBF Preprocessing
A Unified Proof System for QBF Preprocessing Marijn J.H. Heule 1, Martina Seidl 2, and Armin Biere 2 1 Department of Computer Science, The University of Texas at Austin, USA marijn@cs.utexas.edu 2 Institute
More informationTemplate-based Circuit Understanding
Template-based Circuit Understanding Adrià Gascón 1 Pramod Subramanyan 2 Bruno Dutertre 1 Ashish Tiwari 1 Dejan Jovanović 1 Sharad Malik 2 1 SRI International 2 Princeton University Motivation Verify/reverse-engineer
More informationEECS 219C: Formal Methods Boolean Satisfiability Solving. Sanjit A. Seshia EECS, UC Berkeley
EECS 219C: Formal Methods Boolean Satisfiability Solving Sanjit A. Seshia EECS, UC Berkeley The Boolean Satisfiability Problem (SAT) Given: A Boolean formula F(x 1, x 2, x 3,, x n ) Can F evaluate to 1
More informationResolve and Expand. Armin Biere. Computer Systems Institute ETH Zürich, Switzerland
Resolve and Expand Armin Biere Computer Systems Institute ETH Zürich, Switzerland Abstract. We present a novel expansion based decision procedure for quantified boolean formulas (QBF) in conjunctive normal
More informationMechanically-Verified Validation of Satisfiability Solvers
Mechanically-Verified Validation of Satisfiability Solvers Nathan Wetzler The University of Texas at Austin Dissertation Proposal October 18, 2013 Outline Motivation and Proposal Satisfiability and Proofs
More informationPreprocessing in Pseudo-Boolean Optimization: An Experimental Evaluation
Preprocessing in Pseudo-Boolean Optimization: An Experimental Evaluation Ruben Martins, Inês Lynce, and Vasco Manquinho IST/INESC-ID, Technical University of Lisbon, Portugal {ruben,ines,vmm}@sat.inesc-id.pt
More informationFormally Certified Satisfiability Solving
SAT/SMT Proof Checking Verifying SAT Solver Code Future Work Computer Science, The University of Iowa, USA April 23, 2012 Seoul National University SAT/SMT Proof Checking Verifying SAT Solver Code Future
More informationApplying Multi-Core Model Checking to Hardware-Software Partitioning in Embedded Systems
V Brazilian Symposium on Computing Systems Engineering Applying Multi-Core Model Checking to Hardware-Software Partitioning in Embedded Systems Alessandro Trindade, Hussama Ismail, and Lucas Cordeiro Foz
More informationDRAT-trim: Efficient Checking and Trimming Using Expressive Clausal Proofs
DRAT-trim: Efficient Checking and Trimming Using Expressive Clausal Proofs Nathan Wetzler, Marijn J. H. Heule, and Warren A. Hunt, Jr. The University of Texas at Austin Abstract. The DRAT-trim tool is
More informationSymbolic and Concolic Execution of Programs
Symbolic and Concolic Execution of Programs Information Security, CS 526 Omar Chowdhury 10/7/2015 Information Security, CS 526 1 Reading for this lecture Symbolic execution and program testing - James
More informationHECTOR: Formal System-Level to RTL Equivalence Checking
ATG SoC HECTOR: Formal System-Level to RTL Equivalence Checking Alfred Koelbl, Sergey Berezin, Reily Jacoby, Jerry Burch, William Nicholls, Carl Pixley Advanced Technology Group Synopsys, Inc. June 2008
More informationXuandong Li. BACH: Path-oriented Reachability Checker of Linear Hybrid Automata
BACH: Path-oriented Reachability Checker of Linear Hybrid Automata Xuandong Li Department of Computer Science and Technology, Nanjing University, P.R.China Outline Preliminary Knowledge Path-oriented Reachability
More informationOpenSMT2: An SMT Solver for Multi-Core and Cloud Computing
OpenSMT2: An SMT Solver for Multi-Core and Cloud Computing Antti E. J. Hyvärinen, Matteo Marescotti, Leonardo Alt, and Natasha Sharygina Faculty of Informatics, University of Lugano Via Giuseppe Buffi
More informationEECS 219C: Computer-Aided Verification Boolean Satisfiability Solving. Sanjit A. Seshia EECS, UC Berkeley
EECS 219C: Computer-Aided Verification Boolean Satisfiability Solving Sanjit A. Seshia EECS, UC Berkeley Project Proposals Due Friday, February 13 on bcourses Will discuss project topics on Monday Instructions
More informationLookahead Saturation with Restriction for SAT
Lookahead Saturation with Restriction for SAT Anbulagan 1 and John Slaney 1,2 1 Logic and Computation Program, National ICT Australia Ltd., Canberra, Australia 2 Computer Sciences Laboratory, Australian
More informationSearching for Autarkies to Trim Unsatisfiable Clause Sets
Searching for Autarkies to Trim Unsatisfiable Clause Sets Mark Liffiton and Karem Sakallah Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor 48109-2121 {liffiton,karem}@eecs.umich.edu
More informationEvaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits
Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits André Sülflow Ulrich Kühne Robert Wille Daniel Große Rolf Drechsler Institute of Computer Science University of Bremen
More informationSeminar decision procedures: Certification of SAT and unsat proofs
Seminar decision procedures: Certification of SAT and unsat proofs Wolfgang Nicka Technische Universität München June 14, 2016 Boolean satisfiability problem Term The boolean satisfiability problem (SAT)
More informationA Scalable Algorithm for Minimal Unsatisfiable Core Extraction
A Scalable Algorithm for Minimal Unsatisfiable Core Extraction Nachum Dershowitz 1, Ziyad Hanna 2, and Alexander Nadel 1,2 1 School of Computer Science, Tel Aviv University, Ramat Aviv, Israel {nachumd,
More informationGenerating Small Countermodels. Andrew Reynolds Intel August 30, 2012
Generating Small Countermodels using SMT Andrew Reynolds Intel August 30, 2012 Acknowledgements Intel Corporation AmitGoel, Sava Krstic University of Iowa Cesare Tinelli, Francois Bobot New York University
More informationA Lightweight Component Caching Scheme for Satisfiability Solvers
A Lightweight Component Caching Scheme for Satisfiability Solvers Knot Pipatsrisawat and Adnan Darwiche {thammakn,darwiche}@cs.ucla.edu Computer Science Department University of California, Los Angeles
More informationMajorSat: A SAT Solver to Majority Logic
MajorSat: A SAT Solver to Majority Logic Speaker : Ching-Yi Huang Authors: Yu-Min Chou, Yung-Chih Chen *, Chun-Yao Wang, Ching-Yi Huang National Tsing Hua University, Taiwan * Yuan Ze University, Taiwan
More informationVersatile SAT-based Remapping for Standard Cells
Versatile SAT-based Remapping for Standard Cells Alan Mishchenko Robert Brayton Department of EECS, UC Berkeley {alanmi, brayton@berkeley.edu Thierry Besson Sriram Govindarajan Harm Arts Paul van Besouw
More informationA Tale Of Two Solvers: Eager and Lazy Approaches to Bit-vectors
A Tale Of Two Solvers: Eager and Lazy Approaches to Bit-vectors Liana Hadarean 1, Kshitij Bansal 1, Dejan Jovanović 3, Clark Barrett 1, and Cesare Tinelli 2 1 New York University 2 The University of Iowa
More informationA Proof-Sensitive Approach for Small Propositional Interpolants
A Proof-Sensitive Approach for Small Propositional Interpolants Leonardo Alt, Grigory Fedyukovich, Antti E. J. Hyvärinen, and Natasha Sharygina Formal Verification Lab, USI, Switzerland Abstract. The labeled
More informationOpenSMT2. A Parallel, Interpolating SMT Solver. Antti Hyvärinen, Matteo Marescotti, Leonardo Alt, Sepideh Asadi, and Natasha Sharygina
OpenSMT2 A Parallel, Interpolating SMT Solver Antti Hyvärinen, Matteo Marescotti, Leonardo Alt, Sepideh Asadi, and Natasha Sharygina Why another SMT solver? Model checking OpenSMT Interpolation Parallel
More informationEfficiently Solving Bit-Vector Problems Using Model Checkers
Efficiently Solving Bit-Vector Problems Using Model Checkers Andreas Fröhlich, Gergely Kovásznai, Armin Biere Institute for Formal Models and Verification Johannes Kepler University, Linz, Austria Abstract
More informationSimulating Circuit-Level Simplifications on CNF
Journal of Automated Reasoning manuscript No. (will be inserted by the editor) Simulating Circuit-Level Simplifications on CNF Matti Järvisalo Armin Biere Marijn Heule Received: date / Accepted: date Abstract
More informationTree Interpolation in Vampire
Tree Interpolation in Vampire Régis Blanc 1, Ashutosh Gupta 2, Laura Kovács 3, and Bernhard Kragl 4 1 EPFL 2 IST Austria 3 Chalmers 4 TU Vienna Abstract. We describe new extensions of the Vampire theorem
More informationTrimming while Checking Clausal Proofs
Trimming while Checking Clausal Proofs Marijn J.H. Heule, Warren A. Hunt, Jr., and Nathan Wetzler The University of Texas at Austin Abstract Conflict-driven clause learning (CDCL) satisfiability solvers
More informationComplete Instantiation of Quantified Formulas in Satisfiability Modulo Theories. ACSys Seminar
Complete Instantiation of Quantified Formulas in Satisfiability Modulo Theories Yeting Ge Leonardo de Moura ACSys Seminar 2008.12 Motivation SMT solvers have been successful Quantified smt formulas are
More informationExploiting Structure in an AIG Based QBF Solver
Exploiting Structure in an AIG Based QBF Solver Florian Pigorsch and Christoph Scholl Albert-Ludwigs-Universität Freiburg, Institut für Informatik, D-79110 Freiburg im Breisgau, Germany {pigorsch, scholl}@informatik.uni-freiburg.de
More informationPKIND: A parallel k-induction based model checker
PKIND: A parallel k-induction based model checker Temesghen Kahsai The University of Iowa temesghen-kahsaiazene@uiowa.edu Cesare Tinelli The University of Iowa cesare-tinelli@uiowa.edu PKIND is a novel
More informationBoolean Satisfiability: From Theoretical Hardness to Practical Success. Sharad Malik Princeton University
Boolean Satisfiability: From Theoretical Hardness to Practical Success Sharad Malik Princeton University SAT in a Nutshell Given a Boolean formula, find a variable assignment such that the formula evaluates
More informationSAT/SMT summer school 2015 Introduction to SMT
SAT/SMT summer school 2015 Introduction to SMT Alberto Griggio Fondazione Bruno Kessler Trento, Italy Some material courtesy of Roberto Sebastiani and Leonardo de Moura Outline Introduction The DPLL(T)
More informationImproving Glucose for Incremental SAT Solving with Assumptions: Application to MUS Extraction. Gilles Audemard Jean-Marie Lagniez and Laurent Simon
Improving Glucose for Incremental SAT Solving with Assumptions: Application to MUS Extraction Gilles Audemard Jean-Marie Lagniez and Laurent Simon SAT 2013 Glucose and MUS SAT 2013 1 / 17 Introduction
More informationLingeling Essentials POS 2014
Lingeling Essentials Design and Implementation Aspects Armin Biere Johannes Kepler University Linz, Austria POS 2014 5th Workshop on Pragmatics of SAT 2014 SAT 2014 / FLoC 2014 Vienna Summer of Logic Vienna,
More informationExtended Abstract: Combining a Logical Framework with an RUP Checker for SMT Proofs
Extended Abstract: Combining a Logical Framework with an RUP Checker for SMT Proofs Duckki Oe and Aaron Stump Computer Science The University of Iowa Abstract We describe work in progress on a new approach,
More informationVS 3 : SMT Solvers for Program Verification
VS 3 : SMT Solvers for Program Verification Saurabh Srivastava 1,, Sumit Gulwani 2, and Jeffrey S. Foster 1 1 University of Maryland, College Park, {saurabhs,jfoster}@cs.umd.edu 2 Microsoft Research, Redmond,
More informationYices 1.0: An Efficient SMT Solver
Yices 1.0: An Efficient SMT Solver SMT-COMP 06 Leonardo de Moura (joint work with Bruno Dutertre) {demoura, bruno}@csl.sri.com. Computer Science Laboratory SRI International Menlo Park, CA Yices: An Efficient
More informationBroadening the Scope of SMT-COMP: the Application Track
Broadening the Scope of SMT-COMP: the Application Track Roberto Bruttomesso 1 and Alberto Griggio 2 1 Atrenta France 2 Fondazione Bruno Kessler Abstract. During the last decade, SMT solvers have seen impressive
More informationRefinement Strategies for Verification Methods Based on Datapath Abstraction
Refinement Strategies for Verification Methods Based on Datapath Abstraction Zaher S. Andraus, Mark H. Liffiton, and Karem A. Sakallah Department of Electrical Engineering and Computer Science University
More informationUsing Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability
Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability Robert Wille Daniel Große Mathias Soeken Rolf Drechsler Institute of Computer Science University of Bremen,
More informationIntegrating an AIG Package, Simulator, and SAT Solver
Integrating an AIG Package, Simulator, and SAT Solver Alan Mishchenko Robert Brayton Department of EECS, UC Berkeley {alanmi, brayton}@berkeley.edu Abstract This paper focuses on problems where the interdependence
More informationFast Generation of Lexicographic Satisfiable Assignments: Enabling Canonicity in SAT-based Applications
Fast Generation of Lexicographic Satisfiable Assignments: Enabling Canonicity in -based Applications Ana Petkovska 1 ana.petkovska@epfl.ch Giovanni De Micheli 1 giovanni.demicheli@epfl.ch Alan Mishchenko
More informationOn Computing Minimum Size Prime Implicants
On Computing Minimum Size Prime Implicants João P. Marques Silva Cadence European Laboratories / IST-INESC Lisbon, Portugal jpms@inesc.pt Abstract In this paper we describe a new model and algorithm for
More informationIntegration of SMT-LIB Support into Maple
Integration of SMT-LIB Support into Maple SMT-CAS Integration Some SMT solvers presently incorporate computer algebra techniques in their theory solvers. Examples: verit [3], SMT-RAT [4] Alternate avenue
More informationarxiv: v2 [cs.pl] 3 Apr 2018
1 Scheduling Constraint Based Abstraction Refinement for Multi-Threaded Program Verification arxiv:1708.08323v2 [cs.pl] 3 Apr 2018 LIANGZE YIN, School of Computer, National University of Defense Technology,
More informationTighter Integration of BDDs and SMT for Predicate Abstraction
Tighter Integration of BDDs and SMT for Predicate Abstraction A. Cimatti, A. Franzen, A. Griggio, K. Kalyanasundaram, M. Roveri FBK-irst, Trento, Italy {cimatti,franzen,krishnamani,roveri}@fbk.eu University
More informationSAT Solvers: A Condensed History. Sharad Malik Princeton University COS 598d 3/1/2010
SAT Solvers: A Condensed History Sharad Malik Princeton University COS 598d 3/1/2010 Where are we today? Intractability of the problem no longer daunting Can regularly handle practical instances with millions
More informationParallelizing Partial MUS Enumeration
Parallelizing Partial MUS Enumeration Wenting Zhao and Mark Liffiton Department of Computer Science Illinois Wesleyan University {wzhao,mliffito}@iwu.edu http://www.iwu.edu/~mliffito/marco/ ICTAI November
More informationProvably Optimal Test Cube Generation using Quantified Boolean Formula Solving
Provably Optimal Test Cube Generation using Quantified Boolean Formula Solving ASP-DAC 2013 Albert-Ludwigs-Universität Freiburg Matthias Sauer, Sven Reimer, Ilia Polian, Tobias Schubert, Bernd Becker Chair
More informationSAT, SMT and QBF Solving in a Multi-Core Environment
SAT, SMT and QBF Solving in a Multi-Core Environment Bernd Becker Tobias Schubert Faculty of Engineering, Albert-Ludwigs-University Freiburg, 79110 Freiburg im Breisgau, Germany {becker schubert}@informatik.uni-freiburg.de
More informationCAV Verification Mentoring Workshop 2017 SMT Solving
CAV Verification Mentoring Workshop 2017 SMT Solving Alberto Griggio Fondazione Bruno Kessler Trento, Italy The SMT problem Satisfiability Modulo Theories Given a (quantifier-free) FOL formula and a (decidable)
More informationJPF SE: A Symbolic Execution Extension to Java PathFinder
JPF SE: A Symbolic Execution Extension to Java PathFinder Saswat Anand 1,CorinaS.Păsăreanu 2, and Willem Visser 2 1 College of Computing, Georgia Institute of Technology saswat@cc.gatech.edu 2 QSS and
More informationDPLL(T ):Fast Decision Procedures
DPLL(T ):Fast Decision Procedures Harald Ganzinger George Hagen Robert Nieuwenhuis Cesare Tinelli Albert Oliveras MPI, Saarburcken The University of Iowa UPC, Barcelona Computer Aided-Verification (CAV)
More informationNina Narodytska Samsung Research/CMU
Recent trends in MaxSAT solving Nina Narodytska Samsung Research/CMU Outline 1. Boolean satisfiability 2. Boolean (un)satisfiability (MaxSAT) 3. Counting (un)satisfiability 2 Outline Boolean satisfiability
More informationAbstraction Refinement for Bounded Model Checking
Abstraction Refinement for Bounded Model Checking Anubhav Gupta 1 and Ofer Strichman 2 1 School of Computer Science, Carnegie Mellon University, USA anubhav@cs.cmu.edu 2 Information Systems Engineering,
More informationSAT-Based Area Recovery in Technology Mapping
SAT-Based Area Recovery in Technology Mapping Bruno Schmitt Ecole Polytechnique Federale de Lausanne (EPFL) bruno@oschmitt.com Alan Mishchenko Robert Brayton Department of EECS, UC Berkeley {alanmi, brayton}@berkeley.edu
More informationAutomated Testing and Debugging of SAT and QBF Solvers
Automated Testing and Debugging of SAT and QBF Solvers JKU Linz, Austria 13 th International Conference on Theory and Applications of Satisfiability Testing July 13, 2010 Edinburgh, Scotland, UK Outline
More informationBusy Man s Synthesis: Combinational Delay Optimization With SAT
Busy Man s Synthesis: Combinational Delay Optimization With SAT Mathias Soeken 1 Giovanni De Micheli 1 Alan Mishchenko 2 1 Integrated Systems Laboratory, EPFL, Lausanne, Switzerland 2 Department of EECS,
More information