EE382N.23: Embedded System Design and Modeling

Transcription

1 EE382N.23: Embedded System Design and Modeling Lecture 3 Language Semantics Andreas Gerstlauer Electrical and Computer Engineering University of Texas at Austin gerstl@ece.utexas.edu Lecture 3: Outline Language semantics Models of concurrency & time Discrete event model Synchronous reactive model SpecC semantics Formal semantics Simulation semantics EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 1

2 System-Level Language Semantics Language concepts (syntax) Behavioral and structural hierarchy Concurrency and time Synchronization and communication Exception handling State transitions Language semantics needed to define the meaning Semantics of execution for modeling, simulation, synthesis Model of concurrency, time, synchronization, communication Determinism vs. non-determinism Atomicity EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 3 Reactive System Model Concurrent processes Simultaenous processing of multiple inputs and outputs Block diagram as graphical representation f() f() f() Execute (simulate) and synthesize Semantics of a block diagram? Meaning of concurrency and time? EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 2

3 Models of Time (Order) Physical Continuous time, total order Physical components naturally interleaved in (very fine) time Differential equations, Hybrid models Logical Discrete time, partial order Discrete instants of time (time tags t 0 < t 1 <... t k <... ), nothing in between Unspecified interleaving of events with same time tag Freedom of implementation Simulation & execution, Design languages Untimed Partial order based on causality only No ordering in time, explicit dependencies only Free of implementation (purely behavioral) Specification & programming, Models of computation (Lecture 3 & 4) EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 5 (Logical) Concurrency Events/actions happening at the same time Undefined, unspecified or unknown order Implementation/simulation determines actual interleaving Communication/synchronization establishes causal order Partial order t i f() t o? t i f() t o? t i f() t o? Fundamental issues Non-determinism Causality loops EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 3

4 Language Semantics Motivating example 1 Given: 1(int x) ; 2(int x) x = 6; ; B1 B2 int x; B1 b1(x); B2 b2(x); b1; b2; ; What is the value of x after the execution of B? Answer: x = 6 EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 7 Language Semantics Motivating example 2 Given: 1(int x) ; B1 2(int x) x = 6; ; t B2 t int x; B1 b1(x); B2 b2(x); parb1; b2; ; What is the value of x after the execution of B? Answer: The program is non-deterministic! (x may be 5, or 6, or any other value!) EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 4

5 Language Semantics Motivating example 3 Given: 1(int x) waitfor 10; ; B1 2(int x) x = 6; ; t+10 t B2 int x; B1 b1(x); B2 b2(x); parb1; b2; ; What is the value of x after the execution of B? Answer: x = 5 EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 9 Language Semantics Motivating example 4 Given: 1(int x) waitfor 10; ; B1 2(int x) waitfor 10; x = 6; ; t+10 t+10 B2 int x; B1 b1(x); B2 b2(x); parb1; b2; ; What is the value of x after the execution of B? Answer: The program is non-deterministic! (x may be 5, or 6, or any other value!) EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 5

6 Language Semantics Motivating example 5 Given: 1( notify e; ; What is the value of x after the execution of B? Answer: x = 6 B1 2( wait e; x = 6; ; t B2 int x; event e; B1 b1(x,e); B2 b2(x,e); parb1; b2; ; EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 11 Simultaneous Events t A B C t (event a, event b) while (true) wait(a); notify(b); ; behavior C(event a, event b) while(true) // a or b wait(a, b); ; Suppose B is invoked first t A B C t Depending on simulator Process C might be invoked once, observing both inputs in one invocation Process C might be invoked twice, processing events one at a time Non-deterministic order of event processing Source: M. Jacome, UT Austin. EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 6

7 Delta (Superdense) Time Two-level model of time Break each time instant into multiple delta steps Each zero delay event results in a delta step Delta time has zero delay but imposes semantic order delta time offset delta steps time steps time value t+ t+ t+2 A B C Answer: C is invoked twice Source: M. Jacome, UT Austin. EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 13 Delta Semantics Motivating example 5 Given: 1( notify e; ; What is the value of x after the execution of B? Answer: x = 6 B1 2( wait e; x = 6; ; t + B2 int x; event e; B1 b1(x,e); B2 b2(x,e); parb1; b2; ; EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 7

8 Delta Semantics Motivating example 6 Given: 1( notify e; ; What is the value of x after the execution of B? Answer: x = 6 B1 2( wait e; x = 6; ; t + B2 int x; event e; B1 b1(x,e); B2 b2(x,e); parb1; b2; ; EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 15 Delta Semantics Motivating example 7 Given: 1( notify e; x = 4; notify e; ; What is the value of x after the execution of B? Answer: B2 never terminates (x = 6) B1 2( wait e; x = 6; wait e; x = 7; ; t + B2 int x; event e; B1 b1(x,e); B2 b2(x,e); parb1; b2; ; EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 8

9 Delta Semantics Motivating example 8 Given: 1( waitfor 10; notify e; ; What is the value of x after the execution of B? Answer: x = 6 B1 2( wait e; x = 6; ; t +10+ B2 int x; event e; B1 b1(x,e); B2 b2(x,e); parb1; b2; ; EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 17 Delta Semantics Motivating example 9 Given: 1( notify e; ; What is the value of x after the execution of B? Answer: B2 never terminates! (the event is lost) B1 2( waitfor 10; wait e; x = 6; ; t + B2 int x; event e; B1 b1(x,e); B2 b2(x,e); parb1; b2; ; EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 9

10 Delta Semantics Resolve some non-determinism As long as each output has unique delta delay Often not the case, e.g. in SpecC Example 2, Example 4 t+ t+2 A B C Ambiguity still exists Shared resource/variable accesses in same delta cycle With B->C sharing: B or C first? Undefined order, non-deterministic Example on slide 12 with variables: value of bout on first invocation of C? Alternative semantics based on precedence analysis Graph is executed in topologically sorted order [Ptolemy] C only invoked once, with B->C dependency: B invoked first Potentially still ambiguous If there is no B->C dependency: B or C first? Only matters if there are other side effects (printf()) EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 19 t+ bout = 42; bout? Source: M. Jacome, UT Austin. Deterministic Communication Given 1( out notify e; ; 2( in int y, z; y = x; wait e; z = x; ; int x = 0; event e; B1 b1(x,e); B2 b2(x,e); parb1; b2; ; What is the value of (y,z) at the end of execution? Answer: z = 5, y is non-deterministic (0 or 5) EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 10

11 Deterministic Communication Delta-semantics for variables [VDHL, Verilog, SpecC] Signals combine event with current/new value updates 1( out int signal x, int event x e) notify x; e; // implicit ; 2( in int signal x, int event x e) int y, z; ; y = x; wait x; e; z = x; int signal x = int 0; x = 0; event e; B1 b1(x); b1(x,e); B2 b2(x); b2(x,e); parb1; b2; ; What is the value of (y,z) at the end of execution? Answer: z = 5, y = 0 Resolves concurrent read-write Concurrent writes still a problem Non-deterministic [SpecC], resolution functions [VHDL, Verilog] EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 21 Deterministic Communication Avoid event loss by combining event with flag 1(int x, bool flag, event e) waitfor(d1); flag = true; notify e; ; 2(int x, bool flag, event e) waitfor(d2); if (!flag) wait e; flag = false; x = 6; ; int x; bool f = false; event e; B1 b1(x,f,e); B2 b2(x,f,e); parb1; b2; ; What is the value of x at the end of execution? Answer: actually, can end up being x = 5, why? Race conditions, interleaving of B1 and B2 if D1 == D2 Encapsulate in channel (see c_handshake) Code in SpecC channel methods is atomic! EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 11

12 Zero-Delay Feedback Loops Causality loop Where to start & stop? Progress? A B C Reject zero-delay cycles Forbid all zero delay (every t must be strictly > 0) [DEVS] Detect (compile error on zero cycle) Delta cycle semantics Oscillate with no time progress [Zeno machine/model] Approaches based on topological sorting Annotate feedback arcs to break for ordering purposes Insert explicit delay block [Ptolemy] Potentially same oscillation without progress Source: M. Jacome, UT Austin. EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 23 Discrete Event (DE) Model General, universal model for system simulation Hardware [VHDL, Verilog], system [SpecC, SystemC], network [OMNet] Formal, generic discrete time model Signals = globally ordered streams of events Event e i = (value, tag), discrete time tags Asynchronous event processing Execute block on input event i 1, i 2, i 3, Process input and generate output events with tag+ t Flexible Multi-scale, arbitrary dynamic delays Efficient Event-driven, only evaluate when necessary t = t a x 1, x 2, x 3, y 1, y 2, y 3, v 1, v 2, v 3, o 1, o 2, o 3, t = t b z 1, z 2, z 3, t = t c Synthesis challenges Semantics: simultaneous events (non-determinism), zero-delay cycles Implementation: global order (maintain global notion of time) [PTIDES] EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 12

13 Synchronous Reactive (SR) Model Synchronous hypothesis Sequence of discrete lock steps (ticks of logical clock) Reactions are instantaneous (zero time) Events are simultaneous (broadcast) Deterministic, static verifiable (independent of actual delays) t = 0 Precedence analysis, topological sort No arbitrary shared variables Synthesis challenges: Semantics: causality loops, conflicts? Implementation: broadcast events, global clock t = 0 t = 0 t = 0 t = 0 t = 0 t = 0 Synchronous languages Imperative (control) [Esterel] or declarative (data) [Lustre] style Reject cycles [Lustre] or require unique fixed-point [Esterel] Hardware (FSMs) or software (safety critical) compilers EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 25 The Esterel Language Synchronous, imperative language [Berry 83] Structural hierarchy module <name> <b> end module input <ports>, output <ports> Behavior loop await A Sequential: <p> ; <q> emit O Concurrent: <p> <q> each R Multiform time Sequence of logical instants (cycles) module ABRO: input A, B, R; output O; [ await A await B ]; Shortcut for: end module trap T in loop Statements take zero time (same instant) or delay for a number of cycles Delay for one cycle: pause pause; present A then exit T end end loop Broadcast signals (valued or unvalued) end Present or absent in each instant (default to absent in each new cycle) emit <s>(<v>): Make signal <s> present in current instant (optional value) Control (branch, loop, exceptions) present <s> then <p> else <q> end (in current instant) loop <b> end / loop <b> each <s> (restart when <s> is present) trap <s> in <b> end (use exit <s> inside <b>), suspend <b> when <s> EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 13

14 Esterel Semantics Instantaneous communication Signal emitted in a cycle is visible immediately [ pause; emit A; pause; emit A pause; present A then emit B end ] A B A Bi-directional communication Can communicate back and forth in same cycle [ pause; emit A; present B then emit C end; pause; emit A pause; present A then emit B end ] A B C A Source: S. Edwards, Columbia EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 27 Esterel Semantics Signal coherence Signals can not be both absent and present Writers run before readers do present A else emit A; Causality No contradictory or non-deterministic programs (cycles) present S1 else emit S2 end; present S2 else emit S1 end; Instantaneous loops Loops must have at least one statement with delay loop emit A end Erroneous programs, rejected by compiler Statically verified, guaranteed deterministic Source: S. Edwards, Columbia EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 14

15 DE vs. SR (1) N(AND) A(ND) I(NV) t 0 1 t t 1 1? t > 0 t = 0 (eval. order) Pure DE [DEVFS] illegal DE w/ delta & variables [?] ? 1 (A, I / N, N) w/ delta & signals [HDLs] (A, I / N, N) w/ topol. sort [Ptolemy] (A, I, N) SR [Esterel] unsupported 1 1 (A, I, N) A(ND) t I(NV) t N(AND) EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 29 t 1? 0 1 t > 0 t = 0 Pure DE [DEVFS] 1 1 illegal DE w/ delta & signals [HDLs] w/ topol. sort [Ptolemy] (w/ delta block) SR [Esterel] unsupported 1 1 DE vs. SR (2) Discrete-event (DE) w/ delta cycles Can accurately model sub-cycle timing & glitching effects Non-determinism with shared variables/resources Issues with oscillation in case of cycles Discrete-event (DE) w/ topological sort Deterministic if there are no other side effects Requires explicit modifications to break cycles Synchronous-reactive (SR) Consistent & fully deterministic Combines toplogical sorting with fixed-point But restricted model of time (global ticks only) EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 15

16 Lecture 3: Outline Language semantics Models of concurrency & time Discrete event model Synchronous reactive model SpecC semantics Formal semantics Simulation semantics EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 31 Specifying Language Semantics Language semantics are needed for System designer (understanding) Tools Validation (compilation, simulation) Formal verification (equivalence, property checking) Synthesis Documentation and standardization Objective: Clearly define the execution semantics of the language Requirements and goals: completeness precision (no ambiguities) abstraction (no implementation details) formality (enable formal reasoning) simplicity (easy understanding) EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 16

17 SpecC Language Semantics Documentation Language Reference Manual (LRM) set of rules written in English (not formal) Abstract simulation algorithm set of valid implementations (not general) Reference implementation SpecC Reference Compiler and Simulator one instance of a valid implementation (not general) Compliance test bench set of specific test cases (incomplete) Formal execution semantics Time-interval formalism rule-based formalism (incomplete) Abstract State Machines fully formal approach (not easy to understand) EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 33 Formal Semantics Two examples of semantics definition: 1) Time-interval formalism Definition of execution semantics of SpecC V2.0 [SpecC LRM 02] Formal definition of timed execution semantics Sequentiality, concurrency, synchronization Allows reasoning over execution order, dependencies 2) Abstract State Machines Formalism of Evolving Algebras [Gurevich 87] Complete execution semantics of SpecC V1.0 [Mueller 02] wait, notify, notifyone, par, pipe, traps, interrupts operational semantics (no data types!) Influence on the definition of SpecC V2.0 Straightforward extension for SpecC V2.0 Comparable to ASM specifications of SystemC and VHDL 93 EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 17

18 Simulation Semantics Abstract simulation algorithm for SpecC available in LRM (appendix), good for understanding set of valid implementations not general (possibly incomplete) Definitions: At any time, each thread t is in one of the following sets: READY: set of threads ready to execute (initially root thread) WAIT: set of threads suspended by wait (initially Ø) WAITFOR: set of threads suspended by waitfor (initially Ø) Notified events are stored in a set N notify e1 adds event e1 to N wait e1 will wakeup when e1 is in N Consumption of event e means event e is taken out of N Expiration of notified events means N is set to Ø EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 35 Simulation Semantics Abstract simulation algorithm for SpecC Start Select thread t READY, execute t notify wait waitfor NO YES YES YES Add notified events to N Move t READY to WAIT Move t READY to WAITFOR READY=Ø Set N=Ø READY=Ø Update simulation time, move earliest t WAITFOR to READY READY=Ø Stop NO YES EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 36 YES YES NO Move all t WAIT waiting for events e N to READY NO 2017 A. Gerstlauer 18

19 Simulation Semantics Abstract simulation algorithm for SpecC Discrete-event model utilizes delta-cycle mechanism matches execution semantics of other languages» SystemC» VHDL» Verilog Features clearly specifies the simulation semantics easily understandable can easily be implemented Generality is one valid implementation of the semantics other valid implementations may exist as well EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 37 Discrete Event Simulation (DES) Traditional DES Concurrent threads of execution Managed by a central scheduler Driven by events and time advances Delta-cycle Time-cycle Partial temporal order with barriers th 1 th 2 th 3 th 4 T: 0:0 Reference simulators Both SystemC and SpecC use cooperative multi-threading A single thread is active at any time! Cannot exploit multiple parallel cores Example: SystemC 10:0 10:1 EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 19

20 Discrete Event Simulation (DES) SLDL semantics SystemC prescribes Cooperative Multi-Threading SystemC LRM defines: process instances execute without interruption Preemptive interleaving forbidden Parallelizing not possible SpecC specifies Preemptive Multi-Threading SpecC LRM defines: preemptive execution, No atomicity is guaranteed Preemptive interleaving assumed Can be parallelized Need critical regions with mutually exclusive access: Channels! Locks inserted by compiler in parallel mode th 1 th 2 th 3 th 4 T: 0:0 10:0 10:1 10:2 20:0 20:1 20:2 30:0 EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 39 Discrete Event Simulation (DES) Traditional DE simulation algorithm Threads managed in READY queue Scheduler picks a single thread and executes it Time advances In delta-cycle In timed-cycle EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 20

21 Parallel Discrete Event Simulation (PDES) Parallel DE simulation algorithm Threads managed in READY queue Parallel delta cycle Scheduler picks N threads and executes them in parallel N = number of available CPU cores Time advances In delta-cycle In timed-cycle EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 41 Parallel Discrete Event Simulation (PDES) Parallel DES Threads execute in parallel iff in the same delta cycle, and in the same time cycle Significant speed up! But: Amdahl s Law still applies! Cycle bounds are absolute barriers th 1 th 2 th 3 th 4 T: 0:0 10:0 10:1 10:2 Aggressive PDES Optimistic Let threads run ahead in time Rollback if conflict detected (event in the past) Conservative Only run ahead if guaranteed no conflicts E.g. static code/dependency analysis 20:0 20:1 20:2 30:0 EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 21

22 Out-of-Order Parallel DES (OoO PDES) Out-of-Order PDES Threads execute in parallel iff in the same delta cycle, and in the same time cycle, OR if there are no conflicts! Can utilize advanced compiler for static data conflict analysis Allows as many threads in parallel as possible Significantly higher speedup! Results at [Chen 12], [Chen 14] Fully preserves DES execution semantics Accuracy in results and timing th 1 th 2 th 3 th 4 T: 0:0 10:0 10:1 10:2 20:0 20:1 20:2 30:0 EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 43 Lecture 3: Summary Discrete event (DE) model of computation Universal model for simulation of concurrent systems Challenging to synthesize or implement concurrently Delta cycles, global order SpecC language semantics Formal semantics Simulation semantics Simulation algorithm Parallel discrete event simulation Hierarchy of models Models of computation (MoCs) for specification Discrete event (DE) model for simulation Capture & simulate other MoCs in a DE language [SpecC] EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 22