A Local Optimal Method on DSA Guiding Template Assignment with Redundant/Dummy Via Insertion
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1 A Loca Optima Method on DSA Guiding Tempate Assignment with Redundant/Dummy Via Insertion Xingquan Li 1, Bei Yu 2, Jiani Chen 1, Wenxing Zhu 1, 24th Asia and South Pacific Design T h e p i c Automation Conference t u r e c a n 't b e Tokyo Japan d 2019 i s p a y e d. 1 Fuzhou University 2 The Chinese University of Hong Kong 1
2 Outine Introductions Probem Formuation Agorithm Experimenta Resuts Concusions 2
3 Outine Introductions Probem Formuation Agorithm Experimenta Resuts Concusions 3
4 Bock Copoymers Directed Sef-Assemby (DSA) Bock copoymer (BCP) A unique string of two types of poymer. One type of poymer is hydrophiic and another is hydrophobic. Nanostructures Cyinders, spheres, and ameae. The cyindrica nanostructure is suitabe for patterning contacts and vias. Poymer-A (PS) Poymer-B (PMMA) Lameae (A=B) Cyinders (A>B) 4
5 Via Via group DSA Process Vias are not reguary paced in practica ayout. A simpe reguar hoe array generated by standard DSA is not suitabe for IC fabrication. Topoogica tempate guided DSA process has been proposed to support patterning irreguary vias ayout. Cosed vias are grouped; And a guiding tempate is identified for each group. Guiding tempate Meta v3 DSA pattern 5
6 DSA Process Given a vias ayout, we shoud assign the guiding tempates for every via. Guiding tempates are patterned on a wafer through optica ithography. Each guiding tempate is fied with BCPs. DSA can be controed by therma anneaing process. Guided by tempate Pattern tempate by 193i DSA design process 6
7 Guiding Tempates Pre-defined DSA pattern set to improve robust. Within-group contact/via distance. Compex shapes are difficut to print. Unexpected hoes and pacement error of hoes for some patterns. The distance of any two guiding tempates shoud arger than minimum optica resoution spacing d s. d s v3 7
8 Redundant Via Insertion (RVI) Insert an extra via near a singe via. Prevent via faiure, improve circuit yied and reiabiity. v3 r r2 r v r r r2 r3 v3 8
9 Dummy Via Due to the characteristic of DSA, vias in a group must match some specific patterns so that they can be assigned to the same guiding tempate. Increase the choices to form guiding tempates with the hep of dummy via insertion. r2 r3 r2 r3 v3 v3 Case 3 r2 r3 r2 r3 r2 r3 v3 v3 d1 v3 Case 1 Case 2 Case 4 9
10 Outine Introductions Probem Formuation Agorithm Experimenta Resuts Concusions 10
11 DSA Guiding Tempate Assignment with Redundant/Dummy Via Insertion (DRDV) Input Post-routing ayout Usabe DSA guiding tempates Optica resoution imit space v3 v5 v4 v6 Usabe DSA guiding tempates Post-routing ayout d s Optica resoution imit space 11
12 DSA Guiding Tempate Assignment with Redundant/Dummy Via Insertion (DRDV) Input Post-routing ayout Usabe DSA guiding tempates r3 Optica resoution imit space Output r1 r2 v3 Redundant via insertion for every via Guiding tempate assignment with suitabe dummy vias for every via and redundant via r4 v4 v5 r6 d1 v6 12
13 DSA Guiding Tempate Assignment with Redundant/Dummy Via Insertion (DRDV) Input Post-routing ayout Usabe DSA guiding tempates Optica resoution imit space Output Redundant via insertion for every via Guiding tempate assignment with suitabe dummy vias for every via and redundant via Constraints Inserted redundant vias shoud be ega The spacing between neighboring guiding tempate shoud arger than the optica resoution imit space Objectives Maximize the number (ratio) of inserted redundant vias Maximize the number (ratio) of patterned vias by DSA 13
14 Outine Introductions Probem Formuation Agorithm Experimenta Resuts Concusions 14
15 Soution Fow DSA Guiding Tempate Routing Layout Optica resoution imit spacing d s Preprocessing Find A Redundant/Dummy Via Candidates Detect Buiding Bocks Construct Confict Graph Loca Optima Sover Integer Linear Programming Formuation Initia Soution Generation Unconstrained Noninear Programming Sover Redundant/Dummy Via Insertion with Tempate Assignment 15
16 Preprocessing DSA Guiding Tempate Routing Layout Optica resoution imit spacing d s Preprocessing Find A Redundant/Dummy Via Candidates Detect Buiding Bocks Construct Confict Graph Loca Optima Sover Integer Linear Programming Formuation Initia Soution Generation Unconstrained Noninear Programming Sover Redundant/Dummy Via Insertion with Tempate Assignment 16
17 Redundant/Dummy Via Candidates Redundant via candidate It shoud be inserted next to every via. It shoud not overap with any meta wire from other nets of wires. Dummy via candidate It can make up a muti-hoe (not ess than three hoes) guiding tempate with other vias or redundant vias. It can improve the insertion rate or manufacture rate. Find a redundant/dummy via candidates for every via in time O(n). r2 r2 r1 17
18 Buiding-Bocks buiding-bock1: a origina via buiding-bock2: a redundant via buiding-bock3: a origina via and a redundant via buiding-bock4: two origina vias buiding-bock5: two redundant vias buiding-bock6: a origina via and a redundant via (diagona) buiding-bock7: two origina vias (diagona) buiding-bock8: two redundant vias (diagona) buiding-bock9: six origina/redundant vias
19 Combinations of Buiding-Bocks Combinations of buiding-bocks to form guiding tempates 19
20 Buiding-Bocks Detection & Confict Graph Confict graph CG (V, E ) vertex v V denotes a buiding-bock, e ij E is an edge and E = (E C E T ) E O. E C, E T and E O are the sets of confict edges, tempate edges and overap edges. r1 a b c d e f r1 r1 r1 c a b f d Confict edge Overap edge Tempate edge e 20
21 Confict Edges The distance between two buiding-bocks are ess than resoution imit space d s. a b c d e f r1 r1 r1 r1 c b d Confict edge Overap edge Tempate edge a e f f e r1 21
22 Overap Edges Two buiding-bocks are overapped. a b c d e f r1 r1 r1 r1 c b d f d r1 a f Confict edge Overap edge Tempate edge e 22
23 Tempate Edges If buiding-bocks i and j with e ij E C can be assigned to a guiding tempate without any design error. a b c d e f r1 r1 r1 c a r1 c a b f d r1 Confict edge Overap edge Tempate edge e 23
24 Soution Fow DSA Guiding Tempate Routing Layout Optica resoution imit spacing d s Preprocessing Find A Redundant/Dummy Via Candidates Detect Buiding Bocks Construct Confict Graph Loca Optima Sover Integer Linear Programming Formuation Initia Soution Generation Unconstrained Noninear Programming Sover Redundant/Dummy Via Insertion with Tempate Assignment 24
25 Constraints c r1 a c a b e f d f f e r1 d r1 E = ( E C E T ) E O Confict edge Tempate edge Overap edge 25
26 Confict Structure Constraint Tempate constraint If two buiding-bocks i and j are connected by a tempate edge, then they may be assigned to the same guiding tempate, but not necessariy. If both of buiding-bocks i and connect with k by tempate edges, then i, k, may not be assigned to a same guiding tempate. Confict structure (CS) Three bbocks i, k and, in which e ik and e k are tempate edges and there does not exist any edge between i and. i k i k i k 26
27 Integer Linear Programming (ILP) Objectives: Maximize the number of inserted redundant vias Maximize the number of patterned vias by DSA Let N v and N r are the numbers of incuded vias and redundant vias by buiding-bock i, and ILP Formuation (1) 27
28 Inequaity Constraints Caim 1. The ILP is equivaent to the DRDV probem. (1) Transfer inequaity constraints to equaity constraints. (2) 28
29 Equaity Constraints Reax equaity constraints to objective function. (2) (3) 29
30 Adjacent Matrix & CS Tensor Hande adjacent matrix and CS tensor. (3) (4)! "# = % 1, ( "# * 0, ( "# * 1, (2, 3, 4) -6 - "./ = 0 0, (2, 3, 4) -6 30
31 Unconstrained Noninear Programming (UNP) (4)! " = $ 1, ' " 0 0, ' " < = 2 = 4 = 6 = 8 = (5) 31
32 UNP Sover (5) Greedy seection method Wofe-Powe inexact ine search method 32
33 Loca Optima Convergence Lemma 1. Under above Equations, i w i g i 0. Theorem 1. Under above Equations, f(y) does not decrease. Coroary 1. Strict inequaity i w i g i >0 cannot be achieved. Theorem 2. Our UNP sover converges to a oca maximum. 33
34 Outine Introductions Probem Formuation Agorithm Experimenta Resuts Concusions 34
35 Patform Experimenta Settings C++ programming anguage Unix machine with Inte Core 2.70 GHz CPU and 8 GB memory ILP sover: CPLEX Benchmarks 11 circuits are provided by Prof. Fang, modified from MCNC benchmarks and an industry Faraday benchmarks Agorithms TCAD 17: DSA+RVI, ILP+Speed-up ASPDAC 17: DSA+RVI+DVI, ILP+Speed-up TVLSI 18: DSA+RVI+DVI, Two Stage MWIS Sover Ours: DSA+RVI+DVI, UNP Sover Indicators Manufacture rate, insertion rate, runtime 35
36 The Number of Vias The numbers of vias of benchmarks range from eight thousand to seventy thousand. 36
![Comparison: Manufacture Rate Compared with TCAD 17, ASPDAC 17, and TVLSI 18, our agorithm achieves 6%, 0%, and 3% improvement on manufacture rate. [TCAD 17] S.-Y. Fang, Y.-X. Hong, and Y.-Z.](/docs-images/88/115510423/images/37-0.jpg "Lu, Simutaneous guiding tempate optimization and redundant via insertion for directed sef-assemby, IEEE TCAD, 2017. [ASPDAC 17] C.-Y. Hung, P.-Y. Chou, and W.-K.")
37 Comparison: Manufacture Rate Compared with TCAD 17, ASPDAC 17, and TVLSI 18, our agorithm achieves 6%, 0%, and 3% improvement on manufacture rate. [TCAD 17] S.-Y. Fang, Y.-X. Hong, and Y.-Z. Lu, Simutaneous guiding tempate optimization and redundant via insertion for directed sef-assemby, IEEE TCAD, [ASPDAC 17] C.-Y. Hung, P.-Y. Chou, and W.-K. Mak, Optimizing DSA-MP decomposition and redundant via insertion with dummy vias, In Proc. of ASPDAC, [TVLSI 18] X. Li, B. Yu, J. Ou, J. Chen, D. Z. Pan and W. Zhu, Graph based redundant via insertion and guiding tempate assignment for DSA-MP, 37 IEEE TVLSI, 2018.
38 Comparison: Insertion Rate Compared with TCAD 17, ASPDAC 17, and TVLSI 18, our agorithm achieves 7%, 0%, and 2% improvement on insertion rate. 38
39 Comparison: Runtime Our agorithm is 3.99X and 13.32X faster than TCAD 17, ASPDAC
40 Outine Introductions Probem Formuation Agorithm Experimenta Resuts Concusions 40
41 Concusions We introduce a buiding-bock based manner instead of guiding tempate candidate to express soution. We proposed a genera ILP formuation and reaxed it to an UNP. Furthermore, we deveop a first-order optimization method to sove the UNP, which is a oca optima agorithm. Experimenta resuts verify our agorithm achieves comparabe experimenta resuts with a state-of-the-art work, and saves 92% runtime. 41
42 Hande Guiding Tempate Cost A buiding-bock woud be assigned to a guiding tempate. A guiding tempate composed of one or two buidingbocks. Assign proper weights to buiding-bock! " ( $ &) and corresponding tempate edge '! "( ( ) "( * + ). (1 ) 42
43 Hande Guiding Tempate Cost (2 ) (3 ) 43
44 Thank You! 44
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