Real-Time Image Generation with Simultaneous Video Memory Read/Write Access and Fast Physical Addressing

Transcription

1 Rea-Time Image Generation with Simutaneous Video Memory Read/rite Access and Fast Physica Addressing Mountassar Maamoun 1, Bouaem Laichi 2, Abdehaim Benbekacem 3, Daoud Berkani 4 1 Department of Eectronic, Bida University, Bida, Ageria 2 Department of Computer Science, USTHB, Agiers, Ageria. 3 LSIC Laboratory, (ENS Kouba, Agiers, Ageria 4 Signa & Communications Laboratory, (ENP, Agiers, Ageria Abstract: The present work is about an advanced architecture for generating video signas om microprocessor-based systems. This architecture is a soution for rea time image processing hardware/software systems which require a significant recording time and uses a reduced area of physica addressing of microprocessor-based systems. This soution investigates both the Fast Physica Addressing and the simutaneous video memory read-write system. This atter is ensured by a spit of the hardware video memory in separate capacities and by association of a seecting circuit. Key words: Video Image Generation, Fast Physica Addressing, Extended Physica Addressing, Simutaneous Video Memory Read/rite, Software/Hardware System, Microprocessor-based Systems. 1 Introduction The Fast Physica Addressing is an interfacing system which is aimed to reduce the use of physica addresses in microprocessor-based systems [1]. Furthermore, it wi improve the data exchange speed compared to the Extended Physica Addressing technique [2]. The above advantages are obtained by combining a software/hardware soution in order to create a new bus, made up of a data bus, an address bus and a contro bus. The hardware part of this interfacing is composed of a new bus and an interface between the system bus and the new bus. The software part ensures the communication between the microprocessor-based system and our interface. In this technique, we use the Direct Memory Access (DMA to increase the data exchange speed between the microprocessorbased system and our system. The simutaneous video memory read/write access represents a hardware/software soution [3] to enarge the recording access time. This soution consists in designing a dispay system which aows a simutaneous read/write access. The dispay system is composed of a hardware part and a software part. The hardware part is based on the memory capacity spit of the video RAM with separate buses and on the association of a simutaneous seecting circuit. The software part ensures the data transfer to the dispay system and the recording synchronization with the video RAM reading cyce. This paper is organized as foows: The main ines of the Extended Physica Addressing are exposed. After which, the Fast Physica Addressing is investigated. Next, in section five and six, the simutaneous access by two and severa eves are covered, after which a concusion is presented. 2 Extended Physica Addressing The Extended Physica Addressing is based on a mixed software/hardware architecture, which is intended to increase the addressing capacity of the computer and the microprocessor-based system [2]. In this system, we have used some addresses of the microprocessor-based system addressing area to address a arger externa memory capacity. The materia part of this system is made up of the new bus and the interface; it is situated between the system bus and the device being addressed by this technique. The input of this interface is connected to the microprocessor-based system bus, whereas the output, which is our new bus, is connected to the externa device. The new bus contains a data bus and an address bus, the basic idea of the hardware part is iustrated in figure 1.

2 AB: Address Bus. DB: Data Bus. NB: New Bus. SB: System Bus. Fig. 1 Extended Physica Addressing boc diagram. The mechanism of this technique can be described in two steps. First, the software ensures the avaiabiity of the data intended to be present on the new bus as addresses. The decoder enabes the D "LATCH" circuit to record these data and disabes the two data bus buffers unti they reach the second step. The address and data ines of the new bus wi be at the high impedance state. Second, the software ensures the avaiabiity of the data. The address decoder enabes the two bus buffers. The data vaues on the new bus are identica to the system data bus at this eve. The address vaues are identica to the first step data of the system bus. 3 Fast Physica Addressing This method uses the same technique of the data/address conversion, iustrated in the above section, for the address production of the new bus [1]. However, it uses a different process for the data transfer om the microprocessor-based system towards the input of the hardware part of the system. The input of the interface is connected to the microprocessor-based system bus and the output is connected to an externa device, as it is shown in Figure 2. In this version, the hardware part expores the Direct Memory Access for the data exchange, consequenty, the addresses on the new bus depends on the exchanged data of the microprocessor-based system memory. AB: Address Bus. DB: Data Bus. NB: New Bus. SB: System Bus. Fig. 2 Fast Physica Addressing boc diagram. The software part of Fast Physica Addressing ensures two additiona tasks. The first is to send the starting and ending positions of the accessibe memory area. The second is to contro the start and the end of the Direct Memory Access. The two positions of the memory area, which is addressed by the system, wi be sent to the Address Generator AG on the data bus of the system bus on distinct addresses. The DMA process of the system starts at these two data transfer. The address decoder enabes the recording of these two data in the address generator circuit of the DMA. Once the process of the Direct Memory Access is started, the address generator orders the address bus of the system bus to carry out the reading or the writing on the seected memory area and enabes the address decoder of the system to ensure both the decoding of the generated addresses and the distinction between the two types of data. 4 Image generation in the video card The image, which represents the video card output signas, is the resut of repeated readings of the video RAM with a Digita-to-Anaog conversion (DAC of the enabed data [4]. The maximum time for the writing on this RAM during the ame is given by the foowing reation.

3 T = T + T N (1 w r T : The time of return ame. T r : The time of return ine N : The number of ines within the ame The ratio of the writing time over the tota time of the video ame generay varies om 10% to 15% and can be written in the foowing form: r ( T + Tr N = (2 T f T f : The tota time of the ame. 5 Basic architecture of simutaneous access The image generation system with simutaneous access by two eves represents the basic architecture of our system. This dispay architecture uses a video RAM made up of two RAMs. Both RAMs can be seected separatey; one can be seected in reading and the second in writing and vice versa [5]. Figure 2 represents the bock diagram of the hardware part of this system. The hardware part of our system is composed of four units; Interface Unit, Seection Unit, Reading Unit and Digita-to-Anaog Conversion (DAC Unit. The Interface Unit uses the Fast Physica Addressing. The Seection Unit is connected to a the units and the video RAM. The Connection to the interface is made up of a status bus, a contro bus, an address bus and a data bus. The ink to the reading unit is made up of a contro bus and an address bus. The connection to the conversion unit is ensured by a one-way data bus which transfers the seection unit data to the conversion unit. In this architecture of simutaneous access, the ratio of the writing time over the tota time of the video ame varies om 100% to a minima vaue r2, where r2 is given by the foowing reation. 1 r r 2 = + (3 2 2 By using the reation (2, the expression of r2 coud be written in the foowing form: 1 ( T + Tr N r 2 = + (4 2 2T f Using the vaues of r of section 2, the ratio r2 varies om 55% to 57,5%. VIDEO SIGNALS Reading Unit DAC Unit Fast Physica Addressing Unit Seection Unit RAM 1 RAM 2 Fig 3. Two eves system bock diagram

4 Start Spit of Image Fie End of f1 RAM1 End of f2 RAM2 The software part is designed to carry out a process of permanent recording on the video RAM of this architecture. In the case of a simutaneous access by two eves, the image fie is spit up into two parts, fie f1 represents the higher part of the image and fie f2 the ower part. The software aows the switching between data of fie f1 and fie f2. The synchronization of data is reated to the seection state of RAMs in our system. Figure 3 iustrates the main fow chart of the software part. f1 data End of f1 f2 End f2 data Fig 4. Two eves system fow chart 6 Goba architecture of simutaneous access The principe of the image generation with simutaneous access by severa eves is simiar to the principe of two eves. In this dispay structure, our system uses a video RAM made up of severa RAMs. The figure represents the bock diagram of the hardware part of this system. It is made up of four units; Interface Unit, Seection Unit, Reading Unit and Digita-to-Anaog Conversion (DAC Unit. Reading Unit DAC Unit VIDEO SIGNALS RAM 1 Fast Physica Addressing Unit Seection Unit RAM 2 RAM N Fig 5. N eves system bock diagram

5 The connection between the units uses the same structure of the two eves system. The status bus size depends on the number of the used RAMs. The ink between the seection unit and the used RAMs is ensured by severa buses, each bus is composed of a data bus, an address bus and a contro bus. This architecture gives a ratio of the writing time over the tota time of the video ame that varies om 100% to a minima vaue rn. The ratio rn is given by the foowing form: 1 r = ( 1 (5 N N rn + N: Represents the number of RAMs. By using the reation (2, the expression of rn is written as: rn 1 ( T + Tr N = ( 1 + (6 N T N f By using the formua (6 and a vaue of r equas to 10%, rn takes severa vaues according to N. Tabe 1 gives rn as N varies om 1 to 100. The software part of the simutaneous access by severa eves spits up the image fie into severa parts. The resut gives N fies (f1, f2, f3..., fn with which the switching of data is done. The data synchronization is reated to the seection state of the N RAMs, which compose the video RAM of our system. Figure 5 presents the principa fow chart of the software part of the system at severa eves. Tabe 1: rn vaues N rn 10% 55% 70% 77,5% 82% 85% 87,1% 88,75% 90% N rn 95,5% 97% 97,75% 98,2% 98,5% 98,7% 98,87% 99% 99,1% Start Spit of Image Fie End of f1 End of f2 End of f3 End of fn RAM1 RAM2 RAM3 RAMN f1 data f2 data f3 data fn data End of f1 f2 f3. fn End Fig 6. N eves system fow chart

6 7 Concusion The principe of the images generation in the video cards connected to the microprocessor-based systems is generay used through repeated readings of the video memory contents. In this paper, we have shown the main guideines of the simutaneous access, using structures with both two eves and severa eve architectures. Furthermore, in the interfacing deveopment, the Fast Physica Addressing is investigated. The first practica tests have given a recording rate of 95% for the system of two eves and a rate of 98% for the system of three eves. Structures higher than three eves have given rates ower than that of three and two eves. This characteristic is due to the compexity of the circuitry and the software processing time that is significant for the severa eve systems. References: [1] M.Maamoun, A.Benbekacem, D.Berkani, A.Guessoum, Interfacing in Microprocessorbased Systems with a Fast Physica Addressing, The 3rd IEEE Internationa orkshop on System-on-Chip for Rea-Time Appications. Cagary, Aberta, Canada [2] M.Maamoun and G.Zerari, Adressage Matérie dans es Systèmes à Microprocesseur avec un Adressage Physique Etendu, 2001 IEEE Canadian Conference on Eectrica and Computer Engineering (CCECE01. IEEE Canada. Toronto, Ontario, Canada [3] G.F.Marchiro. Découpage Transformationne pour a Conception de Systèmes Mixtes Logicie/Matérie. Thèse de Doctorat. Institut Nationa Poytechnique de Grebe. France [4] Vijay K. Madisetti and Dougas B. iiams, Digita Signa Processing Handbook, CRC Press, [5] S.Raina. Emuation of a Virtua Shared Memory Architecture. PhD thesis. University of Bristo. September 1993.