Proceedings of the International Conference on Systolic Arrays, San Diego, California, U.S.A., May 25-27, 1988 AN EFFICIENT ASYNCHRONOUS MULTIPLIER!

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1 [1,2] have, in theory, revoutionized cryptography. Unfortunatey, athough offer many advantages over conventiona and authentication), such cock synchronization in this appication due to the arge operand sizes. to design that fast speeds and reasonabe area can be achieved. the key distribution since each user ) Proceedings of the nternationa Conference on Systoic Arrays, San Diego, Caifornia, U.S.A., May 25-27, 1988 AN EFFCENT ASYNCHRONOUS MULTPLER! systems have not been widey impemented to date. The reason for this ies not in their security, a decade of intensive cryptanaysis has given of confidence, but in the ack of fast hardware impementations. the We note that conventiona is a arge operand mutipier and divider. methods cannot eiminate the imitations on cock speed imposed by the arge operands required for the into are then used mutipier. FFO buffer. We generaize the basic ce used for and Rivest, Shamir and invented the most

2 need ony have one pair of keys, no matter how many peope are on the network. n conventiona cryptosystems every pair of users wishing to communicate must have a probem of impementing the encryption and decryption transformations. The simpe [1]. They are both moduar exponentiations using norma integer arithmetic. So, where e is the pubic encryption key. Simiary the message is recovered by raising exponentiations coud be performed in software with the program beow: C=1 the binary method above is aways cose to the best and definitey the simpest. From nteger mutipication and division (for taking the moduus) are we understood, and easiy impemented for operands up to 64 bits. However, for arger operands, such as optima. architecture offers the best asymptotic performance. Because of the widespread appication of these mutipiers there has recenty been great interest in finding the best architecture [11-13]. The traditiona approach has the mutipicand oaded in oading the mutipicand seriay is incuded. More recent systoic designs eiminate goba data ines and pipeine the mutipier from ce to ce resuting in faster achieve high speed moduar exponentiation. n an asynchronous wavefront design each eement handshakes with its nearest neighbors in order to ensure that data is passed correcty. The handshaking is done

3 with a ternary signa which communicates either true information (1), fase information other pieces of information is to make sure every eement in the chain does not accept its output have a spacer (X), and a its inputs have data (1 or 0) Simiary, an eement assumed by an eement. That is: 00 = acknowedge, reset or nu; 01 = data vaue ogica 0; 10 = data vaue ogica 1 ; 11 = not aowed. Since the nu state (00) can ony The basic buiding bock used for an asynchronous FFO is the Muer C-eement [5]. Figure 1 C11 Bock Diagram Tabe 1. C11 State Tabe 2. Figure 2 An asynchronous FFO

4 generaized C-eements. Using these eements eads to a faster and more area one output eement. Figure 3 shows our generaized C-eement performing the function F, with x inputs and the output (0) going to yother C-eements. a b Figure 3 CxyZ Bock Diagram no data (that is have spacers or 'be reset'). Simiary, for the output to be equa to reset, a x inputs must be reset and a y eements must have data. The above is iustrated in tabe 2 for a C22F eement F(OO) F(O) F(10) F() When both inputs have data (eg A=1 0 and 8=01), and the ces that have 0 as an input are reset (F). That is: 0=10 or 01 depending on f(01), where f(01) is the mapping F with 8=ogic

5 C11 described previousy, with the input being passed to the output as in a cocked C12 C C12 C '1' (B=01) and A=ogic '0' (A=10). When both inputs are reset (A=B=OO), and both the ces it feeds have data (ie Rand S are 01 or 10), then the output is reset (ie. 0=00). harder than when designing in singe rai ogic. is ony sighty architecture. described by Martin [8]. The gate outputs a nu (00) if either input is a nu, a high (01) simiar to the atch; but with extra ogic to aow for the outputs being fed to 2 and 3 other eements form the computationa heart of the from its three inputs (a,b and c) according to the mapping: gate to perform the mapping. with an additiona ogic C13 C13 C12 C12 Stages

6 t is approximatey 2 times faster than the equivaent systoic version at a cost of 4 times the area. Other ess obvious benefits benefits of the asynchronous approach are particuary important for arger operands RSA-PKC coud run at [1] D.E.Denning. "Cryptography and Data Security.", Addison Wesey, [4] J. Fortes EEE Computer, Vo.20, No.7, pp.12-17, Juy [7] A.L. Fisher & H.T. Kung. "Synchronizing Large VLS Arrays." Computers, pp , Aug Concept to mpementation." EEE Computer, Vo. 20, No.7, pp.18-33, Juy [10] J.A. Abraham et a. "Faut toerance Techniques for Systoic Arrays." EEE Computer, Vo. 20, No.7, pp , Juy output" EEE Tran. Computers, Vo.28, pp , October EEE Vo.36, pp , October 1987.

7 demonstrate the speed and area that coud be achieved using the generaized C-eement. There was no attempt to optimize the speed of the chip, through dynamic 40MHz, which is twice the speed of a simiary designed systoic version. From our impemented faster than an equivaent cocked systoic version previousy invoves one major ce design, with a few modifications, and requires no carefu cock distribution or cock buffer design !~5'";'.';'::;:c! f i f i: r r, f ' ' r f [. r!.. i, i - i