440GX Application Note

Transcription

1 ECC Overview for the PowerPC 440GP/GX January 18, 2008 Introduction The DDR SDRAM controller found on both the AMCC PowerPC 440GP and the PowerPC 440GX supports Error Checking and Correction (ECC) of memory data. The ECC function provides check bit generation on memory system write operations and checking and correcting on memory system reads. In order to activate the function, the memory system must contain an additional memory device to contain the 8 ECC check bits. In brief, to enable the ECC function and ensure correct functionality, the end user must perform the following steps, which are described in this application note. 1. Install an additional 8-bit-wide memory device. See Memory System Design on page Initialize the ECC-based memory system. See Initializing the ECC-Based Memory System on page Alter the timing of the memory system's read data path to accommodate the ECC time delay. See Timing Considerations on page Optionally, test the ECC-based memory system. This option is recommended. See Testing the ECC-Based Memory System on page 4. ECC Overview Error Checking and Correction (ECC) of memory data is controlled by two bits, MCHK, in the SDRAM0_CFG0 register. The ECC function can operate in three different modes: No ECC checking ECC generation without checking ECC generation and checking When enabled, these functions support the ECC process and allow testing of the memory system. Three additional registers (SDRAM0_BESR0, SDRAM0_BESR1, and SDRAM0_BEAR) are used to report ECC errors to the processor system. An interrupt vector can be used to vector off the application code or operating system to an error handling routine. ECC Process When writing data to the memory system, the DDR memory controller calculates an 8-bit-wide check value. The data and check value are then written to the memory system. When the data is read back into the controller, the ECC value of the read data is recalculated and then compared to the received ECC value. If the ECC values match, data is assumed to be correct and passed on to the PLB. If there is a single-bit or double-bit mismatch between the values, an ECC error is issued and an interrupt is usually posted. For more details about the ECC process, refer to the PowerPC 440GP User's Manual. Revision 1.01 Application Note (Proprietary) AN2009

2 SEC/DED Code The ECC function uses a dual 32-bit or 64-bit single-bit-error-correction/double-bit-error-detection (SEC/DED) code, depending on the memory interface width. In 64-bit mode, the DDR SDRAM controller implements a 64-bit data and 8-bit check interface on the memory. In 32-bit mode, the DDR SDRAM controller implements a dual 32-bit data, 8-bit check on the memory. (Basically, the 32-bit word is repeated to form a 64-bit double word and the ECC function is started. This provides SEC/DED coverage for each 32-bit word.) Memory System Design The following memory system requirements must be met before enabling the ECC function: The end user must install an additional 8-bit-wide memory device. The additional memory device (or devices) must be large enough to cover the entire memory system. If the memory system is DIMM-based, the memory system must use ECC-type DIMMs. These DIMMs contain the extra memory part to hold the ECC data. When designing a point-to-point or a discrete memory system, the end user must incorporate an additional 8-bit memory device to hold the ECC bits. Note: The memory controller does not support a mix of ECC and non-ecc memory systems. When ECC is disabled, or if ECC is enabled and ECC error checking and correction are disabled, no memory access error checking, correcting, or notification occurs. Enabling ECC on a Memory System The SDRAM0_CFG0 register contains two bits, MCHK, that control ECC functionality. These two bits are used to configure the memory system to perform ECC generation and no checking, enable ECC generation and checking, and to totally disable ECC checking and generation. The register settings that control ECC are shown in Table 1. Table 1: ECC Bit Settings SDRAM0_CFG0 bits 2:3 Meaning 00 No ECC checking 01 Reserved 10 Generate ECC values and do not check 11 Generate ECC values and check Before using the ECC function, the end user must initialize the ECC bits and alter the timing of the memory system s read data path to accommodate the ECC time delay. In addition, it is recommended that the end user also test the ECC-based memory system before using the ECC function. These actions are described in the following sections. 2 Application Note (Proprietary) Revision 1.01

3 Initializing the ECC-Based Memory System The memory system must be initialized with ECC values before a read of the system can occur. If the ECC function is enabled without initializing the memory array, the memory system will fail due to invalid ECC bits. The memory controller will generate ECC errors and issue enabled interrupts on the first data read operation. To initialize the ECC-based memory system, perform the following steps: 1. Initialize all DDR SDRAM-related configuration registers to the proper settings and timings. 2. Initialize the ECC portion of the SDRAM0_CFG0 register to perform ECC generation and no checking. 3. Write the entire memory array with either valid or dummy data. The memory array and ECC bits are now initialized. 4. Update the timing settings and read data path settings to support the timing changes needed to perform ECC checking properly. 5. Enable ECC generation and checking. The memory system is now ready to operate correctly. After initializing the ECC-based memory system, the end user must alter the timing of the memory systems read data path to accommodate the ECC function time delay. See Timing Considerations. Timing Considerations The ECC function takes approximately 4.0 ns to perform. This time delay is not present in non-ecc systems, so when ECC checking is active, the end user must alter the timing of the memory systems' read data path to accommodate this additional time delay. Changing the settings usually involves adjusting the path that data follows in the read data path. Usually, data must flow through all three stages of the read data path, which ensures that there is adequate time to perform the ECC function and deliver data to the PLB. Note: In some cases, it is possible to perform the ECC function one clock cycle earlier. However, the end user must perform a detailed timing budget analysis to see if there is enough time to do this. Revision 1.01 Application Note (Proprietary) 3

4 Testing the ECC-Based Memory System It is recommended that the end user simulate ECC errors in order to test the memory system's integrity. The occurrence of a single-bit error or an uncorrectable multi-bit error can be simulated by performing a series of memory accesses while varying the memory data error checking and testing bits in the (SDRAM0_CFG0[MCHK]) register. The end application and its intended environment should be used to determine the need and extent of testing. To test the ECC-based memory system, perform the following steps: 1. Initialize all DDR SDRAM-related configuration registers to the proper settings and timings. 2. Set up the Error detection interrupts and registers. 3. Initialize the ECC portion of the SDRAM0_CFG0 register to perform ECC generation and no checking. 4. Write the entire memory array with either valid or dummy data. The memory array and ECC bits are now initialized. 5. Turn off ECC generation. 6. Select test areas in the memory array. Change one or two bits of each data word in the test area. This will invalidate the ECC values already stored. 7. Update the timing settings and read data path settings to support the timing changes needed to perform ECC checking properly. 8. Enable ECC generation and checking. 9. Perform memory reads of the modified areas in the memory system to make sure that the errors are detected (both single-bit and double-bit) and, if possible, corrected (single-bit errors only). Conclusion The programmability of the PowerPC 440GP and the PowerPC 440GX DDR SDRAM controller enables the memory system to use the ECC function and to perform memory system testing and verification. To enable the ECC function and ensure correct functionality, the physical memory system must be designed to support ECC memory functions, and the read data path must be configured properly. In addition, the ECC-based memory system must be initialized and, optimally, tested. If the end user follows the steps presented in this application note, the end system will be able to detect both single-bit and double-bit memory errors and correct all single-bit errors. 4 Application Note (Proprietary) Revision 1.01

5 Document Revision History Revision Date Description v1.01 1/18/08 Converted layout to AMCC format. Revision 1.01 Application Note (Proprietary) 5

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